JP5974603B2 - Inductor array chip and DC-DC converter - Google Patents

Description

  The present invention relates to an inductor array chip and a DC-DC converter including the inductor array chip.

  Conventionally, a DC-DC converter is known as an element having a function of outputting power having a voltage different from input power (see, for example, Patent Document 1). The DC-DC converter described in Patent Document 1 includes an inductor chip provided with an inductor, and a control chip and a capacitor chip provided on the inductor chip.

Japanese Patent No. 4325747

  By the way, there is a demand for a DC-DC converter to output a plurality of types of power having different at least one of current and voltage from one input power. As a DC-DC converter in response to this demand, one having a plurality of conversion units can be considered. When the DC-DC converter is provided with a plurality of types of conversion units that differ in at least one of the voltage and current of the output power, it is necessary to vary the inductance value of the inductor for each conversion unit.

  For example, when using an inductor chip provided with an inductor as in the DC-DC converter described in Patent Document 1, it is conceivable to provide a plurality of types of inductors having different numbers of coiled conductors in one inductor chip. However, when a plurality of types of inductors having different numbers of laminated coil-shaped conductors are provided in one inductor chip, cracks are likely to occur in the magnetic layer laminate during firing of the inductor chip. For this reason, there is a problem that it is difficult to stably manufacture an inductor array chip provided with a plurality of types of inductors with different numbers of coiled conductors.

  The main object of the present invention is to provide an inductor array chip that is unlikely to crack during firing and that is easy to manufacture stably.

  An inductor array chip according to the present invention includes a magnetic layer stack and a plurality of inductors. The magnetic layer stack includes a plurality of stacked magnetic layers. The plurality of inductors are arranged in the magnetic layer stack. A plurality of inductors have mutually different inductance values. Each of the plurality of inductors includes a plurality of coiled conductors and a via hole conductor. The plurality of coiled conductors are respectively disposed between the magnetic layers. The via-hole conductor electrically connects a plurality of coiled conductors. In at least one of the plurality of inductors, the via-hole conductor electrically connects the plurality of coiled conductors so that the inductor has a plurality of inductor portions connected in parallel.

  In a specific aspect of the inductor array chip according to the present invention, the plurality of inductors includes a plurality of inductors having a plurality of inductor portions. In a plurality of inductors having a plurality of inductor portions, connection modes of the plurality of inductor portions are different from each other.

  In another specific aspect of the inductor array chip according to the present invention, in at least one of the plurality of inductors, at least two of the plurality of coiled conductors are connected in parallel.

  In another specific aspect of the inductor array chip according to the present invention, the plurality of inductors have the same number of coiled conductors.

  The DC-DC converter according to the present invention includes the inductor array chip according to the present invention.

  According to the present invention, it is possible to provide an inductor array chip that is unlikely to crack during firing and is easy to manufacture stably.

1 is a schematic circuit diagram of a DC-DC converter according to a first embodiment. 1 is a schematic plan view of a DC-DC converter according to a first embodiment. It is a typical sectional view of an inductor array chip in a 1st embodiment. 1 is a schematic exploded perspective view of a part of an inductor array chip in a first embodiment. 1 is a schematic equivalent circuit diagram of an inductor array chip in a first embodiment. It is a typical exploded perspective view of a part of inductor array chip in a 2nd embodiment. FIG. 6 is a schematic equivalent circuit diagram of an inductor array chip in a second embodiment. It is a typical top view of the inductor array chip in a 3rd embodiment. It is a typical top view of an inductor array chip in a 4th embodiment.

  Hereinafter, an example of the preferable form which implemented this invention is demonstrated. However, the following embodiment is merely an example. The present invention is not limited to the following embodiments.

  Moreover, in each drawing referred in embodiment etc., the member which has a substantially the same function shall be referred with the same code | symbol. The drawings referred to in the embodiments and the like are schematically described, and the ratio of the dimensions of the objects drawn in the drawings may be different from the ratio of the dimensions of the actual objects. The dimensional ratio of the object may be different between the drawings. The specific dimensional ratio of the object should be determined in consideration of the following description.

(First embodiment)
FIG. 1 is a schematic circuit diagram of a DC-DC converter according to the present embodiment. First, the circuit configuration of the DC-DC converter 1 will be described with reference to FIG.

  The DC-DC converter 1 has a plurality of conversion units. Specifically, the DC-DC converter 1 includes two conversion units 10a and 10b. The two conversion units 10a and 10b are connected to the same power source. Therefore, the voltage and current of power input to the conversion unit 10a are equal to the voltage and current of power input to the conversion unit 10b. At least one of current and voltage differs between the output power of the conversion unit 10a and the output power of the conversion unit 10b. Specifically, in the present embodiment, the power of the same input voltage Vin is input to each of the two conversion units 10a and 10b. The conversion unit 10a outputs power of the first output voltage Vout1. The conversion unit 10b outputs power of the second output voltage Vout2.

  The conversion units 10a and 10b include input terminals 11a and 11b, output terminals 12a and 12b, first ground terminals 13a and 13b, and second ground terminals 14a and 14b.

  Between the connection points 15a and 15b between the input terminals 11a and 11b and the output terminals 12a and 12b, and the connection points 16a and 16b between the first ground terminals 13a and 13b and the second ground terminals 14a and 14b, Input side capacitors 17a and 17b are connected. An output side capacitor is provided between the connection points 18a and 18b between the connection points 15a and 15b and the output terminals 12a and 12b, and the connection points 19a and 19b between the connection points 16a and 16b and the second ground terminals 14a and 14b. 20a and 20b are connected.

  The conversion units 10a and 10b have controllers 23a and 23b. The controllers 23a and 23b turn on / off between the connection points 15a and 15b and the connection points 21a and 21b, and connect to the connection points 21a and 21b between the connection points 15a and 15b and the connection points 18a and 18b. The points 16a and 16b and the connection points 22a and 22b between the connection points 19a and 19b are turned on / off. Specifically, the controllers 23a and 23b are connected to the first state in which the connection points 15a and 15b and the connection points 21a and 21b are turned on and the connection point 21a and the connection point 22a are turned off. The second state where the point 15a, 15b and the connection point 21a, 21b are turned off and the point between the connection point 21a and the connection point 22a is turned on is selectively switched.

  Inductors L1 and L2 are connected between the connection points 21a and 21b and the connection points 18a and 18b. As described above, the first output voltage Vout1 is different from the second output voltage Vout2. For this reason, the inductance value of the inductor L1 and the inductance value of the inductor L2 are different.

  Next, a specific configuration of the DC-DC converter 1 will be described mainly with reference to FIG. The DC-DC converter 1 includes an inductor array chip 40, an IC chip 30, and capacitor chips 31a, 31b, 32a, and 32b. The inductor array chip 40 constitutes the inductors L1 and L2 shown in FIG. The IC chip 30 and the capacitor chips 31a, 31b, 32a, and 32b are respectively disposed on the inductor array chip 40. The IC chip 30 constitutes controllers 23a and 23b. The capacitor chips 31a and 31b constitute input side capacitors 17a and 17b. The capacitor chips 32a and 32b constitute output side capacitors 20a and 20b.

  FIG. 3 is a schematic cross-sectional view of the inductor array chip 40 in the first embodiment. FIG. 4 is a schematic exploded perspective view of a part of the inductor array chip 40 in the first embodiment. In FIG. 4, the drawing of the magnetic layer constituting the outer layer portion of the inductor array chip 40 is omitted.

  As shown in FIGS. 3 and 4, the inductor array chip 40 includes a magnetic layer stack 41. The magnetic layer laminate 41 has a plurality of laminated magnetic layers 42. The magnetic layer 42 can be composed of, for example, a magnetic ceramic such as ferrite. The number of magnetic layers 42 constituting the magnetic layer stack 41 can be appropriately set according to the characteristics required for the inductor array chip 40. The number of magnetic layers 42 constituting the magnetic layer stack 41 can be, for example, about 8 to 12. The thickness of the magnetic layer 42 can also be appropriately set according to the characteristics required for the inductor array chip 40. The thickness of the magnetic layer 42 can be set to, for example, about 160 to 240 μm.

  Inductors L1 and L2 are provided in the magnetic layer laminate 41. Each of the inductors L1 and L2 includes a plurality of coiled conductors 43a and 43b and via-hole conductors 44a and 44b (see FIG. 4). The inductor L1 and the inductor L2 have the same number of coiled conductors 43a and 43b. However, in the present invention, it is not always necessary for the plurality of inductors to have the same number of coiled conductors. In FIG. 4, the via-hole conductors 44a and 44b are schematically drawn with broken lines.

  The coiled conductors 43a and 43b are disposed between the magnetic layers 42 adjacent in the thickness direction. The plurality of coiled conductors 43a and 43b are electrically connected by via-hole conductors 44a and 44b.

  The coiled conductors 43a and 43b and the via-hole conductors 44a and 44b can be made of an appropriate conductive material. The coiled conductors 43a and 43b and the via-hole conductors 44a and 44b can be made of, for example, a metal paste typified by silver or copper.

  As shown in FIGS. 5 and 4, at least one of the inductors L <b> 1 and L <b> 2 has a via-hole conductor electrically connecting a plurality of coiled conductors so that the inductor has a plurality of inductor portions connected in parallel. Connected.

  Specifically, the inductor L2 is configured by a single inductor unit. On the other hand, the inductor L1 has a plurality of inductor portions L1a and L1b. The inductor portion L1a and the inductor portion L1b are connected in parallel. The inductor portion L1a includes a plurality of coiled conductors 43a1 to 43a5 connected in series by a plurality of via-hole conductors 44a1 to 44a4. The inductor portion L1b includes a plurality of coiled conductors 43a6 to 43a10 connected in series by a plurality of via-hole conductors 44a5 to 44a8.

  Incidentally, when a plurality of inductors having different inductance values are provided in one inductor array chip, it is conceivable that the number of coil-shaped conductors is different among the plurality of inductors. That is, it is conceivable that the number of turns is different among a plurality of inductors. However, when the number of turns is made different among a plurality of inductors, portions including a conductive agent for constituting the coiled conductor and the via-hole conductor are unevenly distributed. The shrinkage rate at the time of firing differs between the portion containing the conductive agent for constituting the coiled conductor and the via-hole conductor and the magnetic green sheet for constituting the magnetic layer. For this reason, cracks are likely to occur during firing.

  On the other hand, in the inductor array chip 40, as described above, at least one of the plurality of inductors L1 and L2 includes the inductor portions L1a and L1b connected in parallel. By adopting such a configuration, the inductance value of the inductor L1 and the inductance value of the inductor L2 are made different. That is, by providing a coiled conductor connected in parallel in at least one of the plurality of inductors L1 and L2, the inductance value of the inductor L1 and the inductance value of the inductor L2 are made different. For this reason, the difference between the number of coiled conductors 43a included in the inductor L1 and the number of coiled conductors 43b included in the inductor L2 can be reduced. Therefore, the uneven distribution degree of the part containing the electrically conductive agent for comprising the coil-shaped conductors 43a and 43b and the via-hole conductors 44a and 44b is low. Therefore, the inductor array chip 40 is less likely to crack during firing and is easy to manufacture stably.

  Hereinafter, other examples of preferred embodiments of the present invention will be described. In the following description, members having substantially the same functions as those of the first embodiment are referred to by the same reference numerals, and description thereof is omitted.

(Second Embodiment)
FIG. 6 is a schematic exploded perspective view of a part of the inductor array chip in the second embodiment. FIG. 7 is a schematic equivalent circuit diagram of the inductor array chip in the second embodiment.

  The inductor array chip according to the second embodiment is different from the inductor array chip 40 according to the first embodiment in the configuration of the inductor L1. As shown in FIGS. 7 and 6, the inductor L1 includes inductor portions L1c to L1g. The inductor L1c and the inductor L1d are connected in parallel. The inductor L1c is configured by a coiled conductor 43a1. The inductor L1d is configured by a coiled conductor 43a2. The inductor L1f and the inductor L1g are connected in parallel. The inductor L1f is configured by a coiled conductor 43a9. The inductor L1g is configured by a coiled conductor 43a10. The inductor L1c and the inductor L1d, the inductor L1e, the inductor L1f and the inductor L1g are connected in series. The inductor L1e is composed of coiled conductors 43a3 to 43a8 connected in series by via-hole conductors 44a.

  Also in this embodiment, the same effect as the first embodiment is exhibited. As described above, the connection mode of the plurality of inductor sections constituting the inductor is not particularly limited as long as at least two inductor sections are connected in parallel.

  In the first and second embodiments, the example in which only one of the two inductors has a plurality of inductor portions has been described. However, the present invention is not limited to this configuration. For example, both of the two inductor units may have a plurality of inductor units. In that case, it is preferable that a plurality of inductors having a plurality of inductor portions have different connection modes of the plurality of inductor portions. For example, the inductor L1 in the first embodiment and the inductor L2 in the second embodiment may be provided in the inductor array chip.

(Third and fourth embodiments)
FIG. 8 is a schematic plan view of the inductor array chip in the third embodiment. FIG. 9 is a schematic plan view of the inductor array chip in the fourth embodiment.

  In the first embodiment, the example in which the DC-DC converter 1 includes the two conversion units 10a and 10b and the inductor array chip 40 includes the two inductors L1 and L2 has been described. However, the present invention is not limited to this configuration.

  For example, when the DC-DC converter includes three or more conversion units, the inductor array chip may be provided with three or more inductors. For example, when used in a DC-DC converter having four conversion units, four inductors L11, L12, L13, and L14 may be provided in the inductor array chip 40 as shown in FIG. For example, when used in a DC-DC converter having six conversion units, six inductors L21, L22, L23, L24, L25, and L26 may be provided on the inductor array chip 40 as shown in FIG. Good.

(Other embodiments)
In the plurality of inductors provided in the inductor array chip, at least one of the thickness (cross-sectional area), the number of turns, and the coil diameter of the coiled conductor may be different from each other. Here, the coil diameter of the coiled conductor is the inner diameter of the thickest portion of the coiled conductor width on a straight line passing through the center of the coiled conductor.

  Before firing, a cavity may be formed on at least one coiled conductor by providing a vanishing layer made of carbon or the like on at least one conductive paste layer for constituting the coiled conductor. . In that case, in the plurality of inductors, the number of coiled conductors having cavities provided thereon may be different. In other words, the inductance values of the inductors may be made different by changing the number of coil-shaped conductors on which the cavity is provided. Usually, the inductance value of an inductor becomes large, so that the number of the coil-shaped conductors in which the cavity was provided above increases.

  In the first embodiment, an example in which only one coiled conductor constituting one inductor is provided between adjacent magnetic layers has been described. However, the present invention is not limited to this configuration. For example, a plurality of coiled conductors constituting one inductor may be provided between adjacent magnetic layers. By doing so, for example, the number of coiled conductors included in the inductor can be changed and the inductance value can be changed while keeping the number of layers provided with the coiled conductors the same.

DESCRIPTION OF SYMBOLS 1 ... DC-DC converter L1, L2, L11-L14, L21-L26 ... Inductor L1a-L1g ... Inductor part 10a, 10b ... Convert part 11a, 11b ... Input terminal 12a, 12b ... Output terminal 13a, 13b ... 1st Ground terminals 14a, 14b ... Second ground terminals 15a, 15b, 16a, 16b, 18a, 18b, 19a, 19b, 21a, 21b, 22a, 22b ... Connection points 17a, 17b ... Input side capacitors 20a, 20b ... Output side Capacitors 23a, 23b ... Controller 30 ... IC chips 31a, 31b, 32a, 32b ... Capacitor chip 40 ... Inductor array chip 41 ... Magnetic layer stack 42 ... Magnetic layers 43a, 43b ... Coiled conductors 44a, 44b ... Via hole conductors

Claims (4)

A magnetic layer laminate having a plurality of laminated magnetic layers;
First and second inductors that are arranged in the magnetic layer stack and have different inductance values;
With
Each of the first and second inductors is
A plurality of coiled conductors disposed between the magnetic layers;
Via-hole conductors electrically connecting the plurality of coiled conductors;
Have
The first and second inductors have the same number of coiled conductors,
In at least one of the first and second inductors , the via-hole conductor electrically connects the plurality of coiled conductors so that the inductor has a plurality of inductor portions connected in parallel. Inductor array chip. The first, at least one second inductor have a first, second inductor section,
Before Symbol first connection mode of the second inductor section are different from each other, the inductor array chip according to claim 1. 3. The inductor array chip according to claim 1, wherein in at least one of the first and second inductors, at least two of the plurality of coiled conductors are connected in parallel. A DC-DC converter provided with the inductor array chip as described in any one of Claims 1-3 .

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