JP5969769B2 - Charge pump circuit and electronic device - Google Patents

Description

  The present invention relates to a charge pump circuit and an electronic device including the same.

  The charge pump circuit is well known as a circuit for boosting an input voltage. A semiconductor integrated circuit including a charge pump circuit is also known. In the case of a charge pump circuit formed on a semiconductor substrate, latch-up may occur due to the operation of a parasitic transistor.

  For example, Japanese Patent Laying-Open No. 2008-277832 (Patent Document 1) discloses a configuration of a charge pump circuit for preventing latch-up caused by the operation of a parasitic transistor. The charge pump circuit includes a first voltage generation unit, a second voltage generation unit, a third voltage generation unit, and a latch-up prevention unit. The latch-up prevention unit prevents the latch-up operation by the parasitic transistor until the signal output from the third voltage generation unit reaches a predetermined voltage level.

JP 2008-277832 A

  The charge pump circuit disclosed in Japanese Patent Laying-Open No. 2008-277832 (Patent Document 1) is configured to prevent a latch-up operation by a parasitic transistor without using an external Schottky diode. By not using an external Schottky diode, an increase in cost can be suppressed. However, there arises a problem that not only the configuration of the charge pump circuit is complicated, but also the control of the circuit is complicated.

  An object of the present invention is to make it possible to suppress a latch-up operation by a parasitic transistor while suppressing an increase in cost of a charge pump circuit.

  In one aspect of the present invention, a charge pump circuit includes a semiconductor substrate having a first region of a first conductivity type, and a transistor that transfers charges by switching according to a clock signal. The transistor includes a second region of the second conductivity type formed in the first region, a third region of the first conductivity type formed in the second region, and a second region. And a fourth region of the first conductivity type formed. The charge pump circuit further includes a Schottky diode that is formed outside the second region in the first region and clamps the voltage in the first region.

  Preferably, the Schottky diode is disposed between the second region and the fifth region of the second conductivity type. A voltage is applied to the fifth region independently of the second region.

  Preferably, when the semiconductor substrate is viewed in plan, the Schottky diode is formed along the outline of at least a part of the second region.

Preferably, the Schottky diode is divided into a plurality of elements.
In another aspect of the present invention, an electronic device includes a charge pump circuit and a circuit that operates using an output voltage of the charge pump circuit as a power supply voltage. The charge pump circuit includes a semiconductor substrate having a first region of a first conductivity type, and a transistor that transfers charges by switching according to a clock signal. The transistor includes a second region of the second conductivity type formed in the first region, a third region of the first conductivity type formed in the second region, and a second region. And a fourth region of the first conductivity type formed and electrically connected to the second region. The charge pump circuit further includes a Schottky diode that is formed outside the second region in the first region and clamps the voltage of the first region.

  According to the present invention, it is possible to suppress a latch-up operation by a parasitic transistor while suppressing an increase in cost of a charge pump circuit.

1 is a block diagram of an exemplary electronic device including a charge pump circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a schematic configuration of a charge pump circuit 1 shown in FIG. 1. FIG. 3 is a waveform diagram for explaining the operation of the charge pump circuit shown in FIGS. 1 and 2. FIG. 3 is a schematic cross-sectional view of a semiconductor chip on which the circuit shown in FIG. 2 is formed. It is the figure which showed the structure for preventing the latch-up by the charge pump circuit which concerns on embodiment of this invention. FIG. 6 is a schematic cross-sectional view of a semiconductor substrate for explaining a configuration example of the circuit shown in FIG. 5. It is the schematic sectional drawing which showed an example of the element formed with the Schottky diode D1. It is the figure which showed the example of the schematic plane layout of the Schottky diode shown in FIG. It is the figure which showed the outline of the planar layout of area | region A1 shown in FIG. It is the figure which showed the other example of the schematic planar layout of the Schottky diode shown in FIG. FIG. 7 is a diagram showing still another example of a schematic planar layout of the Schottky diode shown in FIG. 6. FIG. 7 is a diagram showing still another example of a schematic planar layout of the Schottky diode shown in FIG. 6.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a block diagram of an exemplary electronic device including a charge pump circuit according to an embodiment of the present invention. With reference to FIG. 1, the electronic apparatus 101 includes a display 102 and a circuit board 103. The charge pump circuit 1 and the driver 104 are mounted on the circuit board 103.

  The electronic device 101 is, for example, a mobile phone (including a smartphone), a tablet, a game machine, a PDA, a car audio, or the like, but is not limited thereto. The display 102 is, for example, a liquid crystal display. The circuit board 103 is, for example, a flexible printed board. The charge pump circuit 1 is a power supply circuit for the driver 104. The charge pump circuit 1 boosts the power supply voltage VDD and supplies the boosted voltage (voltage VGH) to the driver 104. The driver 104 drives the display 102 using the voltage VGH supplied from the charge pump circuit 1.

  FIG. 2 is a circuit diagram showing a schematic configuration of charge pump circuit 1 shown in FIG. Referring to FIG. 2, charge pump circuit 1 includes P channel MOS (Metal Oxide Semiconductor) transistors MP1 and MP2, a control circuit 3, an inverter 5, and capacitors C1 and C2. P-channel MOS transistors MP 1 and MP 2, control circuit 3, and inverter 5 are formed in semiconductor chip 2.

  P-channel MOS transistors MP1 and MP2 are charge transfer transistors. P-channel MOS transistors MP1 and MP2 are connected in series. The source of P-channel MOS transistor MP1 receives power supply voltage VDD. The drain of P channel MOS transistor MP1 is connected to the source of P channel MOS transistor MP2. The drain of P-channel MOS transistor MP2 is connected to terminal T1. The back gate of each P channel MOS transistor is connected to the drain of the P channel MOS transistor.

  A capacitor C1 is connected to the terminal T1. Capacitor C1 has one end connected to terminal T1 and the other end grounded. The voltage VGH is output from the terminal T1.

  The control circuit 3 generates a clock CLK having a predetermined cycle. Inverter 5 inverts clock CLK and outputs clock / CLK. Furthermore, the control circuit 3 controls the switching of each of the P channel MOS transistors MP1 and MP2.

  A connection point of the P-channel MOS transistors MP1 and MP2 is connected to one end of the capacitor C2 via the terminal T2. Clock / CLK is coupled to the other end of capacitor C2 via terminal T3.

  FIG. 3 is a waveform diagram for explaining the operation of the charge pump circuit shown in FIGS. 2 and 3, when the voltage of clock / CLK is VDD, the level of clock / CLK is H (high) level. On the other hand, when the voltage of clock / CLK is VS, the level of clock / CLK is L (low) level. For example, the voltage VS is a ground voltage.

  When clock / CLK is at L level, P-channel MOS transistor MP1 is in an on state and P-channel MOS transistor MP2 is in an off state. In this case, since the capacitor C1 is charged, the voltage V1 at the connection point of the P-channel MOS transistors MP1 and MP2 is equal to VDD.

  On the other hand, when clock / CLK is at the H level, P channel MOS transistor MP1 is in an off state and P channel MOS transistor MP2 is in an on state. In this case, since the voltage at the terminal T3 changes from the ground voltage to VDD, the voltage V1 changes from VDD to 2VDD. The voltage V1 is output through the P channel MOS transistor MP2 and the terminal T1. By repeating the above operation, a voltage VGH equal to 2VDD is output from the terminal T1.

  FIG. 4 is a schematic cross-sectional view of a semiconductor chip on which the circuit shown in FIG. 2 is formed. Referring to FIG. 4, P channel MOS transistors MP 1 and MP 2 are formed on a P type semiconductor substrate 10. Hereinafter, the configuration of the P-channel MOS transistor MP1 will be representatively described.

  P-channel MOS transistor MP 1 has an N-type well 11, P + regions 12 and 13, an N + region 14, and a gate electrode 15. P + regions 12 and 13 and N + region 14 are formed in N-type well 11. P + regions 12 and 13 are connected to the source electrode (S) and drain electrode (D) of P-channel MOS transistor MP1, respectively.

  A P + region 16 is formed on the surface of the semiconductor substrate 10. The voltages of the P + region 16 and the semiconductor substrate 10 are the substrate voltage (voltage Vsub). Further, an N-type well 17 separated from the N-type well 11 is formed in the semiconductor substrate 10. For example, N-type well 17 is a part of a P-channel MOS transistor included in control circuit 3 or inverter 5 shown in FIG. N + region 18 is formed in N-type well 17. A voltage Vb is applied to the N + region 18. The voltage Vb is, for example, the power supply voltage VDD or the ground voltage.

  When the charge pump circuit is started, the voltage of the drain (P + region 13) of the P-channel MOS transistor MP1 may be higher than the voltage of the back gate (N + region 14). In this case, the parasitic PNP transistor Tr1 formed by the P + region 13, the N-type well 11 and the semiconductor substrate 10 is turned on. As a result, a current Isub flows from the P + region 13 to the semiconductor substrate 10 through the N-type well 11.

  On the other hand, the N-type well 11, the semiconductor substrate 10 (and the P + region 16), and the N-type well 17 form a parasitic NPN transistor Tr 2. When the current Isub flows, the parasitic NPN transistor Tr2 may be turned on.

  As described above, in the charge pump circuit shown in FIG. 3, latch-up may occur due to the operations of the parasitic PNP transistor Tr1 and the parasitic NPN transistor Tr2. According to the configuration shown in FIG. 4, N-type well 17 is adjacent to P-channel MOS transistor MP1. However, even when the N-type well 17 is adjacent to the P-channel MOS transistor MP2, latch-up may occur due to the operations of the parasitic PNP transistor and the parasitic NPN transistor as described above.

  FIG. 5 is a diagram showing a configuration for preventing latch-up by the charge pump circuit according to the embodiment of the present invention. Referring to FIGS. 4 and 5, according to the embodiment of the present invention, Schottky diode D1 is connected to the base of parasitic NPN transistor Tr2 and the collector of parasitic PNP transistor Tr1. As described in detail later, the anode of Schottky diode D1 is connected to P + region 16. The cathode of the Schottky diode D1 is grounded. It is assumed that the emitter of the parasitic NPN transistor Tr2 is also grounded.

  The base voltage of the parasitic NPN transistor Tr2 is substantially equal to the substrate voltage (Vsub) of the semiconductor substrate 10. When the current Isub flows through the parasitic PNP transistor Tr1, the voltage Vsub is clamped to Vf by the Schottky diode D1. Vf is a forward voltage of the Schottky diode and is about 0.2V. If the base voltage of the parasitic NPN transistor Tr2 does not reach about 0.7V, the parasitic NPN transistor Tr2 is not turned on. Therefore, according to the configuration shown in FIG. 5, it is possible to prevent the parasitic NPN transistor Tr2 from being turned on. As a result, latch-up can be prevented.

  Conventionally, a Schottky diode is externally attached to a semiconductor circuit including a charge pump circuit. According to the embodiment of the present invention, the Schottky diode is included in the semiconductor device. Therefore, it is possible to suppress the latch-up operation by the parasitic transistor while suppressing an increase in the cost of the charge pump circuit.

  FIG. 6 is a schematic cross-sectional view of a semiconductor substrate for explaining a configuration example of the circuit shown in FIG. Referring to FIG. 6, Schottky diode D 1 is arranged between N-type well 11 and N-type well 17. A voltage is applied to the N-type well 11 and the N-type well 17 independently of each other. For example, when the charge pump circuit is activated, the N-type well 17 is grounded.

  The Schottky diode D1 includes an N-type well 20, an N + region 21, a P-type well 22, a P + region 23, and a silicide electrode 24. The N + region 21 and the P-type well 22 are formed in the N-type well 20. The P + region 23 is formed in the P-type well 22. The P-type well 22, the P + region 23, and the N-type well 20 are connected to the silicide electrode 24.

N + region 21 is grounded . The voltage of each of the P + regions 16 and 16A is Vsub . The sheet Risaido electrode 24, the voltage Vsub Ru given.

  Note that the Schottky diode D1 can be formed using a known semiconductor manufacturing technique. Furthermore, the Schottky diode D1 can be formed together with other elements. Therefore, even when the Schottky diode D1 is added to the configuration shown in FIG. 4, an increase in the number of manufacturing steps can be suppressed. Therefore, according to the embodiment of the present invention, an increase in the cost of the charge pump circuit can be suppressed.

  FIG. 7 is a schematic cross-sectional view showing an example of an element formed together with the Schottky diode D1. Referring to FIG. 7, the N-channel MOS transistor includes a P-type well 31 formed in a P-type semiconductor substrate 10, N + regions 32 and 33, a P + region 34, and a gate electrode 35.

  N + regions 32 and 33 are formed in the P-type well 22. The N + region 32 is connected to the drain electrode (D). The N + region 33 is connected to the source electrode (S). A P + region 23 is formed in the P-type well 22 in order to set the voltage of the P-type well 22 (back gate). Each of N + regions 32 and 33 and P + region 34 is in contact with silicide electrode 36.

  With reference to FIGS. 6 and 7, P-type well 31 is formed by a process in which P-type well 22 is formed. The N + regions 32 and 33 are formed by a process in which the N + regions 14, 18, and 21 are formed. The gate electrode 35 is formed by the step of forming the gate electrode 15. The silicide electrode 36 is formed by a process of forming the silicide electrode 24. The P region 34 is formed by the process of forming the P + regions 12, 13, 16, 16A.

  As described above, according to the embodiment of the present invention, the charge pump circuit transfers charges by switching according to the clock signal and the semiconductor substrate (10) having the first region of the first conductivity type. P-channel MOS transistors (MP1, MP2). In this embodiment, the “first region” is a region for forming an N-type well, that is, a P-type region. P-channel MOS transistors (MP 1 and MP 2) include an N-type well 11 formed in the first region and P + regions 12 and 13 formed in the N-type well 11. The N-type well 11 and the P + regions 12 and 13 correspond to a “second region”, a “third region”, and a “fourth region”, respectively. The N-type well 17 corresponds to a “fifth region”.

  The charge pump further includes a Schottky diode D1. The Schottky diode is formed outside the N-type well 11 in the first region of the semiconductor substrate 10. The Schottky diode D1 clamps the voltage in the first region.

  FIG. 8 is a diagram showing an example of a schematic plan layout of the Schottky diode shown in FIG. Referring to FIG. 8, P channel MOS transistor MP1 is arranged in the vicinity of the chip end.

  Of the regions around the P-channel MOS transistor MP1, the P + region 41 is formed in the region on the chip end side, but no other element is formed. Therefore, Schottky diode D1 is formed so as to surround three sides of the region where P channel MOS transistor MP1 is formed. In other words, the Schottky diode D1 is formed in a region excluding the region on the chip end side in the region around the P-channel MOS transistor MP1.

  A P + region 16 is formed between Schottky diode D1 and P channel MOS transistor MP1. Further, a P + region 16A is formed between Schottky diode D1 and N-type well 17. An N + region 18 is formed in the N-type well 17.

  The Schottky diode D1 includes a plurality of elements formed in the plurality of regions A1 to A7, respectively. The number of regions is not limited as shown in FIG. By dividing the Schottky diode D1 into a plurality of elements, the overall leakage current of the Schottky diode D1 can be reduced.

  Note that metal wiring (including silicide electrodes) is not shown in FIG. 8 in order to avoid complication of the figure. For the same reason, the metal wiring is omitted in the drawings described below.

  FIG. 9 is a diagram showing an outline of the planar layout of the region A1 shown in FIG. Referring to FIG. 9, an N-type well 20 is formed in region A1. An N + region 21 is formed in the N-type well 20. A P-type well 22 is formed inside a region surrounded by the N + region 21. A P + region 23 is formed in the P-type well 22. Each of the regions A2 to A7 has the same planar layout as the region A1.

  FIG. 10 is a diagram showing another example of a schematic planar layout of the Schottky diode shown in FIG. FIG. 10 is a diagram contrasted with FIG. Referring to FIG. 10, a region A11 corresponds to a region where a plurality of regions A1 to A7 are connected to each other.

  FIG. 11 is a diagram showing still another example of the schematic planar layout of the Schottky diode shown in FIG. FIG. 11 is a diagram contrasted with FIG. Referring to FIG. 11, another element is formed in a region around P channel MOS transistor MP1. In FIG. 11, the P-channel MOS transistor MP1 is sandwiched between N-type wells 17 and 17A. An N + region 18A is formed in the N-type well 17A.

  P + region 16 is formed so as to surround the four sides of P channel MOS transistor MP1. Schottky diode D1 is formed so as to surround P + region 16. Therefore, Schottky diode D1 is formed so as to surround the four sides of P-channel MOS transistor MP1. Specifically, the Schottky diode D1 is divided into a plurality of regions A21 to A30. Since the planar layout of each of the plurality of regions A21 to A30 is the same as the layout shown in FIG. 9, the following description will not be repeated.

  FIG. 12 is a diagram showing still another example of a schematic planar layout of the Schottky diode shown in FIG. FIG. 12 is a diagram contrasted with FIG. Referring to FIG. 12, a region A31 corresponds to a region where a plurality of regions A21 to A30 are connected to each other.

  In the planar layouts shown in FIGS. 8 and 10 to 12, P channel MOS transistor MP1 may be replaced with P channel MOS transistor MP2. As shown in FIG. 8 and FIG. 10 to FIG. 12, the Schottky diode D1 includes at least an N-type well region where the P-channel MOS transistor MP1 (or MP2) is formed when the semiconductor substrate is viewed in plan view. Formed along some contours.

  As described above, according to this embodiment, the charge pump circuit includes the Schottky diode that clamps the voltage of the semiconductor substrate 10. The Schottky diode is formed on the semiconductor substrate 10. As a result, the latch-up operation by the parasitic transistor can be suppressed while suppressing an increase in the cost of the charge pump circuit.

  Note that the transistor for transferring charges may be an N-channel MOS transistor. In this case, the conductivity type shown in FIG. 6 is replaced with a conductivity type opposite to the conductivity type. Even with this configuration, the Schottky diode that clamps the substrate voltage can prevent the charge pump circuit from being latched up.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  DESCRIPTION OF SYMBOLS 1 Charge pump circuit, 2 Semiconductor chip, 3 Control circuit, 5 Inverter, 10 Semiconductor substrate, 11, 17, 17A, 20 N type well, 12, 13, 16, 16A P + area | region, 15, 35 Gate electrode, 14, 18 , 18A, 21, 32, 33 N + region, 22, 31 P-type well, 24, 36 Silicide electrode, 101 Electronic device, 102 Display, 103 Circuit board, 104 Driver, A1-A7, A11, A21-A31 region, D1 Schottky diode, MP1, MP2 P channel MOS transistor, Tr1, Tr2 parasitic NPN transistor, T1-T3 terminals.

Claims (5)

A charge pump circuit,
A semiconductor substrate having a first region of a first conductivity type;
A transistor that transfers charges by switching according to a clock signal,
The transistor is
A second region of the second conductivity type formed in the first region;
A third region of the first conductivity type formed in the second region;
A fourth region of the first conductivity type formed in the second region,
The charge pump circuit
A Schottky diode formed outside the second region in the first region and clamping the voltage of the first region ;
The Schottky diode is disposed between the second region and the fifth region of the second conductivity type;
A voltage is applied to the fifth region independently of the second region ,
The Schottky diode is
A sixth region of the second conductivity type formed in the first region;
A seventh region of the first conductivity type formed in the sixth region,
The sixth region is electrically connected to ground;
The charge pump circuit , wherein the seventh region is connected to the same potential as the first region . The charge pump circuit according to claim 1, wherein the seventh region is connected to the same potential as the first region through a silicide electrode . Wherein when the semiconductor substrate is viewed in plane, the Schottky diode, the formed along at least a portion of the contour of the second region, a charge pump circuit according to claim 1 or claim 2. The Schottky diode is divided into a plurality of elements, a charge pump circuit according to any one of claims 1 to 3. The charge pump circuit according to any one of claims 1 to 4 ,
Ru and a circuit that operates using the output voltage of the charge pump circuit to the supply voltage, the electronic device.

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