JP5946566B2 - Scheduling method of hardware thread in multi-thread processor - Google Patents

Description

  More particularly, the present invention relates to a hardware thread scheduling method in a multithread processor having a thread scheduler that schedules the execution order of a plurality of hardware threads.

  In recent years, a multi-thread processor has been proposed in order to improve the processing capability of the processor. Multi-thread processors have threads that generate independent instruction streams. Then, the multi-thread processor executes arithmetic processing while switching which thread the instruction stream generated by the arithmetic circuit that processes the instruction by pipeline processing is processed. At this time, the multi-thread processor can process an instruction generated by another thread in another execution stage while executing an instruction generated by one thread in one execution stage in the pipeline. That is, in the arithmetic circuit of the multithread processor, instructions that are independent of each other are executed in different execution stages. As a result, the multi-thread processor reduces the time during which the execution stage of the pipeline does not process anything while smoothly processing each instruction stream, and improves the processing capacity of the processor.

  An example of such a multi-thread processor is disclosed in Patent Document 1. The multi-thread processor described in Patent Literature 1 includes a plurality of processor elements and a parallel processor control unit that switches threads of each processor element. The parallel processor control unit counts the execution time of the thread being executed in the processor element, outputs a timeout signal when the counted time reaches the thread allocation time, and holds it in the timeout signal and the execution order register. The thread to be executed by the processor element is switched based on the executed execution order information.

  As described above, in the multi-thread processor, the instruction circuit generated by which thread is processed in the arithmetic circuit is switched according to the schedule. An example of this red schedule method is disclosed in Patent Document 2. In the multi-thread processor described in Patent Document 2, a plurality of threads are cyclically executed for each time allocated to the threads. That is, in Patent Literature 2, each thread is executed at a predetermined execution time ratio by cyclically executing a fixed schedule.

  Another scheduling method for threads is disclosed in Patent Document 3. Patent Document 3 describes a round robin method and a priority method as thread scheduling methods. In the round robin method, the queued threads are selected and executed in order at regular intervals. For this reason, in the round robin method, threads in the queue are assigned to the CPUs at regular intervals and executed. In the priority method, threads are executed in the order of thread priority. More specifically, in the priority method, threads of each priority are queued in a queue provided for each priority, and threads are selected in order from the queue with the highest priority, assigned to the CPU, and executed. .

JP 2007-317171 A JP 2008-52750 A JP 2006-155480 A

  However, as a problem common to the round robin method and the priority method, there is a problem that the execution time of the thread cannot be set flexibly while guaranteeing the minimum execution time of the thread. For example, in the round robin method, when the number of threads increases, the execution time of each thread decreases evenly, and there is a problem that a sufficient execution time cannot be assigned to a high priority thread. In addition, the priority method has a problem that a thread with a low priority cannot be processed when processing of a thread with a high priority continues.

  One aspect of the multi-thread processor according to the present invention selects a plurality of hardware threads each generating an independent instruction stream and a hardware thread to be used in a next execution cycle from the plurality of hardware threads according to a schedule A thread scheduler that outputs a thread selection signal to be output, and a first one that selects any one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread A selector, and an arithmetic circuit that executes an instruction output from the first selector, wherein the thread scheduler is fixedly selected from the plurality of hardware threads in a first execution period Selecting at least one said hardware thread; The arbitrary hardware thread is selected in the execution period of 2, the ratio of the first execution period and the second execution period, and the ratio of the hardware thread executed in the first execution period are It is arbitrarily set by a management program executed by the arithmetic circuit.

  According to the multi-thread processor of the present invention, the hardware thread executed in the first execution period is executed regardless of the priority of other hardware threads. In addition, any hardware thread can be executed in the second execution period. Thereby, according to the multi-thread processor according to the present invention, the hardware thread for which the minimum execution time is desired to be guaranteed is defined in the first execution period, and an arbitrary value corresponding to the processing status at that time is defined in the second execution period Hardware threads can be defined.

  The multi-thread processor according to the present invention can flexibly set the execution time of the hardware thread while guaranteeing the minimum execution time of the hardware thread.

1 is a block diagram of a multithread processor according to a first embodiment; FIG. 3 is a block diagram of a thread scheduler according to the first exemplary embodiment. FIG. 3 is a schematic diagram illustrating a configuration of a slot according to the first embodiment. 3 is a flowchart showing an operation procedure at the time of starting the multi-thread processor according to the first exemplary embodiment; 6 is a table showing an operation of the thread scheduler according to the first embodiment. 3 is a timing chart showing an operation of the multithread processor according to the first exemplary embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a processor system including a multi-thread processor 1 according to the present embodiment. In the processor system according to the present embodiment, the multi-thread processor 1 and the memory 2 are connected via a system bus. Although not shown, it is assumed that other circuits such as an input / output interface are also connected to the system bus.

  First, the multithread processor 1 according to the present embodiment will be described. The multi-thread processor 1 includes a plurality of hardware threads. The hardware thread is composed of a circuit group such as a thread program counter, an instruction memory, a general-purpose register, and a control register (in the present embodiment, it is incorporated in the pipeline control circuit 16). The hardware thread is a system that generates an instruction stream including a series of instructions read from the instruction memory in accordance with an instruction fetch address output by a thread program counter built in the multi-thread processor 1. . That is, the instructions included in the instruction stream generated by one hardware thread are highly related to each other. In the present embodiment, the multi-thread processor 1 includes a plurality of thread program counters, so that the number of hardware threads corresponding to the number is mounted. Hereinafter, the multithread processor 1 will be described in more detail.

  As shown in FIG. 1, the multi-thread processor 1 includes an arithmetic circuit 10, an interrupt controller 11, a PC generation circuit 12, thread program counters TPC0 to TPC3, selectors 13 and 18, an instruction memory 14, an instruction buffer 15, and a pipeline control circuit 16. An instruction fetch controller 17 and a thread scheduler 19.

  The arithmetic circuit 10 executes arithmetic processing based on an instruction generated by the hardware thread selected by the selector 18. More specifically, the arithmetic circuit 10 includes an instruction decoder 21, an execution unit 22, and a data register 23. The instruction decoder 21 decodes the received instruction and outputs an operation control signal SC to the execution unit 22. The instruction decoder 21 outputs a data register address Radd indicating the data storage position based on the instruction decoding result. The execution unit 22 executes various calculations according to the calculation control signal SC. The execution unit 22 has a plurality of execution stages and performs operations by pipeline processing. The calculation result executed in the execution unit 22 is transmitted to the PC generation circuit 12, the memory 2, and the data register 23 according to the type of the calculation result. The data register 23 stores data used in the execution unit 22. The data register 23 outputs data at an address designated by the data register address Radd. In the example shown in FIG. 1, the data register 23 is configured to output data a and data b according to the data register address Radd. Further, the data register 23 stores the calculation result output by the execution unit 22 at an address specified by the data register address Radd.

  The interrupt controller 11 receives the interrupt request signal and outputs an interrupt instruction signal instructing execution of interrupt processing in the multithread processor 1. More specifically, when receiving the interrupt request signal, the interrupt controller 11 determines the interrupt factor, the priority of the interrupt processing, and the like, and performs the PC generation circuit 12 and the pipeline control so as to perform processing related to the interrupt factor. The circuit 16 is instructed to execute interrupt processing. This interrupt request is output from circuits other than the multithread processor 1 in addition to those output from the multithread processor 1.

  The PC generation circuit 12 receives a new program instruction signal input via the system bus, an interrupt instruction signal output from the interrupt controller 11, and a branch instruction signal output based on processing in the execution unit 22, and updates the program count. Generate a value. Then, the PC generation circuit 12 gives the program count update value to any one of the thread program counters TPC0 to TPC3. The PC generation circuit 12 also has a function of determining to which thread program counter the generated program count update value is to be given.

  The thread program counters TPC0 to TPC3 generate an address of the instruction memory 14 in which an instruction to be processed is stored (this address is referred to as an instruction fetch address IMadd). When the program count update value is given from the PC generation circuit 12, the thread program counters TPC0 to TPC3 update the instruction fetch address IMadd according to the program count update value. On the other hand, when no program count update value is input, the thread program counters TPC0 to TPC3 calculate addresses in ascending order and calculate the next consecutive instruction fetch addresses. In FIG. 1, the number of thread program counters is four, but the number of program thread counters can be arbitrarily set according to the specifications of the multi-thread processor.

  The selector 13 selects any one of the thread program counters TPC0 to TPC3 according to the thread designation signal output from the instruction fetch controller, and outputs the instruction fetch address IMadd output from the selected thread program counter. In the selector 13 shown in FIG. 1, numbers 0 to 4 are assigned to the input terminals, and these numbers indicate the numbers of hardware threads.

  The instruction memory 14 is a memory area that is commonly used by a plurality of hardware threads. The instruction memory 14 stores various instructions used in operations executed in the multithread processor 1. Then, the instruction memory 14 outputs an instruction specified by the instruction fetch address IMadd input via the selector 13. At this time, the instruction memory 14 determines which one of the thread program counters TPC0 to TPC3 is the instruction fetch address IMadd output by the selector 13, and distributes the output destination of the instruction according to the determination result. In the present embodiment, the instruction buffer 15 has instruction buffer areas BUF0 to BUF3 corresponding to the thread program counters TPC0 to TPC3. Therefore, the instruction memory 14 distributes the read instruction to one of the instruction buffer areas BUF0 to BUF3 according to the output source of the instruction fetch address IMadd. The instruction memory 14 may be a predetermined memory area included in the memory 2. The instruction buffer areas BUF0 to BUF3 are FIFO (First In First Out) type buffer circuits. The instruction buffer areas BUF0 to BUF3 may be divided into areas in one buffer or may be formed in separated areas.

  The pipeline control circuit 16 monitors the instruction stored at the head of the instruction buffer 15 and the instruction being executed in the execution unit 22. Then, when an interrupt instruction signal is input from the interrupt controller 11, the pipeline control circuit 16 instructs the instruction buffer 15 and the execution unit 22 to discard an instruction belonging to a hardware thread related to interrupt processing. Do.

  The instruction fetch controller 17 determines which hardware thread should be fetched according to the number of instructions stored in the instruction buffer 15, and outputs a thread designation signal based on the determination result. For example, if the number of instruction queues stored in the instruction buffer area BUF0 is smaller than the number of instruction queues stored in other instruction buffer areas, the instruction fetch controller 17 fetches an instruction belonging to the 0th hardware thread. A thread designation signal indicating the 0th hardware thread is output. Thereby, the selector 13 selects the thread program counter TPC0. Note that the instruction fetch controller 17 may determine a hardware thread to be selected by a round robin procedure.

  The selector 18 is a selector that functions as a first selector. The selector 18 selects any one of the instruction buffer areas BUF0 to BUF3 according to the thread selection signal TSEL output from the thread scheduler 19, and outputs the instruction read from the selected instruction buffer area to the arithmetic circuit 10. That is, the selector 18 selects one hardware thread from a plurality of hardware threads according to the thread selection signal TSEL, and outputs an instruction output from the selected hardware thread to the arithmetic circuit 10. In the selector 18 as well, numbers 0 to 4 are assigned to the input terminals, and these numbers indicate the numbers of hardware threads.

  The thread scheduler 19 outputs a thread selection signal TSEL that designates one hardware thread to be executed in the next execution cycle among the plurality of hardware threads in accordance with a preset schedule. In other words, the thread scheduler 19 manages in what order the plurality of hardware threads are processed according to the schedule, and selects the thread so that the instructions generated by the hardware threads are executed in the order according to the schedule. The signal TSEL is output. In the multithread processor 1 according to the present embodiment, this schedule is set by a management program executed immediately after the multithread processor 1 is activated.

  The multi-thread processor 1 according to the present embodiment is particularly characterized in the hardware thread scheduling method performed in the thread scheduler 19. Hereinafter, the thread scheduler 19 and the scheduling method will be described.

  FIG. 2 shows a block diagram of the thread scheduler 19. As illustrated in FIG. 2, the thread scheduler 19 includes a second selector (for example, a selector 30), a first scheduler 31, and a second scheduler 32. The selector 30 selects one of the thread number A output from the first scheduler 31 and the thread number B output from the second scheduler 32 according to the signal level of the real-time bit signal, and selects the selected thread. The number is output as a thread selection signal TSEL. The thread number indicated in the thread selection signal TSEL becomes the hardware thread number to be executed in the next execution cycle.

  The first scheduler 31 outputs a selection signal (for example, a real-time bit signal) for switching between the first execution period and the second execution period, and the real-time bit signal specifies the first execution period. A first hardware thread number (for example, thread number A) that specifies a hardware thread to be executed in a predetermined execution order in a certain period is output. Here, the first execution period is a period in which a real-time bit signal described later is 1, and the second execution period is a period in which a real-time bit signal described later is 0. In the first execution period, the hardware thread number to be selected is set in advance, and in the second execution period, the hardware thread number to be selected is arbitrarily set by the second scheduler 32, for example. Is set. The first scheduler 31 includes a thread control register 33, a counter 34, a count maximum value storage unit 35, a coincidence comparison circuit 36, and a third selector (for example, a selector 37).

  The thread control register 33 includes a plurality of slots (for example, slots SLT0 to SLT7). The structure of this slot is shown in FIG. As shown in FIG. 3, each of the slots SLT0 to SLT7 has a number storage unit that stores a hardware thread number and a period attribute setting flag that determines the logical level of the real-time bit signal when the slot is selected. And a real-time bit storage unit to be stored.

  The counter 34 updates the count value CNT at a predetermined interval. More specifically, the counter 34 in the present embodiment counts up the count value CNT in synchronization with an operation clock of the multi-thread processor 1 (not shown). The maximum count value storage unit 35 stores a maximum count value CNTM that defines an upper limit value of the count value CNT of the counter 34. The coincidence comparison circuit 36 compares the count value CNT with the maximum count value CNTM, and outputs a reset signal RST that resets the count value of the counter 34 when the count value CNT matches the maximum count value CNTM. That is, the counter 34 outputs the count value CNT whose value is cyclically updated by repeating the count-up operation while initializing the count value CNT at a predetermined cycle.

  The selector 37 selects one of the slots in the thread control register 33 according to the count value CNT, and outputs a real time bit signal and a thread number A based on the value stored in the selected slot. More specifically, if the count value CNT is 0, the selector 37 selects the slot SLT0, sets the hardware thread number stored in the number storage unit of the slot SLT0 as the thread number A, and the real time bit of the slot SLT0. The value of the period attribute setting flag stored in the storage unit is set as the logical level of the real time bit signal.

  Note that the value stored in the slot of the thread control register 33 of the first scheduler 31, the initial value of the count value CNT of the counter 34, and the maximum count value CNTM of the count maximum value storage unit 35 are determined when the multi-thread processor 1 is started up. Set by the management program to be executed. The management program reads these setting values from the memory 2.

  The second scheduler 32 selects an arbitrary hardware thread in accordance with, for example, a round robin method or a priority method procedure. The hardware thread number output by the second scheduler 32 is referred to as thread number B.

  Next, the operation of the multithread processor 1 using the thread scheduler 19 will be described. FIG. 4 is a flowchart showing a procedure of operations from when the multi-thread processor 1 is powered on until the start of normal processing. As shown in FIG. 4, when the power is turned on, the multi-thread processor 1 first initializes the circuit state by hardware reset (step S1). Subsequently, the multi-thread processor 1 starts operation in the single thread mode (step S2). In this single thread mode, for example, the thread program counter TPC0, the instruction memory 14, and the instruction buffer area BUF0 are activated, and the other thread program counters TPC1 to TPC3 and the instruction buffer areas BUF1 to BUF3 stand by in a standby state.

  Then, the multithread processor 1 reads the management program from the memory 2 or another storage device (not shown) and executes the management program (step S3). Thereafter, according to the management program, the multi-thread processor 1 sets a value in a slot in the thread control register 33 (step S4), initializes a count value CNT of the counter 34 (step S5), and sets a count maximum value CNTM ( Step S6) is performed. When the setting of these various registers is completed, the multithread processor 1 starts operating in the multithread mode (step S7). In this single thread mode, for example, the thread program counters TPC0 to TCP3, the instruction memory 14, and the instruction buffer areas BUF0 to BUF3 are activated. Then, the multi-thread processor 1 starts normal operation in the multi-thread mode.

  Next, the operation of the multithread processor 1 after the start of normal operation will be described. In the following description, the operation of the thread scheduler 19 will be described in particular. In the following description, as an example of setting, the initial value of the count value CNT of the counter 34 is 0, and the maximum count value CNTM is 4. Each value of the slot of the thread control register 33 is set to 1 for the real time bits of the slots SLT0 to SLT2, SLT4, SLT5, and SLT7, and to 0 for the real time bits of the slots SLT3 and SLT6. Furthermore, the hardware thread number of the slots SLT0, SLT2, SLT5, and SLT7 is 0, the hardware thread number of the slots SLT1 and SLT4 is 1, and the hardware thread number of the slot SLT3 is 2.

  The table of FIG. 5 shows the hardware thread numbers selected by the thread selection signal TSEL output from the thread scheduler 19 under the above conditions. In the table of FIG. 5, one timing for switching the hardware thread selected by the thread scheduler 19 is defined as one time, and how the thread selection signal TSEL is switched over time.

  As shown in FIG. 5, when the count value CNT at time t1 is first 0, the selector 37 selects the slot SLT0. Therefore, the selector 37 sets the logic level of the real-time bit signal to 1 and sets the thread number A to 0. As a result, the selector 30 outputs the thread number A, 0, as the thread selection signal TSEL.

  Subsequently, at time t2, the count value CNT is incremented to 1. Therefore, the selector 37 selects the slot SLT1. Accordingly, the selector 37 sets the logic level of the real-time bit signal to 1 and sets the thread number A to 1. As a result, the selector 30 outputs the thread number A No. 1 as the thread selection signal TSEL.

  Next, at time t3, the count value CNT is incremented to 2. Therefore, the selector 37 selects the slot SLT2. Therefore, the selector 37 sets the logic level of the real-time bit signal to 0 and sets the thread number A to 1. As a result, the selector 30 outputs a hardware thread number (for example, n) output as the thread number B as the thread selection signal TSEL.

  Next, at time t4, the count value CNT is counted up to 3. Therefore, the selector 37 selects the slot SLT3. Therefore, the selector 37 sets the logic level of the real time bit signal to 1 and sets the thread number A to 2. As a result, the selector 30 outputs the thread number A No. 2 as the thread selection signal TSEL.

  Next, the count value CNT is counted up to 4 at time t5. Therefore, the selector 37 selects the slot SLT4. Accordingly, the selector 37 sets the logic level of the real-time bit signal to 1 and sets the thread number A to 1. As a result, the selector 30 outputs the thread number A No. 1 as the thread selection signal TSEL.

  Since the count value CNT reaches the maximum count value CNTM at time t5, the count value CNT is reset after time t6 has elapsed. As a result, the thread scheduler 19 during the period from time t6 to t10 repeats the operation from time t1 to t5. In the multi-thread processor 1. A cycle in which the count value CNT is reset is defined as one cycle of the thread selection process.

  Next, FIG. 6 shows a timing chart of the operation of the multi-thread processor 1 based on the thread selection signal TSEL output from the thread scheduler 19. The hardware thread and time selected in FIG. 6 are based on the thread selection signal TSEL and time described in FIG.

  As shown in FIG. 6, the multi-thread processor 1 executes the instruction 0 belonging to the 0th hardware thread in order to select the 0th hardware thread whose thread selection signal TSEL is at the time t1. Next, at time t2, since the thread selection signal TSEL selects the first hardware thread, the instruction 0 belonging to the first hardware thread is executed. Next, at time t3, the thread selection signal TSEL selects an arbitrary hardware thread (for example, n) selected by the second scheduler 32, and therefore the instruction 0 belonging to the nth hardware thread is executed. Next, at time t4, since the thread selection signal TSEL selects the second hardware thread, the instruction 0 belonging to the second hardware thread is executed. Next, at time t5, since the thread selection signal TSEL selects the first hardware thread, the instruction 1 belonging to the first hardware thread is executed. Then, the multi-thread processor 1 ends one thread selection cycle when the time t5 elapses, and starts the next thread selection processing cycle.

  In the next thread selection processing cycle (time t6 to t10), the hardware thread is selected in the same order as the cycle of time t1 to t5, but the instruction processed in the selected hardware thread is the previous cycle. It becomes the instruction group that continues.

  For example, at time t6, the thread selection signal TSEL selects the 0th hardware thread, so the instruction 1 belonging to the 0th hardware thread is executed. Next, at time t7, since the thread selection signal TSEL selects the first hardware thread, the instruction 2 belonging to the first hardware thread is executed. Next, at time t8, since the thread selection signal TSEL selects an arbitrary hardware thread (for example, n) selected by the second scheduler 32, the instruction 1 belonging to the nth hardware thread is executed. Next, at time t9, since the thread selection signal TSEL selects the second hardware thread, the instruction 1 belonging to the second hardware thread is executed. Next, at time t10, since the thread selection signal TSEL selects the first hardware thread, the instruction 3 belonging to the first hardware thread is executed.

  As described above, when the hardware thread to be cyclically selected by the thread scheduler 19 is switched, the execution time of the hardware thread processed in one thread selection processing cycle becomes a predetermined ratio. In the example shown in FIG. 6, the first hardware thread is executed once, the first hardware thread is executed twice, and the second hardware thread is executed once in the first execution period. In addition, any (nth) hardware thread is executed once in the second execution period. That is, the ratio of the processor occupation time between the first execution period and the second execution period is 80:20. The 0th hardware thread secures at least 20% processor occupation time, the 1st hardware thread secures at least 40% processor occupation time, and the 2nd hardware thread at least 20% processor. Ensure occupation time. In addition, during the 20% processor occupation time allocated as the second execution period, an arbitrary hardware thread corresponding to the thread processing status in the multi-thread processor 1 is executed.

  From the above description, in the multi-thread processor 1 according to the present embodiment, the hardware thread preset by the thread scheduler 19 in the preset order in the first execution period in which the logical level of the real-time bit signal is 1. In the second execution period in which the logic level of the real-time bit signal is 0, an arbitrary hardware thread is selected. Thereby, the multi-thread processor 1 guarantees the minimum time of the processor occupation time of the hardware thread selected in the first execution period. Further, by selecting an arbitrary hardware thread in the second execution period, the multi-thread processor 1 can increase the processor occupation time of an arbitrary hardware thread according to the processing status.

  In the multithread processor 1 according to the present embodiment, the ratio between the first execution period and the second execution period and the ratio of hardware threads executed during the first execution period are determined by the management program. It can be set arbitrarily. That is, a flexible hardware thread selection method can be obtained by changing the value to the slot in the thread control register 33 and the value of the maximum count value CNTM set by the management program according to the processing request to the multi-thread processor 1. It becomes possible to choose. More specifically, it is possible to select a hardware thread to be executed during the first execution time by changing the value of the real time bit of the slot in the thread control register 33 and the value of the hardware thread number. In addition, the ratio between the first execution time and the second execution time can be changed. Also, the length of one thread selection processing cycle can be changed depending on what value is set for the maximum count value CNTM.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the thread scheduling method in the second scheduler can be appropriately changed according to the specifications of the multi-thread processor.

DESCRIPTION OF SYMBOLS 1 Multithread processor 2 Memory 10 Arithmetic circuit 11 Interrupt controller 12 PC generation circuit 13, 18, 30, 37 Selector 14 Instruction memory 15 Instruction buffer 16 Pipeline control circuit 17 Instruction fetch controller 19 Thread scheduler 21 Instruction decoder 22 Execution unit 23 Data Register 31 First scheduler 32 Second scheduler 33 Thread control register 34 Counter 35 Count maximum value storage unit 36 Match comparison circuits a and b Data BUF0 to BUF0 Instruction buffer area IMadd Instruction fetch address Radd Data register address SC Operation control signal TSEL Thread selection signal CNT Count value CNTM Count maximum value RST Reset signal SLT0 to SLT7 Slot TPC0 to TCP3 Thread Program counter

Claims (5)

A hardware thread scheduling method in a multi-thread processor that has a plurality of hardware threads and executes an instruction stream generated by the hardware thread while switching the hardware thread according to a predetermined schedule,
The multi-thread processor is:
A thread scheduler that outputs a thread selection signal for selecting a hardware thread to be used in a next execution cycle among the plurality of hardware threads;
A selector that selects any one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread;
Have
The thread scheduler
A thread control register including a plurality of slots in which each slot holds first information and the first information can be rewritten;
Storing second information for designating one of the plurality of slots, and rewriting the second information;
Further comprising
Selecting a slot sequentially from a first slot of the plurality of slots of the thread control register;
When the second slot designated by the second information is selected from the plurality of slots, the slot is returned to the first slot and the slots are sequentially selected again.
Based on the first information held by the sequentially selected slots, let the selector select a hardware thread,
A method of scheduling a hardware thread in a multi-thread processor in which a length of a thread selection process from the first slot until the second slot is selected can be changed by rewriting the second information.   The multiplicity according to claim 1, wherein the first information and the second information are set in the slot and the storage unit by a management program executed by an arithmetic circuit that executes an instruction output from the selector. A method of scheduling hardware threads in a thread processor.   The thread scheduler counts up a count value indicating the slot number at a predetermined period, and the counter is reset when the count value reaches the value indicated by the second information A hardware thread scheduling method in a multi-thread processor according to claim 1, comprising:   The hardware thread scheduling method for a multithread processor according to any one of claims 1 to 3, wherein the first information includes a hardware thread number.   The hardware thread scheduling method in the multithread processor according to claim 2, wherein the management program is executed after the multithread processor is started.

Images