JP5536862B2 - Multithreaded processor - Google Patents

Description

  The present invention relates to a multithread processor according to the present invention, and more particularly to a multithread processor having a thread scheduler that schedules the execution order of a plurality of hardware threads.

  In recent years, a multi-thread processor has been proposed in order to improve the processing capability of the processor. Multi-thread processors have threads that generate independent instruction streams. Then, the multi-thread processor executes arithmetic processing while switching which thread the instruction stream generated by the arithmetic circuit that processes the instruction by pipeline processing is processed. At this time, the multi-thread processor can process an instruction generated by another thread in another execution stage while executing an instruction generated by one thread in one execution stage in the pipeline. That is, in the arithmetic circuit of the multithread processor, instructions that are independent of each other are executed in different execution stages. As a result, the multi-thread processor reduces the time during which the execution stage of the pipeline does not process anything while smoothly processing each instruction stream, and improves the processing capacity of the processor.

  An example of such a multi-thread processor is disclosed in Patent Document 1. The multi-thread processor described in Patent Literature 1 includes a plurality of processor elements and a parallel processor control unit that switches threads of each processor element. The parallel processor control unit counts the execution time of the thread being executed in the processor element, outputs a timeout signal when the counted time reaches the thread allocation time, and holds it in the timeout signal and the execution order register. The thread to be executed by the processor element is switched based on the executed execution order information.

  As described above, in the multi-thread processor, the instruction circuit generated by which thread is processed in the arithmetic circuit is switched according to the schedule. An example of this red schedule method is disclosed in Patent Document 2. In the multi-thread processor described in Patent Document 2, a plurality of threads are cyclically executed for each time allocated to the threads. That is, in Patent Literature 2, each thread is executed at a predetermined execution time ratio by cyclically executing a fixed schedule.

  Another scheduling method for threads is disclosed in Patent Document 3. Patent Document 3 describes a round robin method and a priority method as thread scheduling methods. In the round robin method, the queued threads are selected and executed in order at regular intervals. For this reason, in the round robin method, threads in the queue are assigned to the CPUs at regular intervals and executed. In the priority method, threads are executed in the order of thread priority. More specifically, in the priority method, threads of each priority are queued in a queue provided for each priority, and threads are selected in order from the queue with the highest priority, assigned to the CPU, and executed. .

JP 2007-317171 A JP 2008-52750 A JP 2006-155480 A

  However, as a problem common to the round robin method and the priority method, there is a problem that the execution time of the thread cannot be set flexibly while guaranteeing the minimum execution time of the thread. For example, in the round robin method, when the number of threads increases, the execution time of each thread decreases evenly, and there is a problem that a sufficient execution time cannot be assigned to a high priority thread. In addition, the priority method has a problem that a thread with a low priority cannot be processed when processing of a thread with a high priority continues.

  According to one aspect of the multi-thread processor according to the present invention, a plurality of hardware threads each generating an independent instruction stream, and a priority set in advance for each of the plurality of hardware threads, A first thread scheduler that designates a hardware thread selected in the next execution cycle among the plurality of hardware threads, and selects one of the plurality of hardware threads according to the designation, and selects the selected hardware thread. An arithmetic circuit that executes an instruction generated by a wear thread, wherein the first thread scheduler preferentially selects the hardware thread having a high priority, and the selected hardware thread Each time the generated instruction is executed in the arithmetic circuit, it is executed. The priority of the hardware thread that generated the instruction is updated, and at least one other hardware thread is selected until the priority of the hardware thread with the highest priority becomes the lowest. is there.

  According to the multi-thread processor of the present invention, the priority of the executed hardware thread is updated, and the hardware thread to be selected next is determined according to the updated priority. As a result, it is possible to prevent a predetermined hardware thread from being fixedly selected.

  The multi-thread processor according to the present invention can flexibly set the execution time of the hardware thread while guaranteeing the minimum execution time of the hardware thread.

1 is a block diagram of a multithread processor according to a first embodiment; FIG. 3 is a block diagram of a thread scheduler according to the first exemplary embodiment. FIG. 2 is a block diagram of a dispatch counter according to the first exemplary embodiment. FIG. 3 is a diagram illustrating an example of an instruction group executed in the multithread processor according to the first embodiment; FIG. 5 is a diagram illustrating a processing flow of instructions when a mask signal is not used in the multithread processor according to the first embodiment. FIG. 6 is a diagram illustrating a processing flow of instructions when a mask signal is used in the multithread processor according to the first embodiment. 4 is a flowchart showing an operation procedure when the multithread processor according to the first embodiment is started up; 3 is a flowchart illustrating an operation procedure of the thread scheduler according to the first embodiment; 6 is a table showing an operation of the thread scheduler according to the first embodiment. 6 is a table showing an operation of the thread scheduler according to the first embodiment. FIG. 3 is a block diagram of a multi-thread processor according to a second exemplary embodiment. FIG. 6 is a block diagram of a thread scheduler according to a second embodiment. FIG. 10 is a schematic diagram illustrating a configuration of slots in a second thread scheduler according to the second embodiment; 10 is a table showing an operation of a second thread scheduler according to the second exemplary embodiment. 10 is a table showing the operation of the thread scheduler according to the second embodiment.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a processor system including a multi-thread processor 1 according to the present embodiment. In the processor system according to the present embodiment, the multi-thread processor 1 and the memory 2 are connected via a system bus. Although not shown, it is assumed that other circuits such as an input / output interface are also connected to the system bus.

  First, the multithread processor 1 according to the present embodiment will be described. The multi-thread processor 1 includes a plurality of hardware threads. The hardware thread is composed of a circuit group such as a thread program counter, an instruction memory, a general-purpose register, and a control register (in the present embodiment, it is incorporated in the pipeline control circuit 16). The hardware thread is a system that generates an instruction stream including a series of instructions read from the instruction memory in accordance with an instruction fetch address output by a thread program counter built in the multi-thread processor 1. . That is, the instructions included in the instruction stream generated by one hardware thread are highly related to each other. In the present embodiment, the multi-thread processor 1 includes a plurality of thread program counters, so that the number of hardware threads corresponding to the number is mounted. Hereinafter, the multithread processor 1 will be described in more detail.

  As shown in FIG. 1, the multi-thread processor 1 includes an arithmetic circuit 10, an interrupt controller 11, a PC generation circuit 12, thread program counters TPC0 to TPC3, selectors 13 and 18, an instruction memory 14, an instruction buffer 15, and a pipeline control circuit 16. An instruction fetch controller 17 and a thread scheduler 19.

  The arithmetic circuit 10 executes arithmetic processing based on an instruction generated by the hardware thread selected by the selector 18. More specifically, the arithmetic circuit 10 includes an instruction decoder 21, an execution unit 22, and a data register 23. The instruction decoder 21 decodes the received instruction and outputs an operation control signal SC to the execution unit 22. The instruction decoder 21 outputs a data register address Radd indicating the data storage position based on the instruction decoding result. The execution unit 22 executes various calculations according to the calculation control signal SC. The execution unit 22 has a plurality of execution stages and performs operations by pipeline processing. The calculation result executed in the execution unit 22 is transmitted to the PC generation circuit 12, the memory 2, and the data register 23 according to the type of the calculation result. The data register 23 stores data used in the execution unit 22. The data register 23 outputs data at an address designated by the data register address Radd. In the example shown in FIG. 1, the data register 23 is configured to output data a and data b according to the data register address Radd. Further, the data register 23 stores the calculation result output by the execution unit 22 at an address specified by the data register address Radd.

  The interrupt controller 11 receives the interrupt request signal and outputs an interrupt instruction signal instructing execution of interrupt processing in the multithread processor 1. More specifically, when receiving the interrupt request signal, the interrupt controller 11 determines the interrupt factor, the priority of the interrupt processing, and the like, and performs the PC generation circuit 12 and the pipeline control so as to perform processing related to the interrupt factor. The circuit 16 is instructed to execute interrupt processing. This interrupt request is output from circuits other than the multithread processor 1 in addition to those output from the multithread processor 1.

  The PC generation circuit 12 receives a new program instruction signal input via the system bus, an interrupt instruction signal output from the interrupt controller 11, and a branch instruction signal output based on processing in the execution unit 22, and updates the program count. Generate a value. Then, the PC generation circuit 12 gives the program count update value to any one of the thread program counters TPC0 to TPC3. The PC generation circuit 12 also has a function of determining to which thread program counter the generated program count update value is to be given.

  The thread program counters TPC0 to TPC3 generate an address of the instruction memory 14 in which an instruction to be processed is stored (this address is referred to as an instruction fetch address IMadd). When the program count update value is given from the PC generation circuit 12, the thread program counters TPC0 to TPC3 update the instruction fetch address IMadd according to the program count update value. On the other hand, when no program count update value is input, the thread program counters TPC0 to TPC3 calculate addresses in ascending order and calculate the next consecutive instruction fetch addresses. In FIG. 1, the number of thread program counters is four, but the number of program thread counters can be arbitrarily set according to the specifications of the multi-thread processor.

  The selector 13 selects any one of the thread program counters TPC0 to TPC3 according to the thread designation signal output from the instruction fetch controller, and outputs the instruction fetch address IMadd output from the selected thread program counter. In the selector 13 shown in FIG. 1, numbers 0 to 4 are assigned to the input terminals, and these numbers indicate the numbers of hardware threads.

  The instruction memory 14 is a memory area that is commonly used by a plurality of hardware threads. The instruction memory 14 stores various instructions used in operations executed in the multithread processor 1. Then, the instruction memory 14 outputs an instruction specified by the instruction fetch address IMadd input via the selector 13. At this time, the instruction memory 14 determines which one of the thread program counters TPC0 to TPC3 is the instruction fetch address IMadd output by the selector 13, and distributes the output destination of the instruction according to the determination result. In the present embodiment, the instruction buffer 15 has instruction buffer areas BUF0 to BUF3 corresponding to the thread program counters TPC0 to TPC3. Therefore, the instruction memory 14 distributes the read instruction to one of the instruction buffer areas BUF0 to BUF3 according to the output source of the instruction fetch address IMadd. The instruction memory 14 may be a predetermined memory area included in the memory 2. The instruction buffer areas BUF0 to BUF3 are FIFO (First In First Out) type buffer circuits. The instruction buffer areas BUF0 to BUF3 may be divided into areas in one buffer or may be formed in separated areas.

  The pipeline control circuit 16 monitors the instruction stored at the head of the instruction buffer 15 and the instruction being executed in the execution unit 22. Then, when an interrupt instruction signal is input from the interrupt controller 11, the pipeline control circuit 16 instructs the instruction buffer 15 and the execution unit 22 to discard an instruction belonging to a hardware thread related to interrupt processing. Do. Further, the pipeline control circuit 16 confirms the dependency relationship between the instruction stored at the head of the instruction buffer 15 and the instruction being executed in the execution unit 22. If it is determined that the dependency between instructions is high, a mask signal MSK that notifies the hardware thread number of the hardware thread to which the instruction belongs is output.

  The instruction fetch controller 17 determines which hardware thread should be fetched according to the number of instructions stored in the instruction buffer 15, and outputs a thread designation signal based on the determination result. For example, if the number of instruction queues stored in the instruction buffer area BUF0 is smaller than the number of instruction queues stored in other instruction buffer areas, the instruction fetch controller 17 fetches an instruction belonging to the 0th hardware thread. A thread designation signal indicating the 0th hardware thread is output. Thereby, the selector 13 selects the thread program counter TPC0. Note that the instruction fetch controller 17 may determine a hardware thread to be selected by a round robin procedure.

  The selector 18 is a selector that functions as a first selector. The selector 18 selects any one of the instruction buffer areas BUF0 to BUF3 according to the thread selection signal TSEL output from the thread scheduler 19, and outputs the instruction read from the selected instruction buffer area to the arithmetic circuit 10. That is, the selector 18 selects one hardware thread from a plurality of hardware threads according to the thread selection signal TSEL, and outputs an instruction output from the selected hardware thread to the arithmetic circuit 10. In the selector 18 as well, numbers 0 to 4 are assigned to the input terminals, and these numbers indicate the numbers of hardware threads.

  The thread scheduler 19 outputs a thread selection signal TSEL that designates one hardware thread to be executed in the next execution cycle among the plurality of hardware threads in accordance with a preset schedule. In other words, the thread scheduler 19 manages in what order the plurality of hardware threads are processed according to the schedule, and selects the thread so that the instructions generated by the hardware threads are executed in the order according to the schedule. The signal TSEL is output. In the multithread processor 1 according to the present embodiment, this schedule is set by a management program executed immediately after the multithread processor 1 is activated. When the thread scheduler 19 receives the mask signal MSK from the pipeline control circuit 16, the thread scheduler 19 selects a hardware thread other than the hardware thread corresponding to the hardware thread number indicated by the received mask signal MSK. Further, the thread scheduler 19 receives the dispatch signal DPT from the instruction decoder 21. The dispatch signal DPT notifies the number of the hardware thread to which the instruction processed (dispatched) by the instruction decoder 21 belongs.

  The multi-thread processor 1 according to the present embodiment is particularly characterized in the hardware thread scheduling method performed in the thread scheduler 19. Hereinafter, the thread scheduler 19 and the scheduling method will be described.

  FIG. 2 shows a block diagram of the thread scheduler 19. As shown in FIG. 2, the thread scheduler 19 includes dispatch counters 30a to 30d, a priority order determination unit 31, a thread number selection unit 32, and an initialization determination unit 33. In the present embodiment, since the multi-thread processor 1 has four hardware threads, the thread scheduler 19 is configured to determine the order of the four hardware threads. Is changed, the number of dispatch counters may be matched with the number of hardware threads. The configuration of other circuit blocks may be changed according to the number of dispatch counters.

  The dispatch counters 30a to 30d are provided corresponding to any one of a plurality of hardware threads. Each of the dispatch counters 30a to 30d holds a dispatch count value DCNT (including the dispatch count values DCNT0 to DCNT3 in FIG. 2) corresponding to the priority order for the corresponding hardware thread. Each of the dispatch counters 30a to 30d receives the dispatch signal DPT and counts the number of executions (dispatch times) of instructions belonging to the hardware thread corresponding to the own dispatch counter. More specifically, the dispatch counters 30a to 30d decrement the dispatch count value DCNT when the notification indicates the hardware thread corresponding to the hardware thread number notified by the dispatch signal DPT. The initial value of the dispatch count value DCNT is set by a management program executed when the multi-thread processor 1 is activated. In addition, the initial value of the dispatch count value DCNT is read from the memory by the management program, and the read value is set.

  The dispatch counters 30a to 30d receive the mask signal MSK (including the mask signals MSK0 to MSK3) and the initialization signal CNTint, and output the current count value Vnow (including the current count value Vnow0 to Vnow3). The dispatch counters 30a to 30d set the dispatch count value DCNT to the lowest priority (for example, 0) when the mask signal MSK corresponding to the corresponding hardware thread is input. The dispatch counters 30a to 30d reset the dispatch count value DCNT to the initial value when the initialization signal CNTint is input. The initialization signal CNTint is output from the initialization determination unit 33. The dispatch counters 30a to 30d output the dispatch count value DCNT based on the count value CNT held therein, and output the value of the count value CNT itself as the count current value Vnow. The detailed configuration of the dispatch counters 30a to 30d will be described later.

  The priority determination unit 31 refers to the dispatch count value DCNT output from the dispatch counters 30a to 30d, and determines the dispatch count value DCNT indicating the highest priority, thereby determining the hardware thread with the highest priority. . More specifically, the priority order determination unit 31 includes comparators 34 to 36. The comparators 34 to 36 each receive two values and select and output a larger value from the two values. At this time, the comparators 34 to 36 also output the information of the dispatch counter that has output the selected value. Further, when the two input values are the same value, the comparators 34 to 36 select and output one of the values according to a predetermined rule.

  More specifically, the comparator 34 receives the dispatch count value DCNT0 output from the dispatch counter 30a and the dispatch count value DCNT1 output from the dispatch counter 30b, and has a larger dispatch count value of the two dispatch count values. Is output as the high-priority hardware thread value M1. The comparator 35 receives the dispatch count value DCNT2 output from the dispatch counter 30c and the dispatch count value DCNT3 output from the dispatch counter 30d, and assigns a larger one of the two dispatch count values to the high priority hardware thread. Output as value M2. The comparator 36 receives the high-priority hardware thread value M1 output from the comparator 34 and the high-priority hardware thread value M2 output from the comparator 35, and has a larger value between the two high-priority hardware thread values. The high priority hardware thread value is output as the high priority hardware thread value MAX. The high priority hardware thread values M1, M2, and MAX are added with values indicating the dispatcher that outputs the values.

  The thread number selection unit 32 selects a hardware thread associated with the dispatch counter that has output the high-priority hardware thread value MAX output by the priority order determination unit 31, and the hardware thread number indicating the selected hardware thread Is output as a thread selection signal TSEL.

  Initialization determination unit 33 receives count current values Vnow0 to Vnow3 (count value CNT held in the dispatch counter to output dispatch count value DCNT), and combinations of count current values Vnow0 to Vnow3 are preset. When the predetermined condition is satisfied, the initialization signal CNTint is output. The predetermined condition in the present embodiment is a condition in which the count current values Vnow0 to Vnow3 are all 0.

  Next, the configuration of the dispatch counters 30a to 30d will be described in detail. Since the dispatch counters 30a to 30d have the same configuration, the configuration of the dispatch counter will be described taking the dispatch counter 30a as an example. A block diagram of the dispatch counter 30a is shown in FIG. As shown in FIG. 3, the dispatch counter 30a includes a counter initial set value storage unit 40, a count value storage unit 41, a decrementer 42, and a second selector (for example, a selector 43).

  The counter initial set value storage unit 40 stores a counter initial set value INIT0 of the dispatch count value DCNT output from the dispatch counter 30a. The counter initial setting value INIT0 is a value read from the memory 2 by the management program. The count value storage unit 41 stores the count value CNT0. Further, the count value storage unit 41 reads the counter initial setting value INIT0 in accordance with the initialization signal CNTint and sets it as the initial value of the count value CNT0. In addition to being output to the selector 43, the count value CNT0 is output to the initialization determination unit 33 as the current count value Vnow0, and is also output to the decrementer 42. The decrementer 42 decrements the count value CNT0 every time the dispatch signal DPT0 is input. Then, the decrementer 42 outputs the count value after decrement as a write-back value DCR0, and updates the count value CNT0 with the write-back value DCR0. The selector 43 selects one of the mask value (for example, 0) indicating the lowest priority and the count value CNT0 according to the mask signal MSK, and outputs the selected value as the dispatch signal DPT0.

  Here, the mask signal MSK will be described. The mask signal MSK confirms the dependency between the instruction stored in the head of the instruction buffer 15 and the instruction being executed in the execution unit 22 by the pipeline control circuit 16, and determines that the dependency between the instructions is high. Is output if. Then, the pipeline control circuit 16 reads out an instruction having a high dependency relationship with the instruction being executed in the execution unit 22 before the processing of the instruction executed in the execution unit 22 is sufficiently completed by the mask signal MSK. To prevent it.

  In order to describe the state in which the mask signal MSK is output, an example of an instruction group generated in one hardware thread is shown in FIG. The instruction group shown in FIG. 4 is composed of instructions 1 to 3 and shows an example in which the dependency relationship between the instruction 2 and the instruction 3 is high. The instruction 1 is an addition instruction for adding the value of the register a1 and the value of the register b1 and storing the value obtained as a result of the addition in the register c1. The instruction 2 is a load instruction for loading the data at the address 0x0 (a1) in the memory 2 into the register d1. The instruction 3 is an addition instruction that subtracts the value of the register d1 from the value of the register e1 and stores the result of the subtraction in the register b1.

  A problem that occurs when the instruction group shown in FIG. 4 is issued without the mask signal MSK being output will be described with reference to FIG. FIG. 5 is a timing chart showing an instruction processing flow when instructions 1 to 3 are issued in succession. Instructions 1 to 3 are processed by the decode stage ID, the execution stage EX, and the write back stage WB. Further, the instruction 2 has a memory access waiting stage MM for executing access to the memory 2. In the example shown in FIG. 5, instruction 1 is first decoded at time P1, processed at time P2, and the result value of the operation is written back to register c1 at time P3. Subsequently, instruction 2 is decoded at time P2 which is one time later than instruction 1, is processed at time P3, waits for memory access during the period of time P4 to P6, and stores the result value of the operation at register P1 at time P7. Write back to

  The instruction 3 is decoded at a time P3 that is one time later than the instruction 2, is processed at a time P4, and writes the operation result value back to the register e1 at a time P5. Here, the value of the register d1 referred to in the processing of the instruction 3 is not fixed unless it waits until the time P7. Therefore, the value of the register d1 read by the instruction 3 at the time P5 becomes a value different from the originally intended value, resulting in the result that the operation of the instruction 3 is not performed correctly.

  As described above, when the subsequent instruction uses the result of the instruction executed by the execution unit 22, the pipeline control circuit 16 determines that the dependency between the instructions is high, and outputs the mask signal MSK. Then, the pipeline control circuit 16 prevents the subsequent instruction from being issued by the mask signal MSK until the processing of the instruction previously executed by the execution unit 22 is completed and sufficient preparation for executing the subsequent instruction is made. To do.

  Therefore, FIG. 6 shows a timing chart of processing when the mask signal MSK is output in the processing of the timing chart shown in FIG. As shown in FIG. 6, when the mask signal MSK is output (mask signal MSK = 1), the execution stage EX of the instruction 3 is in a standby state between times P4 and P6 and is executed at time P7. The As a result, the execution stage EX of the instruction 3 is performed after the time P7 when the write back stage WB of the instruction 2 is performed. Thereby, the instruction 3 can read the value originally intended in the execution stage EX from the register d1.

  In this manner, the pipeline control circuit 16 controls the instruction issue timing in one hardware thread so that each operation is correctly performed in the execution unit 22 by using the mask signal MSK. Note that there may be a dependency relationship between instructions even in an instruction other than a load / store instruction to the memory 2.

  Next, the operation of the multithread processor 1 using the thread scheduler 19 will be described. FIG. 7 is a flowchart showing a procedure of operations from when the multi-thread processor 1 is powered on until the start of normal processing. As shown in FIG. 7, when the power is turned on, the multi-thread processor 1 first initializes the circuit state by hardware reset (step S1). Subsequently, the multi-thread processor 1 starts operation in the single thread mode (step S2). In this single thread mode, for example, the thread program counter TPC0, the instruction memory 14, and the instruction buffer area BUF0 are activated, and the other thread program counters TPC1 to TPC3 and the instruction buffer areas BUF1 to BUF3 stand by in a standby state.

  Then, the multithread processor 1 reads the management program from the memory 2 or another storage device (not shown) and executes the management program (step S3). Thereafter, according to the management program, the multi-thread processor 1 sets the counter initial setting value INIT in the counter initial setting value storage unit 40 (step S4). Then, the dispatch counters 30a to 30d initialize the count value CNT stored in the count value storage unit 41 with the counter initial setting value INIT (step S5). When the setting of these various registers is completed, the multi-thread processor 1 starts operating in the multi-thread mode (step S6). In this single thread mode, for example, the thread program counters TPC0 to TCP3, the instruction memory 14, and the instruction buffer areas BUF0 to BUF3 are activated. Then, the multi-thread processor 1 starts normal operation in the multi-thread mode.

  Next, the operation of the thread scheduler 19 during normal operation of the multithread processor 1 will be described. FIG. 8 is a flowchart showing the operation of the thread scheduler 19 during normal operation. Note that the flowchart shown in FIG. 8 is described mainly with respect to the operation of the dispatch counter 30a, but the dispatch counters 30b to 30d also have the same operation.

  As shown in FIG. 8, the thread scheduler 19 first determines whether or not the count current values Vnow0 to Vnow3 satisfy the initialization condition in the initialization determination unit 33 (step S10). If it is determined in step S10 that the current count values Vnow0 to Vnow3 are initial or satisfy the condition (Yes in step S10), the counter initial setting value INIT0 is set to the count value CNT0, and the count value CNT0 is initialized ( Step S11). On the other hand, if it is determined in step S10 that the current count values Vnow0 to Vnow3 are initial or do not satisfy the condition (No branch in step S10), the process proceeds to the next process without performing the process in step S11.

  In the next step, it is determined whether or not the value of the corresponding mask signal MSK0 is 0 (step S12). At this time, if the mask signal MSK0 is 0 (Yes in step S12), the dispatch counter 30a outputs the count value CNT0 as the dispatch count value DCNT (step S13). On the other hand, when the mask signal MSK0 is 1 in step S12 (No branch in step S12), the dispatch counter 30a outputs the mask value as the dispatch count value DCNT (step S14).

  Next, the thread scheduler 19 determines the dispatch counter that outputs the dispatch count value DCNT having the highest priority in the priority determination unit 31, and outputs the high priority hardware thread value MAX (step S15). Next, the thread scheduler 19 selects a hardware thread corresponding to the dispatch counter that outputs the high priority hardware thread value MAX in the thread number selection unit 32, and outputs a thread selection signal TSEL that designates the selected hardware thread. (Step S16).

  Next, the multi-thread processor 1 executes an instruction belonging to the hardware thread designated by the thread selection signal TSEL, and notifies the thread scheduler 19 of the hardware thread to which the executed instruction belongs by the dispatch signal DPT. When the dispatch counter 30a receives the dispatch signal DPT0 (Yes in step S17), the dispatch counter 30a decrements the count value CNT0 (step S18). Thereafter, the thread scheduler 19 returns the process to step S10. On the other hand, when the dispatch counter 30a does not receive the dispatch signal DPT0 (No in step S17), the dispatch counter 30a does not update the count value CNT0. Thereafter, the thread scheduler 19 returns the process to step S10.

  Next, FIG. 9 shows a table for explaining how the thread number selected by the thread scheduler 19 is switched. In the example shown in FIG. 9, the thread switching timing is one time. In addition, the counter initial setting values of the dispatch counters 30a to 30d are 3, 4, 2, and 1, respectively. In the example shown in FIG. 9, it is assumed that the mask signal MSK always indicates 0. In the example shown in FIG. 9, the time t1 is set as an initial state, and the time t1 is set as the processing start time.

  At time t1, the dispatch count values DCNT0 to DCNT3 are the same as the count values CNT0 to CNT3. At this time, the maximum dispatch count value is 4 indicated by the dispatch count value DCNT1. Therefore, the thread number selection unit 32 outputs a thread selection signal TSEL indicating the first hardware thread corresponding to the dispatch counter 30b that outputs the dispatch count value DCNT1. The multi-thread processor 1 executes an instruction belonging to the first hardware thread and outputs a dispatch signal DPT1 notifying that the first hardware thread has been dispatched. Therefore, at time t2, the count value CNT1 and the dispatch count value DCNT1 corresponding to the first hardware thread are decremented by one.

  At time t2, the dispatch count values DCNT0 to DCNT3 are the same as the count values CNT0 to CNT3. At this time, the maximum dispatch count value is 3 indicated by the dispatch count value DCNT0 and the dispatch count value DCNT1. In such a case, the comparator 34 of the priority determination unit 31 outputs a dispatch count value output by a dispatch counter corresponding to a hardware thread having a smaller number. Therefore, the thread number selection unit 32 outputs a thread selection signal TSEL indicating the 0th hardware thread corresponding to the dispatch counter 30a that outputs the dispatch count value DCNT0. The multi-thread processor 1 executes an instruction belonging to the 0th hardware thread and outputs a dispatch signal DPT0 notifying that the 0th hardware thread has been dispatched. Therefore, at time t3, the count value CNT0 and the dispatch count value DCNT0 corresponding to the 0th hardware thread are decremented by one.

  Thereafter, at times t3 to t10, the above operation is repeated according to the count value CNT and the dispatch count value DCNT. Then, when the process at time t10 is performed, the count values CNT0 to CNT3 all become zero. Therefore, initialization processing by the initialization determination unit 33 is performed after the elapse of time t10, and the state of the thread scheduler 19 at time t11 is reset to the state of time t1.

  Next, FIG. 10 shows a table showing another example for explaining how the thread number selected by the thread scheduler 19 is switched. The example shown in FIG. 10 is a case where there is a period in which the mask signal MSK is 1 in the example shown in FIG. In the example shown in FIG. 10, the first hardware thread selected at time t1 is executed, so that the mask signal MSK1 corresponding to the first hardware thread becomes 1 at times t2 to t4. Therefore, the dispatch count value DCNT1 indicating the priority order of the first hardware thread is 0 (lowest priority order) during the period from time t2 to time t4. Therefore, the thread scheduler 19 in the period from time t2 to t4 selects a hardware thread other than the first hardware thread according to the dispatch count value DCNT at that time.

  In the example shown in FIG. 10, the mask signal MSK0 corresponding to the 0th hardware thread becomes 1 at times t13 to t14 by executing the 0th hardware thread selected at time t12. Therefore, during the period from time t12 to t13, the dispatch count value DCNT0 indicating the priority order of the 0th hardware thread is 0 (lowest priority order). Therefore, the thread scheduler 19 in the period from time t13 to t14 selects a hardware thread other than the 0th hardware thread according to the dispatch count value DCNT at that time.

  In the example shown in FIG. 10, the first hardware thread selected at time t13 is executed, so that the mask signal MSK1 corresponding to the first hardware thread becomes 1 at times t14 to t15. Therefore, during the period from time t13 to t13, the dispatch count value DCNT1 indicating the priority order of the first hardware thread is 0 (lowest priority order). Therefore, the thread scheduler 19 in the period from time t14 to t15 selects a hardware thread other than the first hardware thread according to the dispatch count value DCNT at that time. That is, the 0th hardware thread and the 1st hardware thread are excluded from the choices during the period of time t14.

  From the above description, the thread scheduler 19 used in the multi-thread processor 1 according to the present embodiment has the priority corresponding to each hardware thread as the dispatch count value DCNT. Then, the thread scheduler 19 selects any one of the hardware threads according to the priority order of the hardware threads, and outputs a thread selection signal TSEL indicating the selected hardware thread. Further, the thread scheduler 19 recognizes that the selected hardware thread has been executed by the dispatch signal DPT, and updates the priority order of the hardware thread in accordance with the dispatch signal DPT. More specifically, the thread scheduler 19 selects a hardware thread with the highest priority, and outputs a thread selection signal TSEL indicating the selected hardware thread. The thread scheduler 19 recognizes that the selected hardware thread has been executed by the dispatch signal DPT, and lowers the priority of the hardware thread in accordance with the dispatch signal DPT.

  Thereby, the thread scheduler 19 according to the present embodiment preferentially selects a hardware thread with a high priority in the initial state, and does not maintain a high priority thereafter. Therefore, the thread scheduler 19 can secure the execution period of other hardware threads while executing the hardware threads with high priority in the initial state. That is, the multi-thread processor 1 using the thread scheduler 19 according to the present embodiment alternately executes hardware threads having a plurality of priorities, and more hardware threads having higher priorities. Processing time can be assigned. In other words, the multi-thread processor 1 according to the present embodiment can execute a plurality of hardware threads without delay regardless of the initial state of the priority order of the hardware threads.

  The example shown in FIG. 9 will be described. The first hardware thread having a high priority in the initial state has a processing time of 40% in the period from the time t1 to the time t10, and more than the other hardware threads. A lot of processing time is secured. At this time, in the multi-thread processor 1 according to the present embodiment, the first hardware thread and other hardware threads are alternately executed without the execution time of the first hardware thread continuing. That is, in the multi-thread processor 1 according to the present embodiment, a plurality of hardware threads are executed without delay without the processing time being biased to the time of any one hardware thread.

  Further, in the multithread processor 1 according to the present embodiment, the utilization efficiency of the execution stage of the execution unit 22 (or the utilization efficiency of the pipeline) can be improved. More specifically, when the originally scheduled hardware thread cannot be selected due to the pipeline state, the thread scheduler 19 according to the present embodiment recognizes the pipeline state by the mask signal MSK. Then, the thread scheduler 19 selects a hardware thread different from the hardware thread notified by the mask signal MSK. Thereby, since an instruction belonging to another hardware thread can be given to a place where an empty stage may occur in the pipeline, the multi-thread processor 1 according to the present embodiment increases the utilization efficiency of the pipeline. Can do.

Embodiment 2
FIG. 11 is a block diagram of the multithread processor 1a according to the second embodiment. As shown in FIG. 11, the multi-thread processor 1 a is obtained by replacing the thread scheduler 19 in the first embodiment with a thread scheduler 19 a that is a modification of the thread scheduler 19. Therefore, in the following description, the thread scheduler 19a will be mainly described, and description of other components will be omitted.

  FIG. 12 shows a block diagram of the thread scheduler 19a. As illustrated in FIG. 12, the thread scheduler 19 a includes a third selector (for example, the selector 50), the first thread scheduler 19, and the second thread scheduler 51. The selector 50 selects either the first thread selection signal TSELa output from the first thread scheduler 19 or the first thread selection signal TSELb output from the second thread scheduler 51 according to the signal level of the real-time bit signal. One of them is selected, and the selected thread selection signal is output as a thread selection signal TSEL to be supplied to the first selector 18. The first thread selection signal TSELa is the same as the thread selection signal TSEL described in the first embodiment. Here, in order to distinguish the thread selection signals, for convenience, the thread selection signal output by the first thread scheduler 19 is referred to as a first thread selection signal TSELa. Since the first thread scheduler is the same as the thread scheduler 19 in the first embodiment, the description thereof is omitted here.

  The second thread scheduler 51 outputs a selection signal (for example, a real-time bit signal) for switching between the first execution period and the second execution period, and the real-time bit signal specifies the first execution period. A first hardware thread number (for example, a second thread selection signal TSELb) that designates a hardware thread that is executed in a preset execution order in a certain period is output. Here, the first execution period is a period in which a real-time bit signal described later is 1, and the second execution period is a period in which a real-time bit signal described later is 0. In the first execution period, the hardware thread number to be selected is set in advance, and in the second execution period, the hardware thread number to be selected is arbitrarily set by the first thread scheduler 19, for example. Set to The second thread scheduler 51 includes a thread control register 52, a counter 53, a maximum count value storage unit 54, a coincidence comparison circuit 55, and a selector 56.

  The thread control register 52 includes a plurality of slots (for example, slots SLT0 to SLT7). The structure of this slot is shown in FIG. As shown in FIG. 13, the slots SLT0 to SLT7 each have a number storage unit in which the hardware thread number HWT is stored, and a period attribute setting flag that determines the logical level of the real-time bit signal when the slot is selected. A real-time bit storage unit (for example, real-time bit RT).

  The counter 53 updates the count value CNT at a predetermined interval. More specifically, the counter 53 in the present embodiment counts up the count value CNTa in synchronization with an operation clock of the multi-thread processor 1 (not shown). The count maximum value storage unit 54 stores a count maximum value CNTM that defines an upper limit value of the count value CNTa of the counter 53. The coincidence comparison circuit 55 compares the count value CNTa with the maximum count value CNTM, and outputs a reset signal RST that resets the count value CNTa of the counter 53 when the count value CNT matches the maximum count value CNTM. That is, the counter 53 outputs the count value CNTa whose value is cyclically updated by repeating the count-up operation while initializing the count value CNTa at a predetermined cycle.

  The selector 56 selects one of the slots in the thread control register 52 according to the count value CNTa, and outputs a real-time bit signal and the second thread selection signal TSELb based on the value stored in the selected slot. More specifically, if the count value CNTa is 0, the selector 56 selects the slot SLT0, sets the hardware thread number stored in the number storage unit of the slot SLT0 as the second thread selection signal TSELb, and sets the slot SLT0. The value of the real-time bit RT stored in the real-time bit storage unit is used as the logic level of the real-time bit signal.

  Note that the value stored in the slot of the thread control register 52 of the second thread scheduler 51, the initial value of the count value CNTa of the counter 53, and the maximum count value CNTM of the maximum count value storage unit 54 are the activation of the multi-thread processor 1. It is set by a management program that is sometimes executed. The management program reads these setting values from the memory 2.

  Next, the operation of the thread scheduler 19a after starting the normal operation will be described. First, the operation of only the second thread scheduler 51 will be described. In the following description, as an example of the setting, the initial value of the count value CNT of the counter 53 is 0, and the maximum count value CNTM is 4. Each value of the slot of the thread control register 52 sets the real time bits of the slots SLT0 to SLT2, SLT4, SLT5, and SLT7 to 1, and sets the real time bits of the slots SLT3 and SLT6 to 0. Furthermore, the hardware thread number of the slots SLT0, SLT2, SLT5, and SLT7 is 0, the hardware thread number of the slots SLT1 and SLT4 is 1, and the hardware thread number of the slot SLT3 is 2.

  The hardware thread numbers selected by the second thread selection signal TSELb output from the second thread scheduler 51 under the above conditions are shown in the table of FIG. In the table of FIG. 14, one timing for switching the hardware thread selected by the second thread scheduler 51 is defined as one time, and the second thread selection signal TSELb is switched as time passes.

  As shown in FIG. 15, when the count value CNT at time t1 is first 0, the selector 56 selects the slot SLT0. Accordingly, the selector 56 sets the logic level of the real-time bit signal to 1 and sets the second thread selection signal TSELb to 0. Subsequently, at time t2, the count value CNT is incremented to 1. Therefore, the selector 56 selects the slot SLT1. Accordingly, the selector 56 sets the logic level of the real-time bit signal to 1 and sets the second thread selection signal TSELb to No. 1. Next, at time t3, the count value CNT is incremented to 2. Therefore, the selector 56 selects the slot SLT2. Accordingly, the selector 56 sets the logic level of the real-time bit signal to 0 and sets the second thread selection signal TSELb to No. 1. Next, at time t4, the count value CNT is counted up to 3. Therefore, the selector 56 selects the slot SLT3. Therefore, the selector 56 sets the logic level of the real-time bit signal to 1 and sets the second thread selection signal TSELb to No. 2. Next, the count value CNT is counted up to 4 at time t5. Therefore, the selector 56 selects the slot SLT4. Accordingly, the selector 56 sets the logic level of the real-time bit signal to 1 and sets the second thread selection signal TSELb to No. 1. At time t5, the count value CNTa reaches the maximum count value CNTM, so that the count value CNTa is reset after the elapse of time t6. As a result, the second thread scheduler 51 in the period from time t6 to t10 repeats the operation from time t1 to t5.

  In the second embodiment, the first thread scheduler 19 selects a hardware thread to be executed in the second execution period specified by the second thread scheduler 51. Therefore, FIG. 15 shows a table showing the operation of the thread scheduler 19a according to the second embodiment. The example shown in FIG. 15 uses the condition shown in FIG. 14 as the setting value of the second thread scheduler 51. In addition, the counter initial setting values of the first thread scheduler 19 are 2, 1, 3, and 4 in order from the 0th hardware thread to the 3rd hardware thread. That is, in the first thread scheduler in this example, the priority of the hardware thread that is not scheduled to be executed in the second thread scheduler 51 is set higher than that of other hardware threads.

  As shown in FIG. 15, the second thread scheduler 51 sets the real-time bit signal (RT in the figure) to 0 at times t3, t9, t13, and t18. Therefore, the thread scheduler 19a uses the first thread selection signal TSELa output from the first thread scheduler 19 at times t3, t9, t13, and t18. At this time, since the dispatch count value corresponding to the third hardware thread becomes the largest at any timing of times t3, t9, t13, and t18, the first thread selection signal TSELa is set at times t3, t9, and t13. , T18 designates the third hardware thread at any other timing.

  The first thread scheduler 19 is notified of the hardware thread executed based on the second thread selection signal TSELb output from the second thread scheduler 51 by the dispatch signal DPT. Therefore, the count values CNT0 to CNT3 decrease during the period from time t1 to t18. At this time, the count values CNT <b> 0 to CNT <b> 3 do not decrease any more with 0 as the lower limit.

  From the above description, in the thread scheduler 19a according to the second embodiment, the first thread scheduler 19 is used to generate a thread selection signal when the second execution period is designated in the second thread scheduler 51. . At this time, in the first thread scheduler, the priority order of the hardware threads changes reflecting the number of hardware threads executed based on the operation of the second thread scheduler 51. Therefore, by combining the first thread scheduler 19 with the second thread scheduler 51, the first thread scheduler 19 can specify a hardware thread with a small number of executions in the second thread scheduler 51.

  Further, in the second thread scheduler 19, since the hardware thread executed in the first execution period is fixed, the minimum execution time of the hardware thread can be guaranteed regardless of the priority order of the hardware thread. it can. That is, according to the multithread processor 1a according to the second embodiment, the first execution period is designated by the second thread scheduler 51 to guarantee the minimum execution time of the hardware thread. Then, by selecting a hardware thread by the first thread scheduler 19 in the second execution period, it is possible to preferentially select a hardware thread having a low execution frequency in the second execution period. That is, according to the multithread processor 1a according to the second embodiment, it is possible to prevent the occurrence of hardware threads that are delayed in processing while guaranteeing the minimum execution time of the hardware threads.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the thread scheduling method in the second scheduler can be appropriately changed according to the specifications of the multi-thread processor.

1, 1a Multi-thread processor 2 Memory 10 Arithmetic circuit 11 Controller 12 PC generation circuit 13, 18, 43, 50, 56 Selector 14 Instruction memory 15 Instruction buffer 16 Pipeline control circuit 17 Instruction fetch controller 19, 19a, 51 Thread scheduler 21 Instruction decoder 22 Execution unit 23 Data registers 30a-30d Dispatch counter 31 Priority determination unit 32 Thread number selection unit 33 Initialization determination unit 34-36 Comparator 40 Counter initial setting value storage unit 41 Count value storage unit 42 Decrementer 52 Thread control Register 53 Counter 54 Count maximum value storage 55 Match comparison circuits TPC0 to TCP3 Thread program counter BUF0 to BUF3 Instruction buffer area IMadd Instruction fetch address R dd Data register address SC Operation control signal TSEL, TSELa, TSELb Thread selection signal DPT, DPT0-DPT3 Dispatch signal MSK, MSK0-MSK3 Mask signal M1, M2, MAX High priority hardware thread value CNTint Initialization signal Vnow0-Vnow3 Count Current Value CNT, CNT0 to CNT3, CNTa Count value DCNT, DCNT0 to DCNT3 Dispatch count value INIT0 Counter initial setting value DCR0 Write back value CNTM Count maximum value RST Reset signal HWT Hardware thread number RT Real time bits SLT0 to SLT7 Slot

Claims (8)

Multiple hardware threads, each generating independent instruction streams;
A first thread selection signal for designating a hardware thread to be selected in the next execution cycle from among the plurality of hardware threads in accordance with a priority set in advance for each of the plurality of hardware threads. Thread scheduler,
A first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread;
An arithmetic circuit that executes an instruction output from the first selector ,
The first thread scheduler is
A second thread scheduler that determines hardware threads according to the priority;
A thread control register including a plurality of slots each holding first information designating one of the plurality of hardware threads or second information designating the second thread scheduler;
A storage unit for storing third information for designating one of the plurality of slots;
When a slot is sequentially selected from the first slots of the plurality of slots of the thread control register and a slot designated by the storage unit is selected, the slot is returned to the first slot and the slot is sequentially selected again. ,
When the selected slot holds the first information, select a hardware thread designated by the first information and output the thread selection signal;
When the selected slot holds the second information, the hardware thread determined by the second thread scheduler is selected and the thread selection signal is output,
The second thread scheduler,
Preferentially select the hardware thread with the higher priority and output the thread selection signal;
Each time the instruction generated by the hardware thread selected by the thread selection signal is executed in the arithmetic circuit, an update is performed to lower the priority for the hardware thread that generated the executed instruction. ,
A multi-thread processor that outputs the thread selection signal in accordance with the updated priority order . 2. The multi-thread processor according to claim 1 , wherein the second thread scheduler lowers the priority by one step each time the priority update processing is performed. When there are a plurality of hardware threads having the same priority, the second thread scheduler selects any one of the hardware threads according to a preset rule, and selects the selected hardware thread. multithreaded processor according to claim 1 or 2 outputs the thread selection signal designating. The second thread scheduler, when the instruction prepared in the plurality of hardware threads is a highly dependent instruction using a processing result of the instruction being executed in the arithmetic circuit, The multithread processor according to any one of claims 1 to 3 , wherein the priority of the hardware thread including a highly related instruction is set to the lowest priority . The second thread scheduler is
A plurality of dispatch counters each holding a dispatch count value corresponding to the priority for the corresponding hardware thread;
A priority determination unit that refers to the dispatch count value held by the plurality of dispatch counters and determines the hardware thread having the highest priority;
A thread number selection unit that outputs the thread selection signal that specifies a hardware thread that is determined to have the highest priority in the priority determination unit, and
The arithmetic circuit outputs a dispatch signal that notifies the hardware thread that generated the executed instruction each time the hardware thread generates the instruction,
Wherein the plurality of dispatch counter according to any one of claims 1 to 4 wherein the dispatch signal to update the dispatch count value own dispatch counter outputs to indicate the hardware thread corresponding to its own dispatch counter Multi-threaded processor. 6. The multithread processor according to claim 5 , further comprising an initialization determination unit that resets the dispatch count value to an initial set value when dispatch count values held in the plurality of dispatch counters satisfy a predetermined initialization condition. . Each of the plurality of dispatch counters includes a counter initial setting value storage unit that stores a counter initial setting value corresponding to the priority order of the corresponding hardware thread;
A count value storage unit that stores the counter initial setting value as an initial value of the count value;
A decrementer that receives the dispatch signal and updates the count value stored in the count value storage;
A pipeline control circuit that monitors whether or not the instruction prepared in the plurality of hardware threads is a highly dependent instruction using a processing result of the instruction being executed in the arithmetic circuit, Receiving a mask signal output to the hardware thread including a high instruction, and selecting either the count value or the mask value corresponding to the count value of the lowest priority according to the mask signal; A third selector for outputting the selected value as the dispatch count value;
The multi-thread processor according to claim 5 or 6 . The multithread processor according to any one of claims 1 to 7 , wherein initial values of priorities of the plurality of hardware threads are set by a management program executed when the multithread processor is activated.

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