JP5942331B2 - Current detection circuit and projector apparatus including the same - Google Patents

Description

The present invention relates to a current detection circuit that detects a current with respect to a pulse current and a projector apparatus including the current detection circuit.

  As a means of measuring the current value flowing through an arbitrary line in an electric circuit, a voltage drop method is widely used in which a resistance is inserted into the line and converted into the magnitude of the voltage generated at both ends of the resistance. Yes.

  Consider a case where the voltage drop method is performed by, for example, a microcomputer, and processing is performed by reading a voltage value by A / D conversion. In this case, in order to measure the current of the line whose current path is opened and closed at high speed, for example, the current flowing through the switching transistor of the switching regulator, the converted voltage value to be temporarily measured while processing the measured value is used. I need to remember.

  FIG. 3 shows an example of such a circuit. In the figure, an input terminal IN is connected to the drain of an N-channel FET Q1, and a PWM (pulse width modulation) signal for on / off switching control is applied to the gate of the FET Q1. The source of the FET Q1 is connected to one end of a current detection resistor RS for converting a current into a voltage by a voltage drop method via a point c, and the other end of the resistor RS is grounded.

  A current line that includes the current detection resistor RS and becomes an overcurrent detection target is indicated by an arrow CL1 in the figure. One end of a current detection resistor R is connected to the source of the FET Q1 and one end of the resistor RS, and the other end of the resistor R is connected to the other end of the capacitor C3 whose one end is grounded via a point e. The output terminal OUT is used for detection. In the circuit of FIG. 3, the resistor R and the capacitor C3 constitute an integrating circuit, and the integrated output is taken out from the output terminal OUT.

  In the circuit configuration as described above, a stable voltage output can be obtained with a simple circuit configuration by setting an appropriate integration constant according to the values of the resistor R and the capacitor C3. However, since the voltage value that can be measured varies greatly depending not only on the magnitude of the current flowing through the current line CL1, but also on / off duty of the FET Q1, the conditions that can be used are limited.

  As a means for measuring the magnitude of the current value without being affected by the duty, a circuit as shown in FIG. 4 can be considered. In FIG. 4, the resistor R in the circuit configuration of FIG. 3 is replaced with a diode D1, thereby functioning as a peak hold circuit in place of the integrating circuit.

  In the circuit configuration of FIG. 4 as well, if each constant is optimized, the peak value of the voltage generated in the current detection resistor RS can be output to some extent with a simple circuit configuration.

  However, in the configuration shown in FIG. 4, the diode D1 is connected in series with the circuit. Therefore, the voltage at the point c needs to be set higher so that the voltage exceeds the operating voltage VF of the diode D1. When the generated voltage is increased in this way, the power loss generated in the current detection resistor RS also increases. As a result, the circuit configuration as shown in FIG. 4 should be adopted only within the allowable range of the generated voltage and the power loss. I can't.

  Further, as a similar technique, a peak hold circuit for detecting current is used for current control (for example, Patent Document 1), or an overcurrent detection circuit as a peak hold circuit after processing the output of the overcurrent detection resistor. (For example, patent document 2) etc. which are employ | adopted for are considered.

JP 2001-103741 A Japanese Patent Laid-Open No. 05-211715

  Similarly to the circuits shown in FIGS. 3 and 4, the techniques described in each of the above patent documents have a simple circuit configuration, a special circuit form to be inserted, and a voltage generated in the current detection resistor. There is a problem that the degree of freedom in design is low because the use environment is limited to each such as setting the value higher than usual.

The present invention has been made in view of the circumstances described above, and an object, while reducing the circuit scale as a simple structure as possible, the current detection circuit is a high degree of freedom in design for the use environment and It is to provide a projector apparatus provided with the same.

The present invention has a first field effect transistor in which a pulse width modulation signal is input to a gate terminal and a source terminal is electrically grounded , and one terminal is connected to a drain terminal of the first field effect transistor, A first resistor whose other terminal is connected to the power supply voltage, a first diode whose cathode terminal is electrically grounded, one terminal connected to the drain terminal of the first field effect transistor, and the other A second resistor connected to the anode terminal of the first diode, one terminal connected to the drain terminal of the first field effect transistor, and the other terminal connected to the anode of the first diode. A first capacitor connected to the terminal; a second field-effect transistor in which the current to be detected is input to the drain terminal and the pulse width modulation signal is input to the gate terminal; A third resistor whose one terminal is connected to the source terminal of the second field effect transistor and whose other terminal is electrically grounded, and whose anode terminal is the source terminal of the second field effect transistor A second diode connected to the second diode; one terminal connected to the anode terminal of the first diode; the other terminal connected to the cathode terminal of the second diode; and an anode terminal A third diode connected to the cathode terminal of the second diode, a third capacitor having one terminal connected to the cathode terminal of the third diode and the other terminal electrically grounded; The connection point between the cathode terminal of the third diode and one terminal of the third capacitor is an output terminal for detection, and the power supply voltage is The voltage dividing ratio divided by the second resistor and the first diode is such that the voltage across the first capacitor when the pulse width modulation signal is at a low level is the forward direction of the second diode. The voltage dividing ratio is higher than the effective voltage VF, and the potential of the terminal connected to the anode terminal of the first diode of the second capacitor changes to a negative potential according to the pulse width modulation signal. And

  According to the present invention, it is possible to increase the degree of design freedom with respect to the usage environment while reducing the circuit scale as a simple configuration as much as possible.

The figure which shows the structure of the current detection circuit which concerns on one Embodiment of this invention. The timing chart which shows the operation signal waveform in each site | part of the circuit of FIG. 1 which concerns on the embodiment. The figure which shows the circuit structure of a general electric current detection. The figure which shows the structure of the general peak hold circuit of an electric current.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings, taking as an example a method for measuring a pulsed current flowing in a switching transistor of a switching regulator.

  FIG. 1 shows a configuration of a current detection circuit 10 according to the present embodiment. In the figure, an input terminal IN is connected to the drain of an N-channel FET Q1, and a PWM (pulse width modulation) signal for on / off control is applied to the gate of the FET Q1. The source of the FET Q1 is connected to one end of a current detection resistor RS for converting a current into a voltage by a voltage drop method via a point c, and the other end of the resistor RS is grounded.

  The point c is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the anode of the diode D2 and one end of the capacitor C2, which is a second auxiliary capacitor, through the point d. The other end of the capacitor C2 is connected to one end of the capacitor C1, which is the first auxiliary capacitor, one end of the resistor R1, and the anode of the diode D3 via the point b.

  The other end of the capacitor C1 and the other end of the resistor R1 become a point a, and the same point a is connected to one end of the resistor R2 and the drain of the N-channel FET Q2. The power supply voltage VCC is applied to the other end of the resistor R2.

  The cathode of the diode D3 and the source of the FET Q2 are grounded. A PWM signal is applied to the gate of the FET Q2 in the same manner as the FET Q1.

The cathode of the diode D2 is connected to one end of a capacitor C3, the other end of which is grounded, via a point e, and serves as a detection output terminal OUT.
The FET Q2, resistors R1 and R2, diode D3, and first and second auxiliary capacitors C1 and C2 constitute a negative potential generation circuit MP1.

Next, the operation of the above embodiment will be described.
FIG. 2 is a timing chart showing signal waveforms at various points in the circuit of FIG.

  As shown in FIG. 2A, when the PWM signal applied to the gates of the FETs Q1 and Q2 is at the “L (low)” level, both the FETs Q1 and Q2 are turned off, and both ends of the capacitor C1, which is the first auxiliary capacitor. The voltage is a voltage generated as a result of dividing the power supply voltage VCC by the resistors R2 and R1 and the diode D3, that is, a voltage across the resistor R1. This voltage division ratio is selected in advance so that the voltage across the capacitor C1 is higher than the forward drop voltage VF of the diode D1.

  Next, when the PWM signal becomes the “H (high)” level and the FET Q1 is turned on, the voltage corresponding to the current of the measurement current line CL2 at the point c as shown in FIG. 2D due to the voltage drop of the current detection resistor RS. Will occur.

  By turning on the FET Q2 simultaneously with the FET Q1, the point a becomes the GND potential as shown in FIG. Therefore, as shown in FIG. 2C, the point b becomes a negative potential lower than GND by the voltage value held in the capacitor C1.

  Even if the potential difference generated at both ends of the current detection resistor RS is less than or equal to the forward drop voltage VF of the diode D1 by this sweep operation, as shown in FIGS. 2D and 2C, the points c and b The potential difference between the first and second voltages becomes equal to or higher than the voltage VF. Therefore, the capacitor C2, which is the second auxiliary capacitor, can be charged via the diode D1.

When the voltage across the capacitor C1 is V1, the voltage across the current detection resistor RS is VRS, and the voltage across the capacitor C2 is V2, the voltage V2 charged to the capacitor C2 is:
V2 = VRS + V1-VF (1)
It can be expressed by the following formula.

  Next, when the PWM signal becomes “L” level, the FETs Q1 and Q2 are turned off, and the potential at the point b returns to the position where it was previously turned off. Therefore, as shown in FIG. 2E, the potential at the point d is the potential at the point b when the PWM signal is “L” level, and the voltage charged in the capacitor C2 when the PWM signal is “H” level. The added value.

If all the diodes D1 to D3 have the same forward voltage drop VF, the potential at the point b with respect to the GND potential when the PWM signal is “L” level is VF, the potential at the point d with respect to the GND potential is ,
V2 + VF = VRS + V1-VF + VF
= VRS + V1 (2)
It becomes.

This voltage charges the capacitor C3 connected to the output terminal OUT through the diode D2 when the PWM signal is at “L” level. At this time, when the potential at a point e shown in FIG.
VE = VRS + V1-VF (3)
It becomes.

  From this result, since the voltage V1 across the capacitor C1 and the forward voltage drop VF of each diode are known, the measurement voltage proportional to the current generated across the current detection resistor RS can be easily separated and detected. Is possible.

  As described above in detail, according to the present embodiment, the degree of design freedom with respect to the usage environment such as the magnitude of the current flowing through the current line CL1 and the duty ratio of the PWM signal is reduced while reducing the circuit scale as simple as possible. It becomes possible to raise.

  The circuit described in the above embodiment is suitable for a projector apparatus that uses a semiconductor light source element that requires precise current value control, such as an LD (laser diode) or an LED (light emitting diode), for the light source unit.

  It should be noted that the present invention is not limited to the configuration shown in FIG. 1 with respect to the specific circuit configuration of the negative potential generating circuit MP1.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the functions executed in the above-described embodiments may be combined as appropriate as possible. The above-described embodiment includes various stages, and various inventions can be extracted by an appropriate combination of a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, if the effect is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 10 ... Current detection circuit, Q1, Q2 ... (N channel) FET, C1 ... (first auxiliary) capacitor, C2 ... (second auxiliary) capacitor, MP1 ... Negative potential generation circuit.

Claims (2)

A first field effect transistor having a pulse width modulation signal input to a gate terminal and a source terminal electrically grounded ;
A first resistor having one terminal connected to the drain terminal of the first field effect transistor and the other terminal connected to a power supply voltage;
A first diode whose cathode terminal is electrically grounded;
A second resistor having one terminal connected to the drain terminal of the first field effect transistor and the other terminal connected to the anode terminal of the first diode;
A first capacitor having one terminal connected to the drain terminal of the first field effect transistor and the other terminal connected to the anode terminal of the first diode;
A second field effect transistor in which a current to be detected is input to a drain terminal and the pulse width modulation signal is input to a gate terminal;
A third resistor having one terminal connected to the source terminal of the second field effect transistor and the other terminal electrically grounded;
A second diode having an anode terminal connected to a source terminal of the second field effect transistor;
A second capacitor having one terminal connected to the anode terminal of the first diode and the other terminal connected to the cathode terminal of the second diode;
A third diode having an anode terminal connected to the cathode terminal of the second diode;
A third capacitor having one terminal connected to the cathode terminal of the third diode and the other terminal electrically grounded;
With
The connection point between the cathode terminal of the third diode and one terminal of the third capacitor is an output terminal for detection.
The voltage dividing ratio obtained by dividing the power supply voltage by the first resistor, the second resistor, and the first diode is the voltage across the first capacitor when the pulse width modulation signal is at a low level. A voltage division ratio higher than the forward effect voltage VF of the second diode,
A current detection circuit, wherein a potential of a terminal connected to an anode terminal of the first diode of the second capacitor changes to a negative potential according to the pulse width modulation signal. A current detection circuit according to claim 1;
A projector comprising: a controlled circuit unit controlled using the current detection circuit.

Images