JP5942020B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine.

  Pachinko machines have a lottery lottery when a game ball launched in the game area wins the starting prize opening, and the prize winning opening is intermittently released for a certain period by winning the lottery result. It is controlled to the jackpot gaming state that is played (opening per round is one round), which is an advantageous state for the player. The fact that the winner of the jackpot lottery is won, the symbols are variably displayed on a variable display device such as a liquid crystal display called a special symbol game, and the predetermined symbols (generally the same type of symbols) are derived there. To be notified.

  In the jackpot lottery process, for example, the output value of a hardware-configured random number generation circuit is used as a random number value RND for jackpot determination, and it is determined whether or not it is a jackpot state by comparing this with a jackpot winning value Hit. The

  Here, since the counters and latches constituting the random number generation circuit are forcibly reset when the power is turned on, there is a concern about illegal games exploiting this point. That is, since the frequency of the count clock Φ supplied to the counter and the value of the big hit winning value Hit are made clear by obtaining and investigating the gaming machine, the gaming machine is brought into a power reset state by some method, and the counter If an illegal winning switch signal is input from the connector unit aiming at the timing when the counted value coincides with the value of the jackpot winning value Hit, the jackpot state can be intentionally generated.

  Therefore, even when resetting the power supply, the power reset operation is performed by utilizing the variation in the characteristics of the gaming machine in which the power reset timing is changed for each gaming machine, specifically, the passive element or the active element that generates the power reset signal. There has been proposed a gaming machine in which variations are caused (see, for example, Patent Document 1).

JP 2008-295492 A

  An object of the present invention is to provide a gaming machine that can prevent determination of whether to control to an advantageous state using numerical data extracted at different timings.

In order to achieve the above object, a gaming machine according to the present invention provides:
A gaming machine (pachinko gaming machine 1) that can be variably displayed based on a detection signal and can be controlled to an advantageous state (big hit gaming state) advantageous to a player when a specific condition is satisfied,
The detection signal includes a first detection signal and a second detection signal,
Numerical value updating means (random number generation circuit 553, random number sequence change circuit 555) for updating numerical data;
Numerical data storage means (random number latch selector 558B) for storing numerical data updated by the numerical value update means in a numerical data storage area (random number value register 559B) based on the output of the detection signal;
After the numerical data is stored in the numerical data storage area, until the stored numerical data is read, the storage of new numerical data by the numerical data storage means is restricted, and the stored numerical values are stored. Numeric data holding means capable of holding data (prohibiting latching of new numeric data);
Numerical data reading means (steps S221 and S224) for reading numerical data stored in the numerical data storage area;
Decision means (steps S253, S254) for deciding whether or not to control to the advantageous state using the numeric data read by the numeric data reading means;
Non-volatile storage means storing control data;
Data read restriction means for restricting reading of the control data stored in the nonvolatile storage means from outside;
Regardless of whether the variation display based on the first detection signal or the variation display based on the second detection signal, a common variation timing means for measuring the time of the variation display;
Variable means for changing the execution period of a predetermined initial setting process including a security check process for checking whether or not the storage content of the nonvolatile storage means has been changed.
It is characterized by that.

1 is a front view of a pachinko gaming machine according to an embodiment of the present invention. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko machine of FIG. It is a block diagram which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which illustrates the main part of a program management area and a built-in register. It is a figure which shows an example of the setting content in a header and function setting. It is a figure which shows an example of the setting content in 1st random number initial setting, 2nd random number initial setting, and interruption initial setting. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is explanatory drawing which illustrates the random number value counted by the side of a main board | substrate. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is a figure which shows the structural example etc. of a random value acquisition register. It is a figure which shows the structural example etc. of a random number latch selection register. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example etc. of a random number latch flag register. It is a figure which shows the structural example etc. of a random number interrupt control register. It is a figure which shows the structural example etc. of an input port register. It is a figure which shows the structural example of a special figure display result determination table. It is a figure which shows the structural example of a big hit classification determination table. It is a block diagram which shows the structural example of the data holding area for game control. It is a flowchart which shows an example of a security check process. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a random number circuit setting process. It is a flowchart which shows an example of a random number circuit abnormality test | inspection process. It is a flowchart which shows an example of the timer interruption process for game control. It is a flowchart which shows an example of a random number update process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a start winning determination process. It is a flowchart which shows an example of a start winning determination process. It is a flowchart which shows an example of a special symbol normal process. It is a timing chart for demonstrating operation | movement in a random number circuit.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails. In this game area, a game ball as a game medium is shot and shot by a ball hitting device including a shooting motor 61 shown in FIG.

  A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions of the game board 2 (in the example shown in FIG. 1, on the right side of the game area). Each of the first special symbol display device 4A and the second special symbol display device 4B is composed of, for example, 7-segment or dot matrix LEDs (light emitting diodes). Special symbols (also referred to as “special graphics”), which are a plurality of types of identification information (special identification information) that can be displayed, are variably displayed (variable display). For example, each of the first special symbol display device 4A and the second special symbol display device 4B variably displays a plurality of types of special symbols composed of numbers indicating "0" to "9", symbols indicating "-", and the like. To do.

  An image display device 5 is provided near the center of the game area on the game board 2. The image display device 5 is composed of, for example, an LCD (liquid crystal display device) or the like, and forms a display area for displaying various effect images. In the display area of the image display device 5, the first special symbol variable display by the first special symbol display device 4A and the second special symbol variable display by the second special symbol display device 4B in the special symbol game respectively correspond to the variable display. For example, in a decorative symbol display unit serving as a variable display unit divided into a plurality of parts such as three, decorative symbols that are a plurality of types of identification information (decorative identification information) that can be identified are variably displayed. This variable display of decorative designs is also included in the variable display game.

  As an example, “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R are arranged in the display area of the image display device 5. Then, in the special symbol game, any one of the variable display of the first special symbol by the first special symbol display device 4A and the variable display of the second special symbol by the second special symbol display device 4B is started. In response to this, variable display of decorative symbols (for example, vertical or horizontal scroll display) is performed in all of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. Be started. Thereafter, when the fixed special symbol is stopped and displayed as a variable display result in the special symbol game (completely stopped display), the “left”, “middle”, and “right” decorative symbol display portions 5L in the image display device 5 are displayed. At 5C and 5R, the fixed decorative symbol (final stop symbol) that is the variable display result of the decorative symbol is stopped (completely stopped).

  The decorative symbols variably displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R include, for example, eight types of symbols (alphanumeric characters “1” to “8” or Chinese characters). Apply numbers “1” to “8”, English letters “A” to “H”, effect images showing 8 characters related to a given motif, effect images combining numbers, letters or symbols and characters, etc. Each of the decorative symbols has a corresponding symbol number, for example, symbol numbers “1” to “8” for alphanumeric characters indicating “1” to “8”, respectively. Is attached.

  While the decorative symbols are changing, in the decorative symbol display portions 5L, 5C, and 5R of “left”, “middle”, and “right”, for example, from the smallest to the largest symbol numbers, for example, from top to bottom. Alternatively, a scrolling display that flows from the right side to the left side is performed. Then, when the decorative symbol having the largest symbol number (for example, “8”) is displayed, the decorative symbol having the smallest symbol number (for example, “1”) is displayed.

  On the upper part of the first special symbol display device 4A and the second special symbol display device 4B, the first hold indicator 25A and the second hold for displaying the variable display hold number (special figure hold memory number) in an identifiable manner. A display 25B is provided. Here, the holding of the variable display occurs when a game ball enters (starts winning) the first start winning opening formed by the normal winning ball apparatus 6A and the second starting winning opening formed by the ordinary variable winning ball apparatus 6B. To do. That is, the start condition (also referred to as “execution condition”) for executing a variable display game such as a special figure game or a variable display of decorative symbols has been established, but a variable display game based on the previously established start condition is being executed. When the start condition for starting the variable display game is not satisfied due to the fact that the pachinko gaming machine 1 is controlled to the big hit gaming state, the variable display corresponding to the established start condition is suspended. Done. The first hold indicator 25A displays the first hold memory number as the effective start winning ball number that has entered the first start winning port formed by the normal winning ball device 6A so as to be specified. The second hold indicator 25B displays the second hold memory number as the effective start winning ball number that has entered the second start winning port formed by the normal variable winning ball device 6B in an identifiable manner. Each of the first hold indicator 25A and the second hold indicator 25B has, for example, a number (for example, four) of LEDs corresponding to an upper limit value (for example, “4”) in each of the first reserved memory number and the second reserved memory number. It is comprised including.

  Below the image display device 5, an ordinary winning ball device 6A and an ordinary variable winning ball device 6B are provided. The normal winning ball device 6A forms a first start winning opening that is always kept in a certain open state by a predetermined ball receiving member, for example. The normal variable winning ball apparatus 6B is an electric tulip type having a pair of movable wing pieces that are changed into a normal open state that is a vertical position and an expanded open state that is a tilt position by a solenoid 81 for a normal electric accessory shown in FIG. An accessory (ordinary electric accessory) is provided to form a second start winning opening. As an example, in the normally variable winning ball apparatus 6B, the movable wing piece is in the vertical position when the solenoid 81 for the ordinary electric accessory is in the off state, so that the game ball cannot enter the second start winning opening. Closed state. On the other hand, in the normal variable winning ball apparatus 6B, the movable wing piece is in the tilting position when the solenoid 81 for the normal electric accessory is in the on state, so that the game ball can enter the second start winning opening. It becomes an open state.

  A game ball that has entered the first start winning opening formed in the normal winning ball apparatus 6A is detected by, for example, a first start opening switch 22A shown in FIG. A game ball that has entered the second start winning opening formed in the normal variable winning ball apparatus 6B is detected by, for example, a second start opening switch 22B shown in FIG. Based on the detection of the game ball by the first start port switch 22A, a predetermined number (for example, three) of game balls are paid out as prize balls, and the first reserved memory number is set to a predetermined upper limit value (for example, “4”). ) If the following, the first start condition is satisfied. Based on the detection of the game ball by the second start port switch 22B, a predetermined number (for example, three) of game balls are paid out as prize balls, and if the second reserved memory number is equal to or less than a predetermined upper limit value, The second start condition is satisfied.

  A special variable winning ball device 7 is provided below the normal winning ball device 6A and the normal variable winning ball device 6B. The special variable winning ball apparatus 7 includes a large winning opening door that is opened and closed by a solenoid 82 for the large winning opening door shown in FIG. 2, and is opened (first state) and closed (first state) by the large winning opening door. 2) to form a big prize opening. As an example, in the special variable winning ball apparatus 7, when the solenoid 82 for the special prize opening door is in the off state, the special prize opening door closes the special prize opening. On the other hand, in the special variable winning ball apparatus 7, when the solenoid 82 for the big prize opening door is in the ON state, the big prize opening door opens the big winning opening. A game ball that has entered a special winning opening formed in the special variable winning ball apparatus 7 is detected by, for example, a count switch 23 shown in FIG. Based on the detection of the game ball by the count switch 23, a predetermined number (for example, 13) of game balls are paid out as prize balls.

  A normal symbol display 20 is provided at a predetermined position of the game board 2 (on the left side of the game area in the example shown in FIG. 1). As an example, the normal symbol display 20 is composed of 7 segments, dot matrix LEDs, and the like, like the first special symbol display device 4A and the second special symbol display device 4B, and a plurality of types of identification information different from the special symbols. Is displayed (variably displayed) in a variable manner. Such variable display of normal symbols is called a general game (also referred to as “normal game”). The normal symbol display 20 variably displays, for example, a plurality of types of normal symbols composed of numbers indicating “0” to “9”, symbols indicating “−”, and the like. A plurality of types of normal symbols are assigned symbol numbers corresponding thereto. Above the normal symbol display 20, a universal figure holding display 25 </ b> C is provided. The general-purpose hold indicator 25C includes, for example, four LEDs, and displays the general-purpose hold storage number as the number of effective passing balls that have passed through the passing gate 41.

  In addition to the above configuration, the surface of the game board 2 is provided with a windmill for changing the flow direction and speed of the game ball and a number of obstacle nails. In addition, as a winning opening different from the first starting winning opening, the second starting winning opening, and the large winning opening, for example, one or a plurality of general winning openings that are always kept open by a predetermined ball receiving member are provided. May be. In this case, a predetermined number (for example, 10) of game balls may be paid out as a prize ball based on the fact that a game ball that has entered one of the general prize openings is detected by a predetermined general prize ball switch. In the lowermost part of the game area, there is provided an out port through which game balls that have not entered any winning port are taken. Speakers 8L and 8R for reproducing and outputting sound effects and the like are provided at the left and right upper positions of the gaming machine frame 3, and a game effect lamp 9 is provided at the periphery of the game area. A decorative LED may be arranged around each structure (for example, the normal winning ball device 6A, the normal variable winning ball device 6B, the special variable winning ball device 7, etc.) in the game area of the pachinko gaming machine 1.

  At the lower right position of the gaming machine frame 3, there is provided an operation knob 30 serving as a hitting operation handle operated by a player or the like to launch a game ball as a game medium toward the game area. For example, the resilience of the game ball is adjusted according to the operation amount (rotation amount) by the player or the like. At a predetermined position of the gaming machine frame 3 below the gaming area, a game ball paid out as a prize ball or a game ball lent out by a predetermined ball lending machine is held (stored) so as to be supplied to a ball hitting device. ) Is provided. For example, an operation button that can be operated by the player by a pressing operation or the like may be provided at a predetermined position in the gaming machine frame 3 of the pachinko gaming machine 1 such as a central position on the front side of the upper surface of the hitting ball supply tray. Further, below the hitting ball supply tray, there is provided an extra ball receiving tray (lower plate) that holds (stores) game balls that cannot be stored in the hitting ball supply tray.

  Furthermore, a prepaid card unit (card unit) for executing processing for enabling ball lending using a prepaid card or the like may be installed at a predetermined position adjacent to the pachinko gaming machine 1.

  In the normal game with the normal symbol display 20, the normal symbol display 20 shows that the game ball that has passed through the passing gate 41 provided in the game area is detected by the gate switch 21 shown in FIG. After the general chart start condition for executing variable display is established, based on the fact that the general chart start condition for starting variable display of normal symbols, such as the end of the previous general chart game, is established, Be started. In this ordinary game, when a predetermined variable display time elapses after starting the change of the normal symbol, the fixed normal symbol that becomes the variable display result of the normal symbol is completely stopped and displayed. The variable symbol display time may be determined as one of a plurality of variable display times by, for example, extracting numerical data indicating a predetermined random value at the start of each normal game. . If a specific normal symbol (symbol per symbol), such as a number indicating “7”, is stopped and displayed as a fixed normal symbol that becomes a variable display result of the normal symbol in the normal game, the variable symbol display result of the normal symbol is It becomes "per ordinary figure". On the other hand, if a normal symbol other than the symbol per symbol such as a number or symbol other than the number indicating “7” is stopped and displayed as the fixed ordinary symbol, the variable symbol display result of the normal symbol is “ordinary loss”. Become. Corresponding to the fact that the variable symbol display result of the normal symbol is “per standard”, the open control that allows the game ball to win by the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6B being tilted. When a predetermined time elapses, the closing control is performed to return to the vertical position and prevent the game ball from winning a prize.

  The special symbol game by the first special symbol display device 4A is caused by the fact that the game ball that has entered the first starting winning port formed in the normal winning ball device 6A is detected by the first starting port switch 22A shown in FIG. The process starts when the first start condition is satisfied after the first start condition is satisfied. The first start condition is satisfied when the current special figure game using the first special figure can be started, for example, when the previous special figure game, the big hit game state, or the small hit game state is finished. In the special game by the second special symbol display device 4B, a game ball that has entered the second start winning port formed in the normal variable winning ball device 6B is detected by the second start port switch 22B shown in FIG. Is started based on the fact that the second start condition is satisfied after the second start condition is satisfied. The second start condition is satisfied when the current special figure game using the second special figure can be started, for example, when the previous special figure game, the big hit gaming state, or the small hit gaming state is finished.

  In the special symbol game by the first special symbol display device 4A or the second special symbol display device 4B, after a predetermined variable display time elapses after the variable symbol special display is started, the result of the special symbol variable display is determined. The special symbol is displayed as a complete stop. The variable display time of the special symbol is determined as one of a plurality of types of variable display times corresponding to the variation pattern determined at the start of each special game. If a specific special symbol (big hit symbol) is stopped and displayed as a fixed special symbol that will be the variable display result of the special symbol in the special symbol game, it will be a “big hit” as the specific display result, and a specific special that is different from the big bonus symbol If the symbol (small hit symbol) is stopped and displayed, it will be the “small hit” as the predetermined display result. If the special symbol (losing symbol) other than the big hit symbol or small hit symbol is stopped, the non-specific display result will be displayed. It becomes "losing". After the variable display result in the special figure game becomes “big hit”, the game is controlled to the big hit gaming state as the specific gaming state. Further, after the variable display result in the special figure game becomes “small hit”, the game is controlled to the small hit game state different from the big hit game state. In the pachinko gaming machine 1 in this embodiment, as an example, numbers indicating “1”, “3”, and “7” are jackpot symbols, numbers indicating “5” are jackpot symbols, and “−” is indicated. The symbol is a lost pattern.

  In this embodiment, among the special symbols indicating the numbers “1”, “3”, and “7” that are jackpot symbols, the special symbols indicating the numbers “3” and “7” are 15 round jackpot symbols, A special symbol indicating the number “1” is a two-round jackpot symbol. In the big hit gaming state (15 round big hit state) as the first specific gaming state controlled after the 15 round big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, the open / close plate of the special variable winning ball apparatus 7 is The special variable winning ball apparatus 7 is played by opening the large winning opening in a predetermined period (for example, 29 seconds) which is the first period or until a predetermined number (for example, 9) of winning balls are generated. A round is performed that changes to a first state that is advantageous to the user. In this way, the open / close plate that opened the grand prize opening during the round receives the game ball falling on the surface of the game board 2, and then closed the grand prize opening to play the special variable prize ball device 7 as a game. Change to the second state, which is disadvantageous to the person, and finish one round. In the 15 round big hit state, the number of executions of the round, which is the open cycle of the big prize opening, is the first number (for example, “15”).

  In the big hit gaming state (two round big hit state) as the second specific gaming state controlled after the two round big hit symbol is stopped and displayed as the confirmed special symbol in the special figure game, the special variable winning ball apparatus 7 is played in each round. The period for changing to the first state that is advantageous to the player (the period in which the big prize opening is opened by the opening / closing plate) is a second period (for example, 0.5 seconds) shorter than the first period in the 15 round big hit state. . In the 2 round big hit state, the number of executions of the round is a second number (for example, “2”) smaller than the first number in the 15 round big hit state.

  Further, among the special symbols indicating the numbers “3” and “7” which are the 15-round jackpot symbol, the special symbol indicating the number “3” is stopped and displayed as the confirmed special symbol in the special game 15 After the round big hit state is over, as one of the special game states, the special symbol variation time (special diagram variation time) in the special figure game is controlled to be a short time state as compared with the normal state. Here, the normal state is a game state other than a special game state such as a big hit game state or a special game state such as a short-time state, and an initial setting state of the pachinko gaming machine 1 (for example, when a system reset is performed) Thus, the same control as in the state in which the initialization process is executed after power-on is performed. If the time-short state is terminated when any of the conditions of the special game is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit” is satisfied first, Good. Like the special symbol indicating the number “3”, the 15 round jackpot symbol controlled to the short-time state or the normal state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is This is usually referred to as a big hit symbol (also referred to as a “non-probable big hit symbol”). The variable display mode of special symbols and decorative symbols when the confirmed special symbol in the special figure game is a normal jackpot symbol is variable to “normal” (also referred to as “normal jackpot”) when the variable display result is “big hit”. It is referred to as a display mode (also referred to as “big hit type”).

  Out of the special symbols showing the numbers “3” and “7” that will be the 15-round jackpot symbol, the 15-round jackpot is based on the special symbol showing the number “7” being stopped and displayed as a confirmed special symbol in the special game. After the state is over, or after the two round jackpot state is over based on the fact that the special symbol indicating the number “1” that becomes the two-round jackpot symbol is stopped and displayed as the confirmed special symbol in the special figure game, As one of the special game states different from the normal game state, for example, the special figure change time is shortened compared to the normal state, and the probability change state (high probability game state) in which probability change control (probability change control) is continuously performed is controlled. Is done. In this probability change state, the variable display result of each special figure game and the decorative symbol variable display is improved so that the probability that the variable display result becomes “big hit” and is further controlled to the big hit gaming state is higher than in the normal state. Such a probability change state may be continued until the next variable display result becomes “big hit” regardless of the number of executions of the special game. On the other hand, after the certainty change state is reached, any one of the conditions that the special game is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit” is first. You may make it complete | finish when it is materialized. In addition, even if the special figure game is executed a predetermined number of times in the probability change state or before the variable display result is “big hit”, the probability change state ends at a predetermined rate when the special figure game is started. There may be.

  Like the special symbol indicating the number “7”, the 15-round jackpot symbol controlled to the probable change state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is a probabilistic big hit symbol. It is called. The variable display mode of special symbols and decorative symbols when the confirmed special symbol in the special figure game becomes a probable big hit symbol is variable "probable change" (also called "probable big hit") when the variable display result is "big hit". It is referred to as a display mode (also referred to as “big hit type”). Like the special symbol indicating the number “1”, the two-round big hit symbol controlled to the probable change state after the big hit gaming state based on being stopped and displayed as the confirmed special symbol in the special figure game is a sudden big hit symbol. It is called. The variable display mode for special symbols and decorative symbols when the confirmed special symbol in the special figure game is a sudden big hit symbol is “surprise” (“surprise big hit” or “sudden probability big hit” when the variable display result is “big hit”. ")" As a variable display mode (also referred to as "big hit type").

  In the probabilistic state and the short time state, the normal symbol display unit 20 controls the normal symbol variable display time in the normal symbol game to be shorter than that in the normal state, and the normal symbol variable display result of each time the normal symbol game is “normal”. Control for improving the probability of “per figure” than in the normal state, when the tilt time of the movable blade piece in the normal variable winning ball apparatus 6B based on the fact that the variable display result is “per normal figure” is in the normal state The player can be more likely to satisfy the second start condition by increasing the possibility that the game ball will enter the second start winning opening, such as a control for making it longer and a control for increasing the number of tilts than in the normal state. Control which is advantageous to the user is performed.

  After the small hit symbol is stopped and displayed as the confirmed special symbol in the special symbol game, the small hit game state different from the big hit game state is controlled. In this small hit gaming state, a variable winning operation for changing the special variable winning device 7 to the first state advantageous to the player is performed as in the two round big hit state. That is, in the small hit game state, for example, the operation of opening the large winning opening over the second period by the opening / closing plate provided in the special variable winning ball apparatus 7 is repeatedly executed until the second number of times is reached. After the small hit gaming state ends, the gaming state is not changed, and the game state before the variable display result becomes “small hit” is continuously controlled. However, if it is determined to end the short-time state corresponding to the variable display game in which the variable display result is “small hit”, the normal state is controlled after the end of the small hit gaming state. It will be.

  On the display screen of the image display device 5, variable display of decorative symbols is performed corresponding to the variable display of special symbols by the first special symbol display device 4 </ b> A and the second special symbol display device 4 </ b> B. That is, on the display screen of the image display device 5, for example, the “left”, “middle”, or “right” decorative symbol display section 5 </ b> L based on the fact that either the first start condition or the second start condition is satisfied. In all of 5C and 5R, decorative symbols are displayed in an accelerated manner (all symbols accelerated display). When a predetermined speed is reached, the decorative symbols are displayed at a constant speed (all symbols are displayed at a constant speed). Such all symbols acceleration display and all symbols constant speed display are included in all symbol variations that variably display the ornament symbols in all of the “left”, “middle”, and “right” ornament symbol display portions 5L, 5C, and 5R. . After all the symbols change, for example, display the symbols in a decelerating display (each symbol deceleration display) in a predetermined order such as “Left” → “Right” → “Medium”. While stopping and displaying, for example, temporary stop display that causes slight shaking or expansion / contraction is performed. Then, when the elapsed time from the start of the variable display of the decorative pattern reaches the variable display time determined based on the variation pattern or the like, the fixed decorative pattern that is the variable display result is displayed in a completely stopped state.

  After all symbols change is started, the decorative symbols are reach-displayed on all or some of the decorative symbol display portions 5L, 5C, and 5R of “left”, “middle”, and “right”. It may be derived and displayed in the state. Here, the reach display state refers to a decorative symbol that has not yet been derived and displayed when the decorative symbol derived and displayed on the display screen of the image display device 5 constitutes a part of the jackpot combination (“reach variation symbol”). ")" Is a display state in which the variation continues, or a display state in which all or part of the decorative symbols change synchronously while constituting all or part of the jackpot combination. Specifically, some of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R (for example, “left” and “right” decorative symbol display portions 5L and 5R, etc.) The remaining decorative symbol display part (for example, “medium”) that has not yet been derived and displayed when the decorative symbol (for example, the decorative symbol indicating the alphanumeric character “7”) that constitutes the determined jackpot combination is derived and displayed. In the symbol display portion 5C, etc., the decorative symbols are changing, or the decorative symbols are big hits in all or part of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. This is a display state that changes in synchronization while constituting all or part of the combination. Corresponding to the reach display state, an effect image such as an animation image or a live-action image different from the decorative design is displayed on the display screen of the image display device 5, the display mode of the background image is changed, There are times when the variation pattern of the decorative design is changed. Such an effect image display, background image display mode change, and decorative pattern change mode change are referred to as reach effect display (or simply reach effect). Some reach productions are set such that when they appear, a big hit is likely to occur (a high probability is a big win) compared to a normal reach production (normal reach). Such a special reach production is also called a super reach production (or simply “super reach”).

  In addition, during the variable display of decorative symbols, unlike reach production, there is a possibility that the decorative symbols may be derived and displayed in the reach state, and that the variable display result may be a “hit”, There may be a case where a specific effect for informing the player is given in accordance with a variable display mode of the decorative design. In this embodiment, specific effects such as “sliding”, “pseudo-continuous”, “intro”, “development opportunity”, and “end of development opportunity” are set to be executable. These specific effects are not directly related to the present invention, and thus detailed description thereof is omitted.

  Furthermore, during the variable display of the decorative pattern, unlike the reach effect or the specific effect, for example, by displaying the decorative pattern in a display mode other than the variable display mode of the decorative pattern, such as displaying a predetermined character image or message image. A notice effect may be executed to notify the player that the variable display state may become a reach state and that the variable display result may be a “hit”. For example, the notice effect such as “character display”, “step-up image”, and “background change” may be set to be executable. Since these notice effects are not directly related to the present invention, detailed description thereof is omitted.

  If a special symbol that will be a lost symbol is stopped and displayed as a special symbol to be confirmed in the special symbol game, the decorative symbol variable display state will not reach the reach state after the variable symbol variable display starts. There are cases where a fixed decorative symbol that is a non-reach combination or a fixed decorative symbol that is one of a plurality of types of development chances is stopped and displayed. Such a decorative display variable display mode is referred to as a “non-reach” (also referred to as “normal loss”) variable display mode when the variable display result is “losing”.

  When a special symbol that becomes a losing symbol is stopped and displayed as a confirmed special symbol in the special symbol game, it corresponds to the fact that the decorative symbol variable display state has reached the reach state after the decorative symbol variable display has started. Then, after the reach effect is executed, or when the reach effect is not executed, a confirmed decorative pattern that becomes a predetermined reach-losing combination may be stopped and displayed. Such a variable display result of the decorative design is referred to as a variable display mode of “reach” (also referred to as “reach lose”) when the variable display result is “losing”.

  When the special symbol indicating the number “3”, which is a normal big hit symbol, is stopped and displayed as a special symbol to be confirmed in the special figure game as the 15 round big hit symbol, the variable symbol display state of the decorative symbol is reached. Corresponding to the state, after a predetermined reach effect is executed, a predetermined decorative symbol that is a predetermined normal jackpot combination is stopped and displayed. Here, for example, the symbol numbers that are variably displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R in the image display device 5 are the determined decorative symbols that are usually the big hit combinations. Among the decorative symbols “1” to “8”, any one of the decorative symbols whose symbol numbers are an even number “2”, “4”, “6”, “8” is “left”, “middle”, What is necessary is just to be stopped and displayed on the predetermined effective line in each of the “right” decorative symbol display portions 5L, 5C, and 5R. In this way, the decorative symbols having the even number “2”, “4”, “6”, “8” constituting the normal jackpot combination are referred to as normal symbols (also referred to as “non-probable variation symbols”). Then, in response to the confirmed special symbol in the special figure game becoming the normal jackpot symbol, after the predetermined reach effect is executed, the decorative display variable display mode in which the fixed ornament symbol of the normal jackpot combination is stopped and displayed is This is referred to as a “normal” (also referred to as “normal jackpot”) variable display mode (also referred to as a jackpot type) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the “normal” variable display mode, the game is controlled to the 15 round big hit gaming state, and when the 15 round big hit state is finished, it is controlled to the short time state or the normal state. become.

  When the special symbol indicating the number “7”, which is the probability variable big hit symbol, is stopped and displayed as a special symbol to be confirmed in the special figure game as a 15-round big hit symbol, the variable display state of the decorative symbol is reached. Corresponding to the state, after the reach effect similar to the case where the big hit type is “normal” is executed, a fixed decorative symbol that becomes a predetermined probability variation big hit combination may be stopped and displayed. Here, the confirmed decorative symbols that are the probable big hit combinations are, for example, symbol numbers that are variably displayed on the decorative symbol display portions 5L, 5C, and 5R of “left”, “middle”, and “right” in the image display device 5. Among the decorative symbols “1” to “8”, any one of the decorative symbols whose symbol numbers are odd numbers “1”, “3”, “5”, “7” are “left”, “middle”, What is necessary is just to be stopped and displayed on the predetermined effective line in each of the “right” decorative symbol display portions 5L, 5C, and 5R. In this way, the decorative symbols having odd numbers “1”, “3”, “5”, and “7” constituting the probability variation big hit combination are referred to as probability variation symbols. Then, in response to the confirmed special symbol in the special figure game becoming a probable big hit symbol, after the reach effect is executed, the fixed decorative symbol of the probable big jackpot combination is stopped and displayed. This is referred to as a variable display mode (also referred to as a jackpot type) of “first probability change” when the display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “first positive change”, the game is controlled to the 15th round big hit state, and when the 15th round big hit state ends, it is controlled to the positive change state. .

  When the special symbol indicating the number “7”, which is the probability variable big hit symbol, is stopped and displayed as a special symbol to be confirmed in the special figure game as a 15-round big hit symbol, the variable display state of the decorative symbol is reached. Corresponding to the state, after the reach effect different from the case where the variable display mode is “normal” is executed, the fixed decorative symbol that becomes a predetermined probability variation big hit combination may be stopped and displayed. In this way, in response to the confirmed special symbol in the special figure game becoming a probable big hit symbol, after the reach effect different from the case where the decorative symbol variable display mode is “normal” is executed, The variable display mode of the decorative pattern in which the fixed decorative pattern is stopped and displayed is referred to as a “second probability change” variable display mode (also referred to as a jackpot type) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “second positive change”, the control is made to the 15 round big hit state, and when the 15 round big hit state is finished, the variable change state is controlled to the positive change state. .

  When the special symbol indicating the number “7”, which is the probability variable big hit symbol, is stopped and displayed as a special symbol to be confirmed in the special figure game as a 15-round big hit symbol, the variable display state of the decorative symbol is reached. Corresponding to the state, after the reach effect similar to the case where the decorative symbol variable display mode is “normal” is performed, the fixed symbol combination of the normal jackpot combination may be stopped and displayed. In this way, in response to the confirmed special symbol in the special figure game becoming a probable big hit symbol, after the reach effect similar to the case where the variable display mode of the decorative symbol is “normal” is executed, The decorative display variable display mode in which the fixed decorative design is stopped and displayed is referred to as a “third probability change” variable display mode (also referred to as a jackpot type) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “third probability change”, the game is controlled to the 15 round big hit state, and when the 15 round big hit state is finished, it is controlled to the positive change state. .

  In this way, when the big hit type when the variable display result is “big hit” is “first probability variation” or “second probability variation”, the fixed decorative symbol that becomes the probability variation big hit combination by variable display of the decorative symbol Is stopped and displayed, it is determined that the probability change state is reached after being controlled to the 15 round big hit state. On the other hand, when the big hit type when the variable display result is “big hit” is “third probability variation”, the variable symbol display is normally performed in the same manner as when the big hit type is “normal”. The confirmed decorative pattern that is a jackpot combination is stopped and displayed. Therefore, when the big hit type is “third probability variation”, the player cannot recognize whether or not the probability variation state is obtained from the variable display result of the decorative symbols. That is, the confirmed decorative symbol that becomes the probability variation jackpot combination is included in the specific display result that is determined to be controlled to the jackpot gaming state, and is included in the special display result that is determined to be controlled to the probability variation state. On the other hand, a confirmed decorative pattern that is normally a big hit combination is included in a specific display result (non-special display result) other than a special display result that is not determined to be controlled in a certain variation state.

  When a special symbol indicating the number “1” that is a two-round jackpot symbol is stopped and displayed as a confirmed special symbol in the special symbol game, the decorative symbol variable display state does not reach the reach state, and a predetermined non- A fixed decorative symbol that is a reach combination is stopped and displayed, a fixed decorative symbol that is one of multiple types of development chances is stopped or displayed, or a decorative symbol that is preset as multiple types of chances of chance There is a case where a fixed decorative symbol that is one of the combinations is stopped and displayed. In addition, when the special symbol indicating the number “1”, which is a two-round jackpot symbol, is stopped and displayed as a confirmed special symbol in the special symbol game, the variable symbol display state of the decorative symbol is changed to the reach state. Then, after a predetermined reach effect is executed, a confirmed decorative pattern that becomes a predetermined reach-losing combination may be stopped and displayed. In this way, in response to the confirmed special symbol in the special symbol game becoming a special symbol indicating the number “1”, which is a two-round jackpot symbol, various decorative decorative variable display modes in which various confirmed decorative symbols are stopped and displayed. Is referred to as a variable display mode (also referred to as a jackpot type) of “surprise accuracy” (also referred to as “sudden probability big hit” or “sudden probability change big hit”) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “surprise accuracy”, it is controlled to the two round big hit state, and when the two round big hit state is finished, it is controlled to the probability changing state.

  When a special symbol indicating the number “5” as a small hit symbol is stopped and displayed as a confirmed special symbol in the special symbol game, the ornament is displayed in the same manner as when the variable display mode of the decorative symbol is “surprise”. After the variable display of the symbol is performed, the fixed decorative symbol that is a predetermined non-reach combination is stopped, the fixed decorative symbol that is one of multiple types of development opportunities is stopped, or There is a case where a fixed decorative symbol that is a predetermined reach-losing combination is stopped and displayed. In this way, in response to the confirmed special symbol in the special symbol game becoming a special symbol indicating the number “5” as the small hit symbol, the variable display mode of the decorative symbols on which various confirmed decorative symbols are stopped and displayed is as follows. , “Small hit” variable display mode (also referred to as “small hit type”). Here, the confirmed decorative pattern that is one of the multiple types of random chances is stopped only when the variable display mode of the decorative pattern is “Accuracy”, and when the variable display mode is “Small”. Is not stopped and displayed as a confirmed decorative pattern. In other words, when a fixed decorative pattern that is a chance of a chance of success is stopped and displayed in a variable display of decorative symbols, it is determined that the variable display result is “big hit” by the variable display mode of “accuracy”. After the variable display result is “small hit”, the game is controlled to the small hit gaming state in which the variable winning action similar to the two round big hit state is performed, and when the small hit gaming state ends, the gaming state is not changed. Therefore, the gaming state before the variable display result becomes “small hit” continues. If it is determined that the probability change state or the short-time state is to be ended in response to the variable display game in which the variable display result is “small hit”, the normal state is returned after the end of the small hit gaming state. Will be controlled.

  If the big hit type when the variable display result is “big hit” is any one of “normal”, “first probability variation”, or “third probability variation”, a specific variation display is made during variable display of decorative symbols. Promotional effects may be executed during the change. In the fluctuating promotion effect, a decorative symbol that is normally a big hit combination is temporarily displayed on the effective lines of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R on the image display device 5. After that, for example, the decorative pattern display portions 5L, 5C, and 5R of “left”, “middle”, and “right” are changed again in a state where the same decorative pattern is aligned, and the decorative symbol that becomes a probable big hit combination, Any of the decorative symbols that are normally a big hit combination is stopped and displayed as a finalized decorative symbol (final stop display). Here, when the changing promotion effect is executed corresponding to the fact that the decorative symbol variable display mode is “normal” or “third probability change”, the temporarily changing display is performed as the changing promotion effect. After changing the decoration symbol again, a promotion promotion failure during change is performed in which the fixed decoration symbol which is normally a big hit combination is stopped and displayed. On the other hand, when the changing promotion effect is executed in response to the variable display mode being “first probability change”, the temporarily stopped display of the decorative design is changed again as the changing promotion effect. After that, the promotion success effect during change is performed to stop and display the confirmed decorative pattern that becomes the probability variation big hit combination.

  When the big hit type when the variable display result is “big hit” is either “normal” or “third probability variation”, the variable display result is stopped and displayed, and then controlled to the 15 round big hit state. Thereafter, during the period until the 15-round big hit state is completed, a promotion effect during the big hit is executed as a notification effect as to whether or not to control to the probable change state.

  In the jackpot promotion effect, there is a jackpot promotion promotion effect that informs that there is a promotion that the gaming state becomes a probable change state even though the confirmed decorative pattern is a normal jackpot combination, and that there is no promotion that becomes a probable change state There is a promotion promotion failure during the jackpot to be notified. As an example, in the jackpot promotion effect, the decorative symbol is variably displayed in the display area of the image display device 5 and either the normal symbol or the probability variation symbol is stopped and displayed as the effect display result. At this time, the normal symbol is stopped and displayed as the effect display result in the jackpot promotion promotion effect, while the probable change symbol may be stopped and displayed as the effect display result in the jackpot promotion promotion effect.

  The pachinko gaming machine 1 includes various power supply boards 10, a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a payout control board 15, a launch control board 17 as shown in FIG. A control board is mounted. The pachinko gaming machine 1 is also equipped with a relay board 18 for relaying various control signals transmitted between the main board 11 and the effect control board 12. In addition, various control boards such as an information terminal board and an interface board are disposed on the back surface of the pachinko gaming machine 1. The interface board is a control board interposed between the payout control board 15 and the card unit when the card unit is installed adjacent to the pachinko gaming machine 1.

  The power supply board 10 is installed independently of each control board such as the main board 11, the effect control board 12, and the payout control board 15, and generates a voltage used by each control board and mechanism component in the pachinko gaming machine 1. For example, the power supply board 10 generates AC 24 V, VLP (DC +24 V), VSL (DC +30 V), VDD (DC +12 V), VCC (DC +5 V), and VBB (DC +5 V) as shown in FIG. For example, as shown in FIG. 3, the power supply board 10 includes a transformer circuit 301, a DC voltage generation circuit 302, a power supply monitoring circuit 303, and a clear switch 304. In addition, the power supply board 10 is provided with a power switch for executing or cutting off the power supply to each control board and the mechanical components in the pachinko gaming machine 1.

  As shown in FIG. 3, AC24V output from the transformer circuit 301 is transmitted to the payout control board 15 via a predetermined connector or a power supply line, for example. The VLP is transmitted to the lamp control board 14 via, for example, a predetermined connector or a power supply line. VSL, VDD, and VCC are transmitted to the main board 11, the lamp control board 14, and the payout control board 15 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 11 and the payout control board 15 through, for example, a predetermined connector and a power supply line.

  The power monitoring circuit 303 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes a power monitoring unit that outputs a power interruption signal. For example, the power supply monitoring circuit 303 has a predetermined period of time (56 milliseconds as an example) during which the predetermined voltage (VLP as an example) used in the pachinko gaming machine 1 is equal to or lower than a predetermined value (+20 V as an example). When the above is continued, a power-off signal is output. The power cut-off signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then transmitted to the payout control board 15 via a predetermined connector or signal line, thereby giving out payout control. The signal is transmitted from the substrate 15 to the main substrate 11.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 303 outputs a reset signal (sets to a low level) when a predetermined period elapses after the power-off circuit 303 outputs a power-off signal (sets to a low level). ) In the predetermined period, for example, the game control microcomputer 100 mounted on the main board 11 and the payout control microcomputer 150 mounted on the payout control board 15 shown in FIG. It is sufficient if the time is sufficient for execution. That is, the power monitoring circuit 303 outputs a power-off signal as a power failure signal, and after the game control microcomputer 100 and the payout control microcomputer 150 complete execution of predetermined power-off processing, The reset signal is output (set to low level). The game control microcomputer 100 and the payout control microcomputer 150 that have received the reset signal output from the power supply monitoring circuit 303 are in an operation stop state, and execution of various control processes is stopped. In addition, when the power supply to the pachinko gaming machine 1 is started, for example, when a predetermined voltage (VCC as an example) exceeds a predetermined value (+5 V as an example), the power monitoring circuit 303 stops outputting the reset signal (high Level).

  FIG. 4 is a timing diagram schematically showing the states of AC 24 V, VLP, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 4, when the power supply to the pachinko gaming machine 1 is started, VLP and VCC gradually reach specified values (DC + 24V and DC + 5V). At this time, when VLP exceeds the first predetermined value, the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. When VCC exceeds the second predetermined value, the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VLP and VCC gradually decrease. At this time, when the VLP drops to the first predetermined value, the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). When VCC decreases to the second predetermined value, the power supply monitoring circuit 303 outputs the reset signal as an ON state (sets it to a low level).

  When the power supply to the pachinko gaming machine 1 is essentially stopped by turning off the power switch, necessary processing such as data saving is performed in the power-off process executed by the output of the power-off signal. Later, an infinite loop is entered to wait for the power supply to be cut off. However, even if a momentary interruption occurs when the voltage drops for a certain period and then recovers to the original voltage, a power interruption signal may be output. In this case, too, the power interruption process is executed and an infinite loop is entered. May end up. In this case, since the process for playing the game cannot be executed even if the voltage recovers, for example, when the time of the infinite loop reaches a predetermined time, the system is reset and the program is started from the beginning as when the power is turned on. Processing can be executed. Or, instead of entering an infinite loop at the end of the power-off process, a process for polling the power-off signal is executed, and when a monitoring result indicating that the power-off signal has changed to the off state is obtained, the system It is also possible to execute a process from the beginning of the program in the same way as when the power is turned on by applying a reset.

  The clear switch 304 included in the power supply substrate 10 illustrated in FIG. 3 has a push button structure, for example, and outputs a clear signal in response to an operation such as pressing. The clear signal may be an electric signal that is turned on when the clear signal is at a low level, for example. The clear signal output from the clear switch 304 is transmitted to the main board 11 via a predetermined connector or signal line, for example, and is transmitted from the main board 11 to the payout control board 15. When the clear switch 304 is not operated, the output of the clear signal is stopped (set to a high level).

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is a sub-side mainly composed of a random number setting function used in a special game, a function of inputting a signal from a switch arranged at a predetermined position, an effect control board 12, a payout control board 15, and the like. It has a function of outputting and transmitting a control command as an example of command information to the control board as a control signal, a function of outputting various information to the hall management computer, and the like. In addition, the main board 11 performs on / off control of each LED (for example, segment LED) constituting the first special symbol display device 4A and the second special symbol display device 4B, and thereby the first special diagram and the second special diagram. Variable display of a predetermined display pattern such as controlling the variable display of the normal symbol display 20 and controlling the variable symbol display of the normal symbol display 20 by controlling the lighting / extinguishing / coloring control of the normal symbol display 20. It also has a function to control. As shown in FIG. 2, for example, the main board 11 includes a game control microcomputer 100, a control clock generation circuit 111, a random number clock generation circuit 112, a switch circuit 114, and a solenoid circuit 115. . A game start switch 31 is provided on the main board 11.

  Here, the control clock generation circuit 111 generates a control clock CCLK that becomes an oscillation signal having a predetermined frequency outside the game control microcomputer 100. The control clock CCLK generated by the control clock generation circuit 111 is supplied to the clock circuit 502 via a control external clock terminal EXC of the game control microcomputer 100 as shown in FIG. 5, for example. The random number clock generation circuit 112 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the game control microcomputer 100. The random number clock RCLK generated by the random number clock generation circuit 112 is supplied to the random number circuit 509 via the random number external clock terminal ERC of the game control microcomputer 100 as shown in FIG. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 may be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111.

  The switch circuit 114 takes in detection signals from various switches for detecting game balls and transmits them to the game control microcomputer 100. The solenoid circuit 115 transmits a solenoid drive signal from the game control microcomputer 100 to the solenoids 81 and 82. The game start switch 31 has, for example, a push button structure, and the pachinko gaming machine 1 closes the gaming machine frame 3 so that the player can not normally touch the pachinko gaming machine 1 in a state in which the player plays a normal game. What is necessary is just to be arrange | positioned. Then, for example, when the pachinko gaming machine 1 is turned on or when the system is reset, the pachinko gaming machine 1 is operated to instruct the game start after the initial setting.

  As shown in FIG. 2, wiring for transmitting detection signals from the gate switch 21, the first start port switch 22 </ b> A, the second start port switch 22 </ b> B, and the count switch 23 is connected to the main board 11. Negative logic is applied to the detection signals output from the gate switch 21, the first start port switch 22A, the second start port switch 22B, and the count switch 23, and it is high when the passing of the game ball is not detected. The level is low when the passing of a game ball is detected. For example, the first start condition is established on condition that the detection signal from the first start port switch 22A is continuously at a low level for a certain period or longer. The same applies to the second start condition and the normal start condition. When the voltage drops, the detection signal of the first start port switch 22A changes to a low level, but the starting condition cannot be satisfied due to a momentary interruption in which the voltage drops for an extremely short time.

  The main board 11 includes a first special symbol display device 4A, a second special symbol display device 4B, a normal symbol display device 20, a first hold display device 25A, a second hold display device 25B, and a general drawing hold display device 25C. Wiring for transmitting a command signal for performing display control such as is connected. Further, the main board 11 is connected to wiring for transmitting command signals for performing drive control, such as a solenoid 81 for an ordinary electric accessory and a solenoid 82 for a prize winning door.

  Various control commands are transmitted between the main board 11 and the effect control board 12, for example, by performing serial communication only in a single direction from the main board 11 to the effect control board 12 via the relay board 18. The The effect control board 12 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the relay board 18, and receives the image display device 5, speakers 8L, 8R. In addition, various circuits for controlling electric parts (production device) for production such as a light emitter such as a game effect lamp 9 are mounted. That is, the effect control board 12 has a function of controlling the display operation in the image display device 5, the sound output operation from the speakers 8L and 8R, the lighting operation and the extinguishing operation in the light emitter such as the game effect lamp 9 and the like. . The effect control board 12 is connected to wiring for transmitting a control signal to the sound control board 13 and the lamp control board 14, wiring for transmitting an image data signal to the image display device 5, and the like.

  The main board 11 may be provided with a main board side connector corresponding to the relay board 18, for example, and an output buffer circuit may be connected between the main board side connector and the game control microcomputer 100. . This output buffer circuit can pass a control signal only in the direction from the main board 11 to the effect control board 12 via the relay board 18, for example, and prevents the signal input from the relay board 18 to the main board 11. . Therefore, there is no room for signals to be transmitted from the production control board 12 or the relay board 18 side to the main board 11 side.

  For example, the relay board 18 may be provided with a transmission direction regulating circuit in a wiring for transmitting a control signal from the main board 11 to the effect control board 12. The transmission direction regulating circuit includes a diode having an anode connected to the main board connector corresponding to the main board 11 and a cathode connected to the presentation control board connector corresponding to the presentation control board 12, and one end connected to the cathode of the diode. And the other end of which is connected to the ground (GND). With this configuration, the transmission direction regulating circuit can prevent the signal from being input from the effect control board 12 to the relay board 18 and pass the signal only in the direction from the main board 11 to the effect control board 12. Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In this embodiment, a transmission direction regulating circuit is provided in the wiring for transmitting a control signal in the relay board 18, and an output buffer circuit is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing, illegal signal input to the main board 11 from the outside can be prevented.

  Various control commands and notification signals are transmitted between the main board 11 and the payout control board 15 by, for example, bidirectional serial communication. The payout control board 15 is a sub-side control board independent of the main board 11, receives a control command and a notification signal transmitted from the main board 11, and controls the payout operation of the game ball by the payout motor 51. Various circuits are installed. That is, the payout control board 15 has a function of controlling the award ball payout operation by the payout motor 51. The payout control board 15 receives wiring for receiving detection signals from the full tank switch 26 and the ball break switch 27, and detection signals from the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. Wiring for is connected. In addition, a wiring for transmitting a command signal for performing payout control of the game ball in the payout motor 51 and a command signal for performing display control in the error display LED 74 are transmitted to the payout control board 15. Wiring for communication with the card unit is connected via the interface board.

  Here, the full tank switch 26 is installed on the side wall of the surplus ball passage that communicates between the striking ball supply tray and the surplus ball receiving tray, for example, below the back of the game board 2, and detects the full tank of the surplus ball receiving tray. Is. When a lot of game balls based on award balls or ball lending requests are paid out and the batting supply tray is full, and the game balls reach the contact port, the game balls are passed through the surplus ball passage. It is led to the extra ball tray. When the game ball is further paid out, for example, a predetermined sensing lever presses the full switch 26 to turn on.

  In addition, the ball break switch 27 is installed downstream of the guide rail that guides the game ball to the payout device in which the payout motor 51 is installed, for example, on the back of the game board 2, and via a curve rod downstream of the guide rail. This is for detecting the presence or absence of game balls in two rows of ball passages communicated with each other. As an example, the ball break switch 27 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path, and the maximum payout number (for example, 100) It is possible to confirm that at least 25 pieces corresponding to a circle are secured.

  The error release switch 73 is a switch for releasing the error state by software reset when the payout control microcomputer 150 is controlled to a predetermined error state. The error display LED 74 is composed of, for example, a 7-segment LED, and is used to display error codes corresponding to various errors based on an error flag set by the payout control microcomputer 150.

  The launch control board 17 shown in FIG. 2 is for controlling the launch operation of the game ball by a predetermined launch device in accordance with the operation amount of the operation knob 30. For example, the firing control board 17 has wiring for transmitting a drive signal from the power supply board 10 or the main board 11, wiring for transmitting a connection signal from the card unit via the payout control board 15 and the interface board, and an operation knob 30. Are connected to the firing motor 61. The firing control board 17 adjusts the driving force of the firing motor 61 in accordance with the operation amount of the operation knob 30. For example, the launch motor 61 elastically deforms the launch spring by a driving force adjusted by the launch control board 17, and transmits the biasing force of the launch spring to the hitting hammer to hit the game ball, thereby operating the game ball on the operation knob 30. It is fired toward the game area at a speed corresponding to the operation amount.

  The control command transmitted from the main board 11 to the effect control board 12 via the relay board 18 is, for example, an effect control command transmitted as an electric signal. In this embodiment, the effect control command is set for transmission by the CPU 505 (see FIG. 5) provided in the game control microcomputer 100 mounted on the main board 11, and the game control microcomputer 100 is based on the setting. Is transmitted to the effect control board 12 by a serial communication circuit 511 (see FIG. 5). In the following description, the transmission operation of the effect control command from the main board 11 to the effect control board 12 includes a series of operations by the CPU 505 and the serial communication circuit 511 provided in the game control microcomputer 100. To do. In this case, on the side of the effect control board 12, for example, the CPU of the effect control microcomputer 120 performs an interrupt process based on a reception interrupt request generated when communication data in the serial signal format transmitted from the main board 11 is received. By executing, the effect control command may be captured and stored in a predetermined buffer (for example, a reception command buffer for effect).

  The effect control command includes, for example, a display control command used for controlling an image display operation in the image display device 5, a voice control command used for controlling sound output from the speakers 8L and 8R, and a game effect lamp 9. The lamp control command used for controlling the lighting operation of the light emitter is included.

  FIG. 5 shows a configuration example of the game control microcomputer 100 mounted on the main board 11. A game control microcomputer 100 shown in FIG. 5 is, for example, a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset / interrupt controller 504, a CPU (Central Processing Unit). ) 505, ROM (Read Only Memory) 506, RAM (Random Access Memory) 507, CTC (Counter / Timer Circuit) 508, random number circuit 509, PIP (Parallel Input Port) 510, and serial communication circuit 511 And an address decoding circuit 512.

  FIG. 6 shows an example of an address map in the game control microcomputer 100. As shown in FIG. 6, the area from address 0000H to address 1FFFH is allocated to the ROM 506 and includes a user program area and a program management area. FIG. 7A shows an example of the usage and contents of the main part of the program management area in the ROM 506. The area from address 2000H to address 20FFH is a built-in register area assigned to the built-in register of the game control microcomputer 100. FIG. 7B shows an example of the usage and contents of the main part of the built-in register area. An area from address 7E00H to address 7FFFH is a work area assigned to the RAM 507, and can be assigned to an I / O map or a memory map. An area from address FDD0H to address FDFBH is an XCS decode area allocated to the address decode circuit 512.

  The program management area is a storage area for storing information necessary for the CPU 505 to execute the user program. As shown in FIG. 7A, the program management area includes a header KHDR, a function setting KFCS, a first random number initial setting KRS1, a second random number initial setting KRS2, an interrupt initial setting KIIS, a security time setting KSES, and the like. It is.

  The header KHDR stored in the program management area indicates the internal data read setting in the game control microcomputer 100. FIG. 8A illustrates the correspondence between setting data and operation in the header KHDR. Here, in the game control microcomputer 100, the ROM read prevention function and the bus output mask function can be set. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 506 provided in the game control microcomputer 100, and the data stored in the ROM 506 cannot be read in a state where the read is prohibited. The bus output mask function is an address bus output, data bus output, and control signal in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the game control microcomputer 100. This function makes it impossible to read internal data from an external device by masking the output. As shown in FIG. 8A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 8A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The function setting KFCS stored in the program management area indicates the operation setting of the watch dog timer (WDT) in the game control microcomputer 100 and the use setting of various function shared terminals. FIG. 8B shows an example of setting contents in the function setting KFCS.

  The bit number [7-5] of the function setting KFCS indicates, for example, the operation permission / prohibition of the watchdog timer that can be set as an interrupt factor in the reset / interrupt controller 504, and the cycle when it is permitted. The bit number [4] of the function setting KFCS indicates whether the predetermined function shared terminal (first shared terminal) in the game control microcomputer 100 is the second channel transmission terminal TXB used by the serial communication circuit 511 or the address decoding This is a TXB terminal setting that designates whether the circuit 512 uses the chip select output terminal XCS13. In the example shown in FIG. 8B, if the bit value in the bit number [4] of the function setting KFCS is “0”, the first shared terminal is used for the second channel transmission in the serial communication circuit 511. This is the setting for the 2-channel transmission terminal TXB. On the other hand, if the bit value is “1”, the first dual-purpose terminal is set to the chip select output terminal XCS13 used in the address decode circuit 512. In this embodiment, by setting the bit number [4] of the function setting KFCS to “0” and setting the first shared terminal to the second channel transmission terminal TXB, serial communication with the effect control board 12 is performed. to enable.

  The bit number [3] of the function setting KFCS indicates whether the predetermined function shared terminal (second shared terminal) in the game control microcomputer 100 is the first channel transmission terminal TXA used by the serial communication circuit 511 or the address decoding This is a TXA terminal setting that indicates whether the circuit 512 uses the chip select output terminal XCS12. In the example shown in FIG. 8B, if the bit value in the bit number [3] of the function setting KFCS is “0”, the second shared terminal is used for the first channel transmission in the serial communication circuit 511. 1 channel transmission terminal TXA is set. On the other hand, if the bit value is “1”, the second dual-purpose terminal is set to the chip select output terminal XCS12 used in the address decode circuit 512. In this embodiment, by setting the bit number [3] of the function setting KFCS to “0” and setting the second shared terminal to the first channel transmission terminal TXA, serial communication with the payout control board 15 is performed. to enable.

  The bit number [2] of the function setting KFCS indicates that the predetermined function shared terminal (third shared terminal) in the game control microcomputer 100 is the first channel reception terminal RXA used by the serial communication circuit 511, or the PIP 510 This is an RXA terminal setting indicating whether to use the input port P5. In the example shown in FIG. 8B, if the bit value in the bit number [2] of the function setting KFCS is “0”, the third shared terminal is used for the first channel reception in the serial communication circuit 511. 1 channel receiving terminal RXA is set. On the other hand, if the bit value is “1”, the third shared terminal is set to the input port P5 used in the PIP 510. In this embodiment, by setting the bit number [2] of the function setting KFCS to “0” and setting the third shared terminal to the first channel receiving terminal RXA, serial communication with the payout control board 15 is performed. to enable.

  The bit number [1] of the function setting KFCS is used by the PIP 510 as the external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like as a predetermined function shared terminal (fourth shared terminal) in the game control microcomputer 100 This is an NMI connection setting indicating whether to set the input port P4. In the example shown in FIG. 8B, if the bit value [1] in the bit number [1] of the function setting KFCS is “0”, the external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like is set as the fourth shared terminal. (CPU connection). On the other hand, if the bit value is “1”, the fourth shared terminal is set for the input port P4 used in the PIP 510 (CPU disconnected).

  The bit number [0] of the function setting KFCS is a predetermined function shared terminal (fifth shared terminal) in the game control microcomputer 100 is used as an external maskable interrupt terminal XINT connected to the CPU 505 or the like, or is used by the PIP 510 The XINT connection setting indicates whether the input port is P3. In the example shown in FIG. 8B, if the bit value in the bit number [0] of the function setting KFCS is “0”, the external maskable interrupt terminal XINT connected to the CPU 505 or the like is set to the fifth shared terminal. (CPU connection). On the other hand, if the bit value is “1”, the fifth shared terminal is set for the input port P3 used in the PIP 510 (CPU disconnected).

  The first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area indicate the initial setting of the random number circuit 509. FIG. 9A shows an example of the setting contents in the first random number initial setting KRS1. FIG. 9B shows an example of setting contents in the second random number initial setting KRS2.

  The bit number [3] of the first random number initial setting KRS1 is a random number circuit use setting indicating whether to use the random number circuit 509 or not. In the example shown in FIG. 9A, if the bit value in the bit number [3] of the first random number initial setting KRS1 is “0”, the random number circuit 509 is not used (unused), but “1”. "Is set to use the random number circuit 509 (use). In this embodiment, the bit number [3] of the first random number initial setting KRS1 is set to “1”, and the random number circuit 509 is set to be usable.

  The bit number [2] of the first random number initial setting KRS1 uses the random number update clock RGK (see FIG. 13) used for updating the numerical data that becomes the random number value in the random number circuit 509 as the internal system clock SCLK or for the random number. This is a random number update clock setting indicating whether the clock RCLK is divided by two. In the example shown in FIG. 9A, if the bit value in the bit number [2] of the first random number initial setting KRS1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. If it is 1 ″, the random number clock RCLK is divided by two and used as the random number update clock RGK. In this embodiment, the bit number [2] of the first random number initial setting KRS1 is set to “1”, and the random number clock RCLK is divided by two to be used as the random number update clock RGK.

  The bit number [1-0] of the first random number initial setting KRS1 is a random number update rule setting indicating whether or not to change the random number update rule in the random number circuit 509 and the change method in the case of the change. In the example shown in FIG. 9A, if the bit value in the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number update rule is not changed, and if it is “01”. The setting for changing the random number update rule by software is made after the second round, and if it is “10”, the random number update rule is automatically changed after the second round.

  The bit number [3-2] of the second random number initial setting KRS2 is set to a fixed bit value “00”. Note that “B” of “00B” in FIG. 9B indicates binary display. The bit number [1-0] of the second random number initial setting KRS2 indicates the setting relating to the start value in the numerical data that becomes the random value in the random number circuit 509. In the example shown in FIG. 9B, if the bit value in the bit number [1] of the second random number initial setting KRS2 is “0”, the start value is set to a predetermined default value 0001H, while “1”. In this case, a value based on the ID number, which is unique identification information assigned to each game control microcomputer 100, is set as the start value. In the example shown in FIG. 9B, if the bit value in the bit number [0] of the second random number initial setting KRS2 is “0”, the start value is not changed every time the system is reset. When it is 1 ″, the start value is changed every time the system is reset. In addition, when setting the start value to a value based on the ID number, a part or all of the calculation for performing a predetermined scramble process on the ID number and the calculation such as addition / subtraction / multiplication / division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value. Further, when the start value is changed at every system reset, for example, the count value of the free run counter built in the game control microcomputer 100 is used as a predetermined built-in that the game control microcomputer 100 has when the system reset occurs. Store in the register (random number start value register). Then, by using the stored value of the random number start value register as it is at the time of initial setting, or by using a value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the start value is It may be determined at random. The free-run counter only needs to be backed up using a backup power source common to the backup location on the main board 11, such as a backup area in the RAM 507 of the game control microcomputer 100. Alternatively, the free-run counter may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 507 or the like. In this way, the free-run counter is backed up by the backup power supply, so that the count value in the free-run counter is stored for a predetermined period even when the power supply is stopped.

  Note that when two systems (corresponding to the first and second channels) for generating numerical data to be a random number value in the random number circuit 509 are provided, the first shown in FIGS. 9A and 9B. The bit number [3-0] of the random number initial setting KRS1 and the bit number [3-0] of the second random number initial setting KRS2 are used to indicate the initial setting in the first channel. On the other hand, the bit number [7-4] of the first random number initial setting KRS1 and the bit number [7-4] of the second random number initial setting KRS2 (omitted in FIGS. 9A and 9B), the second It may be used as an indication of the initial setting in the channel.

  Interrupt initial settings KIIS stored in the program management area indicate initial settings related to handling of maskable interrupts generated in the game control microcomputer 100. FIG. 9C shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of maskable interrupt factor priorities is set. In the example shown in FIG. 9C, if any of “00H” to “02H” and “06H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt factor from the CTC 508 is determined. A combination of priorities to be given the highest priority is set. On the other hand, if any one of “03H” and “07H” is designated, a combination of priorities with the highest priority given to the maskable interrupt factor from the random number circuit 509 is set. If either “04H” or “05H” is specified, a combination of priorities that sets the maskable interrupt factor from the serial communication circuit 511 as the highest priority is set. Note that even if the priority combination has the highest priority for maskable interrupt factors from the same circuit, if the specified value is different, the type of maskable interrupt factor that has the highest priority, the priority combination in the second or lower order, etc. will differ. ing.

  The security time setting KSES stored in the program management area is the frequency at which an abnormality is detected when the frequency of the random number clock RCLK is monitored, the time of the security mode that is shifted to when the operation of the game control microcomputer 100 starts ( Indicates settings related to (security time). Here, when the operation mode of the game control microcomputer 100 is the security mode, a predetermined security check process is executed to check whether or not the content stored in the ROM 506 has been changed. FIG. 10A shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES is a random number clock abnormality detection setting indicating a frequency at which an abnormality is detected when the frequency of random number clock RCLK is monitored. FIG. 10B shows an example of setting contents in the bit number [7-6] of the security time setting KSES. The bit number [7-6] of the security time setting KSES specifies a reference value (determination value) at which the frequency of the random number clock RCLK is detected as abnormal based on the frequency of the internal system clock SCLK. The bit number “5” of the security time setting KSES is set to a fixed bit value “0”.

  The bit number [4-3] of the security time setting KSES indicates a time setting when the security time is extended by a random time every system reset. FIG. 10C shows an example of setting contents in the bit number [4-3] of the security time setting KSES. In the example shown in FIG. 10C, if the bit value in the bit number [4-3] of the security time setting KSES is “00”, the setting is not performed at random time extension. On the other hand, if the bit value is “01”, the short mode is set. If the bit value is “10”, the long mode is set. Here, when the short mode or the long mode is designated, for example, the count value of the free-run counter incorporated in the game control microcomputer 100 is set to a predetermined value provided in the game control microcomputer 100 when a system reset occurs. Store in the built-in register (variable security time register). Then, the security time can be reduced by using the stored value of the variable security time register as it is at the time of initial setting, or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). What is necessary is just to determine the extension time at the time of extending at random. As an example, when the frequency of the internal system clock SCLK is 6.0 MHz, the extension time is randomly determined in the range of 0 to 680 μs (microseconds) in the short mode, and in the range of 0 to 348, 160 μs in the long mode. The extension time is determined at random. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 408 μs in the short mode, and in the range of 0 to 208,896 μs in the long mode. The extension time is determined at random. The free-run counter used for randomly determining the extension time for extending the security time for each system reset randomly determines the start value of the random number generated by the random number circuit 509 for each system reset. Therefore, the counter may be the same as the free-run counter used for the purpose, or may be a counter provided separately.

  Bit number [2-0] of security time setting KSES indicates time setting when the security time is set to one of a plurality of pre-selectable extended times in addition to the fixed time. FIG. 10D shows an example of setting contents in the bit number [2-0] of the security time setting KSES. In the example shown in FIG. 10D, if the bit value in the bit number [2-0] of the security time setting KSES is “000”, there is no extension time added to the fixed time, and no setting is made. On the other hand, if the bit value is a value other than “000”, it is set to one of a plurality of extension times determined using the cycle TSCLK of the internal system clock SCLK. In this case, a different extension time is set according to the designated bit value. As an example, if the bit value [2-0] of the security time setting KSES is “001” when the frequency of the internal system clock SCLK is 6.0 MHz, about 699.1 ms in addition to the fixed time. An extension time of (milliseconds) is set. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz and the bit value in the bit number [2-0] of the security time setting KSES is “001”, in addition to the fixed time An extension time of about 419.4 ms is set.

  Further, the short mode or the long mode is set by the bit value [4-3] of the security time setting KSES, and the bit value in the bit number [2-0] of the security time setting KSES is set to other than “000”. Thus, it is possible to set an extension time to be added to the fixed time. In this case, both the extension time corresponding to the bit value in the bit number [2-0] and the extension time randomly determined based on the bit value in the bit number [4-3] are fixed times. By adding, the security time during which the game control microcomputer 100 is in the security mode is determined.

  The external bus interface 501 provided in the game control microcomputer 100 shown in FIG. 5 is an interface function between an external bus and an internal bus of the chip constituting the game control microcomputer 100, an address bus, a data bus, and each control signal. A bus interface having a direction control function and the like. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to the internal data of the game control microcomputer 100 from an external device via the external bus interface 501 so that the internal resource access control circuit 501A, for example, a game control program or fixed data stored in the ROM 506 This is a circuit for limiting improper external reading of data. Here, a circuit analysis device such as an in-circuit emulator (ICE; InCircuit Emulator) may be connected to the external bus interface 501 as an external device.

  As an example, according to the contents of the header KHDR stored in the program management area of the ROM 506, it is possible to switch between prohibiting or permitting reading of stored data in the ROM 506. For example, when the header KHDR is bus output mask invalid data, the ROM 506 can be read by an external device, and external reading of internal data is permitted. On the other hand, if the header KHDR is the bus output mask valid data, the ROM 506 can be read from the external device by masking the address bus output, data bus output and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that internal data cannot be read from the external device. . Further, when the header KHDR is ROM read prohibition data, the ROM 506 itself may not be read, and reading of stored data in the ROM 506 may be prevented. For example, in the ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, the bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, if the ROM for mass production is used, the bus output mask valid data is written in the header KHDR, so that the ROM 506 can be read by the CPU 505 and the like inside the game control microcomputer 100, while the external device It is only necessary to prevent the ROM 506 from being read.

  As another example, the internal resource access control circuit 501A is requested by an external device connected to the external bus interface 501 to read out internal data of the game control microcomputer 100 such as all or part of data stored in the ROM 506. Detect that. When this read request is detected, the internal resource access control circuit 501A determines whether or not reading of the internal data of the game control microcomputer 100 is permitted. For example, it is assumed that all or part of the stored data in the ROM 506 has been encrypted. In this case, if the read request from the external device is a read request for the encryption processing program or key data stored in the ROM 506, the internal resource access control circuit 501A rejects the read request, and the game control micro Reading of the internal data of the computer 100 is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 506 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be turned off. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 506). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from an external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 506. When an authentication code is input from the external device, the authentication code is compared with the authentication code stored in the internal device. If they match, a read request is accepted and the internal data of the game control microcomputer 100 is read. To give permission. On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and reading of the internal data of the game control microcomputer 100 is prohibited. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. Thereby, it is possible to read out the internal data of the game control microcomputer 100 using a correct authentication code known in advance by an inspection organization or the like, and to properly inspect the validity of the internal data. become.

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 506 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the reading prohibition flag is in the off state, reading of the ROM 506 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. That's fine. That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A does not have a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read internal data of the game control microcomputer 100 such as data stored in the ROM 506. At this time, if the reading prohibition flag is on, the reading request from the external device is rejected, and reading of the internal data of the gaming control microcomputer 100 is prohibited. On the other hand, if the read prohibition flag is OFF, a read request from an external device is accepted and reading of the internal data of the game control microcomputer 100 is permitted. With such a configuration, a provider who creates a game control program and stores it in the ROM 506 reads the program that has been debugged from the ROM 506 into an external device while the read prohibition flag is off. Can do. Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 506 can be restricted thereafter, and by the user of the pachinko gaming machine 1 or the like Reading of the ROM 506 can be prevented. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  Note that the read prohibition flag is not set irreversibly but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, external reading of the ROM 506 may be restricted by erasing the data stored in the ROM 506 (for example, flash erasure).

  The clock circuit 502 included in the game control microcomputer 100 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In this embodiment, the control clock CCLK generated by the control clock generation circuit 111 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 505 that control the progress of the game in the game control microcomputer 100. The internal system clock SCLK is also supplied to the random number circuit 509 and used to monitor the frequency of the random number clock RCLK supplied from the random number clock generation circuit 112. Furthermore, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the game control microcomputer 100. It is desirable that the internal system clock SCLK is not output to the outside of the game control microcomputer 100. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 505) of the game control microcomputer 100 from the outside, and numerical data that becomes a random value Can be prevented from being specified from the outside when the software is updated by software.

  The unique information storage circuit 503 included in the game control microcomputer 100 is a circuit that stores a plurality of types of unique information that is internal information of the game control microcomputer 100, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 506 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 506, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the game control microcomputer 100 is manufactured, and represents a different numerical value for each chip constituting the game control microcomputer 100. The ID number is an 8-byte number assigned when the game control microcomputer 100 is manufactured, and indicates a different numerical value for each chip constituting the game control microcomputer 100. Here, the chip individual number may be read from the user program, while the ID number may be set so as not to be read from the user program. The unique information storage circuit 503 may be included in the ROM 506 by using a predetermined area of the ROM 506, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 505 by using a built-in register of the CPU 505, for example.

  The reset / interrupt controller 504 provided in the game control microcomputer 100 is for controlling various reset and interrupt requests generated inside or outside the game control microcomputer 100. Resets controlled by the reset / interrupt controller 504 include system resets and user resets. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 504 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even in the interrupt disabled state of the CPU 505, and is an interrupt that is generated when a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port P4) for a certain period. is there. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 505, and multiple interrupts can be executed by setting priority. The cause of the maskable interrupt INT is that a low level signal is input to the external maskable interrupt terminal XINT (also used as the input port P3) for a certain period of time, a time-out has occurred in the timer circuit included in the CTC 508, A plurality of types of interrupt factors are determined in advance, such as the occurrence of an interrupt factor due to data reception or data transmission in the serial communication circuit 511 and the occurrence of an interrupt factor due to fetching of numerical data as a random value in the random number circuit 509. It only has to be done.

  The reset / interrupt controller 504 includes an interrupt mask register IMR (address 2028H), an interrupt wait monitor register IRR (address 2029H), among interrupted registers included in the game control microcomputer 100 as shown in FIG. The monitor register ISR (address 202AH), the internal information register CIF (address 208CH), etc. are used to control interrupts and manage resets. The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The in-interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The internal information register CIF is a register for managing the reset factor generated immediately before and recording the frequency abnormality of the random number clock RCLK.

  FIG. 11A shows a configuration example of the internal information register CIF. FIG. 11B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data CIF4 stored in the bit number [4] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCLK. In the example shown in FIG. 11B, when the frequency abnormality of the random number clock RCLK is not detected, the bit value of the internal information data CIF4 is “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 11B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”. As a first example of the operation using the internal information data CIF2, the CPU 505 of the game control microcomputer 100 checks the bit value of the internal information data CIF2 when the power is turned on, and the bit value is “1” (set). If not, it is determined that the power is not turned on normally. At this time, for example, by transmitting a predetermined effect control command to the effect control board 12, an illegal signal input action is performed aiming at a big hit gaming state immediately after the power is turned on in the pachinko gaming machine 1. You may notify that there exists possibility with a production | presentation apparatus etc. Further, as a second example of the operation using the internal information data CIF2, when the pachinko gaming machine 1 notifies the probability variation state only when the power is turned on and does not inform the probability variation state normally, the game control microcomputer 100 when the power is turned on. The CPU 505 or the like may check the bit value of the internal information data CIF2, and if the bit value is not “1” (set), the gaming state may not be notified.

  The internal information data CIF1 stored in the bit number [1] of the internal information register CIF is a WDT timeout instruction indicating whether or not the reset factor generated immediately before is a user reset due to a watchdog timer (WDT) timeout. . In the example shown in FIG. 11B, when the immediately preceding reset factor is not a user reset due to a watchdog timer timeout (timeout has not occurred), the bit value of the internal information data CIF1 becomes “0”, while the watchdog When a user reset is caused by a timer timeout (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  The CPU 505 provided in the game control microcomputer 100 executes a program read from the ROM 506, thereby executing a process for controlling the progress of the game in the pachinko gaming machine 1. At this time, the CPU 505 reads out fixed data from the ROM 506, the CPU 505 writes various data to the RAM 507 and temporarily stores the data, and the CPU 505 stores various data temporarily stored in the RAM 507. The CPU 505 receives the input of various signals from the outside of the game control microcomputer 100 via the external bus interface 501, PIP 510, serial communication circuit 511, etc., the CPU 505 receives the external bus interface 501 A transmission operation for outputting various signals to the outside of the game control microcomputer 100 via the communication circuit 511 or the like is also performed.

  As described above, in the game control microcomputer 100, the CPU 505 executes control according to the program stored in the ROM 506. Therefore, the game control microcomputer 100 (or CPU 505) is hereinafter referred to as executing (or performing processing). Specifically, the CPU 505 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 11.

  A ROM 506 provided in the game control microcomputer 100 stores a user program for game control, fixed data, and the like. The ROM 506 stores a security check program 506A. The CPU 505 reads the security check program 506A stored in the ROM 506 when the game control microcomputer 100 shifts to the security mode in response to the power-on of the pachinko gaming machine 1 or the occurrence of a system reset. A security check process is executed to check whether or not the change has been made. Note that the security check program 506A may be stored in a built-in memory different from the ROM 506. Further, the security check program 506A may correspond to a security check process for inspecting the storage content of an external memory externally attached to the game control microcomputer 100 via the external bus interface 501, for example.

  A RAM 507 provided in the game control microcomputer 100 provides a work area for game control. Here, at least a part of the RAM 507 may be a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 507 is stored for a predetermined period.

  The CTC 508 provided in the game control microcomputer 100 is configured, for example, by incorporating three channels (PTC0-PTC2) of 8-bit programmable timers, and includes a timer circuit that enables real-time interrupt generation and time measurement. Each programmable timer PTC0-PTC2 has a timer value that is updated in response to a change in the count clock signal generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is. The CTC 508 may incorporate, for example, an 8-bit programmable counter with 4 channels (PCC0 to PCC3). Each of the programmable counters PCC0 to PCC3 only needs to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3. The CTC 508 resets the start time of the random number generated by the free run counter used for randomly determining the extension time (variable setting time) for extending the security time for each system reset or the random number circuit 509. A free-run counter or the like used for determining each item at random may be included. Alternatively, these free-run counters may be included in an internal circuit of the game control microcomputer 100 different from the CTC 508, such as a backup area of the RAM 507, for example.

  The random number circuit 509 provided in the game control microcomputer 100 is a circuit that generates numerical data that is a random value having a predetermined update range, such as a 16-bit random number. In this embodiment, on the main board 11 side, for example, as shown in FIG. 12, a random value MR1 for determining a special figure display result, a random value MR2 for determining a big hit type, a random value MR3 for determining reach, a variation pattern Numeric data indicating each of the random number value MR4 for determining the type, the random value MR5 for determining the variation pattern, and the random value MR6 for determining the added value are controlled to be countable. Based on the numerical data extracted from the random number circuit 509, the CPU 505 uses a random counter different from the random number circuit 509 such as a random counter provided in the game control counter setting unit 594 shown in FIG. Numerical data representing all or part of the random number values MR1 to MR6 may be counted by processing or updating the data. In the following, as an example, the numerical data indicating the random value MR1 for determining the special figure display result and the numerical data indicating the random value MR6 for determining the added value are extracted by the CPU 505 from the random number circuit 509 serving as hardware. It is assumed that the numerical data that is updated by processing the numerical data by software, and that indicates the other random number values MR2 to MR5, is updated by software by the CPU 505 using a random counter or the like.

  Among random number values MR1 to MR6 shown in FIG. 12, for random number values MR3 to MR5, an addition value, an addition determination value, and a maximum determination value are determined. The added value is a value to be added to each random number value in response to one timer interruption or the like, and the value can be changed every time a random number update process for updating the random number value is executed. For example, the addition value is obtained on the basis of the random value MR6 for determining the addition value, and an area for storing the addition value as a temporary variable may be provided in the RAM 507 or the like. The addition determination value is a value used for obtaining an addition value corresponding to each random value by comparison with the random value MR6 for determining the addition value. More specifically, after the random value MR6 for determining the added value is read as the initial value of the added value corresponding to each random value, it is determined that the current added value is smaller than the added determination value. The value obtained by subtracting the addition determination value from the current addition value is updated as a new addition value. The random number determination value is a value used to determine whether each updated random number value obtained by adding the finally obtained addition value is within a range of possible values. When each updated random number value exceeds the corresponding random number determination value, a value obtained by subtracting the random number determination value from the updated random number value is set as a new random number value. In this embodiment, it is assumed that the numerical data indicating the random value MR2 is updated to be incremented by one each time a timer interrupt occurs in the game control microcomputer 100.

  The random number MR1 for determining the special figure display result indicates whether or not the variable display result of the special symbol or the like in the special figure game is controlled as a big hit game state, and whether the variable display result is the “small hit” or not. It is a random value used to determine whether or not to control the gaming state. For example, the random number MR1 for determining the special figure display result takes a value in the range of “0” to “65535”. The random value MR2 for determining the big hit type is a random value used for determining the big hit type as one of a plurality of types when the variable display result is “big hit”. For example, the random value MR2 for determining the big hit type takes a value in the range of “0” to “99”.

  The random number MR3 for reach determination is used to determine whether or not to use the “reach” variable display mode in which the decorative symbol is derived and displayed in the reach display state when the variable display result is “lost”. It is a random value. For example, the random number MR3 for reach determination takes a value in the range of “0” to “239”. Corresponding to the reach determination random value MR3, the range of the addition value is set to “0” to “7”, the addition determination value is “8”, and the maximum determination value is “240”.

  The random number value MR4 for determining the variation pattern type is a random value used for determining the variation pattern type of the decorative design as one of a plurality of types prepared in advance. For example, the random value MR4 for determining the variation pattern type takes a value in the range of “0” to “241”. Here, each variation pattern type may be configured to include one or a plurality of variation patterns classified based on, for example, a rendering operation executed during variable display of decorative symbols. Corresponding to the random value MR4 for determining the variation pattern type, the range of the addition value is set to “0” to “7”, the addition determination value is “8”, and the maximum determination value is “242”.

  The random value MR5 for determining the variation pattern is a random value used for determining the variation pattern of the decorative design as one of a plurality of types prepared in advance. For example, the random number MR5 for determining the variation pattern takes a value in the range of “0” to “255”. Corresponding to the random value MR5 for determining the variation pattern, the range of the added value is “0” to “7”, the added determination value is “8”, and the maximum determined value is “256”.

  The random value MR6 for determining the added value is a value used for obtaining an added value corresponding to each random value by comparing with an addition determination value corresponding to each random value. For example, the random value MR6 for determining the added value takes a value in the range of “0” to “7”.

  FIG. 13 is a block diagram illustrating a configuration example of the random number circuit 509. As shown in FIG. 13, the random number circuit 509 includes a frequency monitoring circuit 551, a clock flip-flop 552, a random number generation circuit 553, a start value setting circuit 554, a random number sequence change circuit 555, a random number sequence change setting circuit 556, and a latch flip-flop. 557A, 557B, random number latch selectors 558A, 558B, and random number value registers 559A, 559B. The random value register 559A and the random value register 559B are respectively a random value register R1D (address 2038H-2039H) and a random value register R2D included in the built-in registers of the game control microcomputer 100 as shown in FIG. (Addresses 203AH-203BH).

  The frequency monitoring circuit 551 is a circuit for monitoring the frequency of the random number clock RCLK generated by the random number clock generation circuit 112 and detecting the occurrence of an abnormality. For example, the frequency monitoring circuit 551 monitors an oscillation signal input to the random number external clock terminal ERC, and sets the contents of the bit number [7-6] of the security time setting KSES based on the internal system clock SCLK (FIG. 10B When the frequency abnormality according to the reference) is detected, the bit number [4] of the internal information register CIF is set to “1”. In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 112 is input to the random number external clock terminal ERC.

  The clock flip-flop 552 is configured using, for example, a D-type flip-flop, and the random number clock RCLK from the random number external clock terminal ERC is input to the clock terminal CK. Further, in the clock flip-flop 552, the negative phase output terminal (inverted output terminal) Q bar is connected to the D input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal) Q, while the latch clock RC0 is output from the negative phase output terminal (inverted output terminal) Q bar. In this case, when the signal state of the random number clock RCLK input to the clock terminal CK changes a predetermined state, the clock flip-flop 552 has a positive phase output terminal (non-inverted output terminal) Q and a negative phase output terminal ( Inverted output terminal) Changes the signal state in the output signal from the Q bar. For example, the clock flip-flop 552 rises when the signal state of the random number clock RCLK changes from a low level to a high level, or rises when the signal state of the random number clock RCLK changes from a high level to a low level. The input signal at the D input terminal is captured at any one of the falling timings. At this time, from the positive phase output terminal (non-inverted output terminal) Q, the input signal captured at the D input terminal is output without being inverted, while the negative phase output terminal (inverted output terminal) Q bar is output. From the input signal captured by the D input terminal is inverted and output. Thus, the random number update clock RGK having an oscillation frequency (for example, 10 MHz) that is ½ of the oscillation frequency (for example, 20 MHz) of the random number clock RCLK from the positive phase output terminal (non-inverted output terminal) Q of the clock flip-flop 552. Is output from the negative phase output terminal (inverted output terminal) Q bar, that is, the reverse phase signal (inverted signal) of the random number update clock RGK, that is, the same frequency as the random number update clock RGK and the phase of the random number update clock RGK is π. A different latch clock RC0 is output by (= 180 °).

  The random number update clock RGK output from the clock flip-flop 552 is input to the clock terminal of the random number generation circuit 553 and used for incrementing the count value in the random number generation circuit 553. The latch clock RC0 output from the clock flip-flop 552 is branched into the latch clock RC1 and the latch clock RC2 at the branch point BR1. Therefore, the latch clock RC1 and the latch clock RC2 have the same oscillation frequency, and the signal state changes with a common cycle. Here, examples of changes in the signal state in the latch clock RC1 and the latch clock RC2 include a rising edge that changes from a low level to a high level and a falling edge that changes from a high level to a low level. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A and becomes a random number acquisition clock used to generate the start winning latch signal SL1. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B and becomes a random number acquisition clock used to generate the start winning latch signal SL2.

  Here, the oscillation frequency of the random number clock RCLK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other, and one of the oscillation frequencies is the other. It is never an integral multiple of the oscillation frequency. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCLK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clocks RC1 and RC2 are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 505. In other words, the clock flip-flop 552 is based on the random number clock RCLK generated by the random number clock generation circuit 112, and the random number update clock RGK for updating the count value and the latch clock that is used as a plurality of random number acquisition clocks. As RC1 and RC2, oscillation signals whose signal states change with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) are generated.

  The random number generation circuit 553 is composed of, for example, a 16-bit counter and the like, and based on an input such as a random number update clock RGK output from the clock flip-flop 552, a predetermined initial value within a predetermined range in which numerical data can be updated. It is a circuit that cyclically updates to a predetermined final value. For example, the random number generation circuit 553 responds to the rising edge in the random number update clock RGK that is an input signal to a predetermined clock terminal, and “65535” from the initial value set in the range from “0” to “65535”. The numerical data is counted up so that one is added at a time. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The start value setting circuit 554 sets the start value in the count value generated by the random number generation circuit 553 in accordance with the bit value (see FIG. 9B) in the bit number [1-0] of the second random number initial setting KRS2. Set. For example, the start value setting circuit 554 sets the start value to the default value “0000H” if the bit number [1-0] of the second random number initial setting KRS2 is “00”, and if it is “10”. The value is set based on the ID number. If “01”, the value is changed every time the system is reset.

  The random number sequence change circuit 555 is a circuit that allows the permutation, which is the update order of the numerical data, to be changed to a permutation that conforms to a predetermined random number update rule when the numerical data generated by the random number generation circuit 553 makes a round. For example, the random number sequence change circuit 555 executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553. The random number sequence change circuit 555 can change the permutation, which is the update order of the numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble process, for example.

  The random number sequence change setting circuit 556 determines the update order of the numerical data in the random number sequence change circuit 555 according to the bit value (see FIG. 9A) in the bit number [1-0] of the first random number initial setting KRS1. It is a circuit for performing the setting to change. For example, if the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number sequence change setting circuit 556 sets the random number update rule not to change after the second round, while “01” If so, the random number update rule is changed in response to a change request by software after the second round, and if it is “10”, the random number update rule is automatically changed.

  When the random number update circuit 556 changes the random number update rule by software in response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, FIG. Of the built-in registers included in the gaming control microcomputer 100 as shown, the random number update rule RDSC (address 2034H) is used to control the change of the random number update rule. FIG. 14A shows a configuration example of the random number sequence change register RDSC. FIG. 14B shows an example of setting contents in each bit of the random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates the presence / absence of a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 14B, when there is no random number sequence change request by software, the bit value of the random number sequence change request data RDSC0 is “0”, while when there is a random number sequence change request, The bit value is “1”.

  FIG. 15 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553 is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. And change the random number update rule. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 505 executing the user program stored in the ROM 506.

  In response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0 and the bit value is “1”. In response to "," a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 556, according to the count value permutation RCN output from the random number generation circuit 553 reaching a predetermined final value, for example, any one of a plurality of types of random number update rules prepared in advance. The random number update rule is changed, for example, by selecting. In the operation example shown in FIG. 15, the random number sequence change circuit 555 outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence change circuit 555 outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 555 is “65535 → 65534 →... → 0”. Become.

  When the CPU 505 executes the user program stored in the ROM 506 and the bit value “1” is written again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 15, when the random number sequence change circuit 555 outputs the numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. Thereafter, the random number sequence changing circuit 555 outputs “0 → 2 →... → 65534 → 1 →... → 65535” as the random number sequence RSN according to the changed random number update rule.

  FIG. 16 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553 being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 556 automatically changes the random number update rule. To change. In the operation example shown in FIG. 16, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number change circuit 555 reaches a predetermined final value, the random number sequence change setting circuit 556 follows a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule. Alternatively, the random number sequence change setting circuit 556 may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 16, the random number sequence RSN output from the random number sequence change circuit 555 becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 555 becomes “0 → 2 →... → 65534 → 1 →. In the operation example illustrated in FIG. 16, the random number sequence RSN output from the random number sequence change circuit 555 is “65534 → 0 →... → 32768” due to the third change in the random number update rule. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “4 → 3 →... → 465553”.

  Each of the latch flip-flops 557A and 557B is configured using, for example, a D-type flip-flop. In the latch flip-flop 557A, a wiring from the input port P0 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC1 is connected to the clock terminal CK. In this embodiment, the first start winning signal SS1 from the first start port switch 22A is input to the input port P0. The latch flip-flop 557A takes in the first start winning signal SS1 (actually an inverted signal of SS1) in response to the rising edge of the latch clock RC1, and outputs it as the start winning latch signal SL1. Accordingly, in the latch flip-flop 557A, the first start winning signal SS1 is output as the start winning latch signal SL1 in synchronization with the rising edge of the latch clock RC1. In the latch flip-flop 557B, a wiring from the input port P1 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC2 is connected to the clock terminal CK. In this embodiment, the second start winning signal SS2 from the second start port switch 22B is input to the input port P1. In response to the rising edge of the latch clock RC2, the latch flip-flop 557B takes in the second start winning signal SS2 (actually an inverted signal of SS2) and outputs it as the start winning latch signal SL2. Thus, in the latch flip-flop 557B, the second start winning signal SS2 is output as the start winning latch signal SL2 in synchronization with the rising edge of the latch clock RC2.

  The first start winning signal SS1 and the second start winning signal SS2 are not limited to those directly transmitted from the first start port switch 22A and the second start port switch 22B. As an example, the time during which the output signal from the first start port switch 22A and the output signal from the second start port switch 22B are in the ON state is measured, and the measured time becomes a predetermined time (for example, 3 ms). Sometimes, a timer circuit for outputting the first start winning signal SS1 and the second starting winning signal SS2 may be provided.

  The random number latch selector 558A is a circuit that takes in the start winning latch signal SL1 transmitted from the latch flip-flop 557A and the random number latch request signal by software, and selectively outputs one as the random number latch signal LL1. The random number latch selector 558B is a circuit that takes in the start winning latch signal SL2 transmitted from the latch flip-flop 557B and the random number latch request signal by software, and selectively outputs one as the random number latch signal LL1. The random number latch selector 558A and the random number latch selector 558B are a random value fetch register RDLT (address 2032H) and a random number latch selection register RDLS among the built-in registers included in the game control microcomputer 100 as shown in FIG. (Address 2030H) is used to control the output of the random number latch signal LL1 and the random number latch signal LL2. The random value acquisition register RDLT is a register used for acquiring numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random value register 559A or the random value register 559B by software. The random number latch selection register RDLS receives the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random number value register 559A or the random number value register 559B by software, or by signal input to the input ports P0 and P1. It is a register indicating a fetching method of fetching.

  FIG. 17A shows a configuration example of the random value fetch register RDLT. FIG. 17B shows an example of the setting contents in each bit of the random value take-in designation data stored in the random value take-in register RDLT. The random value acquisition specification data RDLT1 stored in the bit number [1] of the random value acquisition register RDLT indicates whether or not random number acquisition is specified for the random value register 559B serving as the random value register R2D. In the example shown in FIG. 17B, when there is no specification of random number acquisition to the random number register R2D by software, the bit value of the random value acquisition specification data RDLT1 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included. The random value acquisition specification data RDLT0 stored in the bit number [0] of the random value acquisition register RDLT indicates whether or not a random value acquisition specification is given to the random value register 559A serving as the random value register R1D. In the example shown in FIG. 17B, when there is no specification of random number acquisition to the random value register R1D by software, the bit value of the random value acquisition specification data RDLT0 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included.

  FIG. 18A shows a configuration example of the random number latch selection register RDLS. FIG. 18B shows an example of setting contents in each bit of the random number latch selection data stored in the random number latch selection register RDLS. The random number latch selection data RDLS1 stored in the bit number [1] of the random number latch selection register RDLS indicates a method for taking in the random number value register 559B serving as the random number value register R2D. In the example shown in FIG. 18B, when the numerical value data that becomes the random number value is loaded into the random number value register R2D in response to the writing of the random number value loading designation data RDLT1 by the software, the bit value of the random number latch selection data RDLS1 is set to “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R2D in response to the signal input to the input port P1, the bit value of the random number latch selection data RDLS1 is set to “1”. The random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 18B, when the numerical data that becomes the random number value is loaded into the random value register R1D in response to the writing of the random value fetch designation data RDLT0 by software, the bit value of the random number latch selection data RDLS0 is set to “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R1D in response to the signal input to the input port P0, the bit value of the random number latch selection data RDLS0 is set to “1”.

  The random value registers 559A and 559B are registers for storing numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 as random number values. FIGS. 19A and 19B show a configuration example of a random value register 559A serving as the random value register R1D. FIG. 19A shows the lower byte R1D (L) of the random value register R1D, and FIG. 19B shows the upper byte R1D (H) of the random value register R1D. FIGS. 19C and 19D show a configuration example of a random value register 559B serving as the random value register R2D. FIG. 19C shows the lower byte R2D (L) of the random value register R2D, and FIG. 19D shows the upper byte R2D (H) of the random value register R2D. Each of the random value registers 559A and 559B is a 16-bit (2-byte) register and can store a 16-bit random value.

  The random value register 559A takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL1 supplied from the random number latch selector 558A being turned on. Store with. When the register read signal RRS1 supplied from the CPU 505 is turned on, the random value register 559A is in a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS1 is in the off state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559A may be in a state in which the register read signal RRS1 cannot be received when the random number latch signal LL1 is in the ON state. Further, the random number register 559A may be configured to be in a state in which the random number latch signal LL1 cannot be received when the register read signal RRS1 is in the on state before the random number latch signal LL1 is in the on state. Good.

  The random value register 559B takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL2 supplied from the random number latch selector 558B being turned on. Store with. When the register read signal RRS2 supplied from the CPU 505 is turned on, the random value register 559B enters a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS2 is in the OFF state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559B may be in a state in which the register read signal RRS2 cannot be received when the random number latch signal LL2 is in the ON state. Further, the random value register 559B may be configured to be in a state in which the random number latch signal LL2 cannot be received when the register read signal RRS2 is in the on state before the random number latch signal LL2 is in the on state. Good.

  The random value register 559A and the random value register 559B are a random number latch flag register RDFM (address 2033H) and a random number interrupt control register RDIC (of the built-in registers included in the game control microcomputer 100 as shown in FIG. 7B). Address 2031H) and enable operation management and interrupt control at the time of random number latching. The random number latch flag register RDFM is a register for storing a random number latch flag indicating whether or not numerical data to be a random number value is latched corresponding to each of the random number value register 559A and the random number value register 559B. The random number interrupt control register RDIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random value is latched in the random value register 559A or the random value register 559B.

  FIG. 20A shows a configuration example of the random number latch flag register RDFM. FIG. 20B shows an example of setting contents in each bit of random number latch flag data stored in the random number latch flag register RDFM. The random number latch flag data RDFM1 stored in the bit number [1] of the random number latch flag register RDFM becomes a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559B serving as the random number value register R2D. In the example shown in FIG. 20B, when the numerical value data is not taken into the random value register R2D (no random value is taken), the bit value of the random number latch flag data RDFM1 becomes “0”, while the numerical data Is taken (with random number fetching), the bit value becomes “1”. The random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM becomes a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 20B, when the numerical data is not captured in the random value register R1D (no random value is captured), the bit value of the random number latch flag data RDFM0 is “0”, while the numerical data Is taken (with random number fetching), the bit value becomes “1”.

  FIG. 21A shows a configuration example of the random number interrupt control register RDIC. FIG. 21B shows an example of setting contents in each bit of random number interrupt control data stored in the random number interrupt control register RDIC. The random number interrupt control data RDIC1 stored in the bit number [1] of the random number interrupt control register RDIC permits or prohibits an interrupt that occurs when numerical data is taken into the random number value register 559B serving as the random number value register R2D. Indicates the interrupt control setting for In the example shown in FIG. 21 (B), when interrupting at the time of fetching into the random value register R2D is prohibited (interrupt disabled), the bit value of the random number interrupt control data RDIC1 is set to “0”, while this interrupt is When enabling (interrupt enabled), the bit value is set to “1”. The random number interrupt control data RDIC0 stored in the bit number [0] of the random number interrupt control register RDIC allows or prohibits an interrupt that occurs when numerical data is taken into the random number value register 559A serving as the random number value register R1D. Indicates the interrupt control setting for In the example shown in FIG. 21 (B), when the interrupt at the time of fetching into the random value register R1D is prohibited (interrupt disabled), the bit value of the random number interrupt control data RDIC0 is set to “0”, while this interrupt is When enabling (interrupt enabled), the bit value is set to “1”.

  The PIP 510 included in the game control microcomputer 100 is, for example, a 6-bit input dedicated port, and includes an input port P0 to an input port P2 serving as a dedicated terminal, and an input port P3 to an input port P5 serving as a function shared terminal. It is out. The input port P3 is also used as an external maskable interrupt terminal XINT connected to the CPU 505 or the like. The input port P4 is also used as an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. The input port P5 is also used as the first channel reception terminal RXA used by the serial communication circuit 511. The use setting of the input port P3 to the input port P5 is instructed by the function setting KFCS stored in the program management area.

  The PIP 510 uses the input port register PI (address 2090H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. 7B to manage the status of the input port P0 to the input port P5. Do. The input port register PI is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input port P0 to the input port P5.

  FIG. 22A shows a configuration example of the input port register PI. FIG. 22B shows an example of setting contents in each bit of the input port data stored in the input port register PI. The input port data PI5 stored in the bit number [5] of the input port register PI indicates the terminal state (ON / OFF) at the input port P5 that is also used as the first channel receiving terminal RXA. The input port data PI4 stored in the bit number [4] of the input port register PI indicates the terminal state (ON / OFF) at the input port P4 that is also used as the external non-maskable interrupt terminal XNMI. The input port data PI3 stored in the bit number [3] of the input port register PI indicates the terminal state (ON / OFF) at the input port P3 that is also used as the external maskable interrupt terminal XINT. The input port data PI2 stored in the bit number [2] of the input port register PI indicates the terminal state (ON / OFF) at the input port P2. The input port data PI1 stored in the bit number [1] of the input port register PI indicates the terminal state (ON / OFF) at the input port P1. The input port data PI0 stored in the bit number [0] of the input port register PI indicates the terminal state (ON / OFF) at the input port P0.

  An address decoding circuit 512 provided in the game control microcomputer 100 shown in FIG. 5 is for decoding each functional block in the game control microcomputer 100 and a chip select signal that is a decode signal for an external device. Circuit. By the chip select signal, an internal circuit of the game control microcomputer 100 or an external device as a peripheral device is selectively operated effectively and can be accessed from the CPU 505.

  The ROM 506 provided in the game control microcomputer 100 stores various selection data and table data used for controlling the progress of the game, in addition to the game control user program and the security check program 506A. . For example, the ROM 506 stores data constituting a plurality of determination tables, determination tables, setting tables, and the like prepared for the CPU 505 to perform various determinations, determinations, and settings. The ROM 506 also has a variation pattern in which the CPU 505 stores a plurality of types of table data constituting a plurality of command tables used for transmitting control signals serving as various control commands from the main board 11 and a plurality of types of decorative pattern variation patterns. Table data constituting the table is stored.

  FIG. 23 shows a configuration example of the special figure display result determination table stored in the ROM 506. In this embodiment, as the special figure display result determination table, a first special figure display result determination table 130A shown in FIG. 23A and a second special figure display result determination table 130B shown in FIG. Are prepared in advance. The first special figure display result determination table 130A has a variable display result before a fixed special symbol that is a variable display result is derived and displayed in the special figure game using the first special figure by the first special symbol display device 4A. Whether or not to control the big hit gaming state as “big hit” and whether to control the small display game status as “small hit” based on the random number value MR1 for determining the special figure display result It is a table referred to for determination. The second special figure display result determination table 130B shows the variable display result before the fixed special symbol that becomes the variable display result is derived and displayed in the special figure game using the second special figure by the second special symbol display device 4B. Whether or not to control the big hit gaming state as “big hit” and whether to control the small display game status as “small hit” based on the random number value MR1 for determining the special figure display result It is a table referred to for determination.

  In the first special figure display result determination table 130A, the random value MR1 for determining the special figure display result is determined depending on whether the probability variation flag provided in the game control flag setting unit 592 shown in FIG. 25 is OFF or ON. Are allocated so as to be associated with the big hit determination value data, the small hit determination value data, and the loss determination value data. In the second special figure display result determination table 130B, the random value MR1 for special figure display result determination is associated with the big hit determination value data or the loss determination value data depending on whether the probability variation flag is OFF or ON. Is allocated as In the first special figure display result determination table 130A and the second special symbol display result determination table 130B, the table data indicating the random value MR1 for determining the special figure display result is allocated to the determination result as to whether or not to control the big hit gaming state. This is the judgment data. In each of the first special figure display result determination table 130A and the second special figure display result determination table 130B, when the probability variation flag is on, a larger number of random values MR1 than when the probability variation flag is off, Allocated to jackpot decision data. Here, when the gaming state in the pachinko gaming machine 1 is the probability variation state, the probability variation flag is turned on. On the other hand, when the gaming state in the pachinko gaming machine 1 is a normal state or a short time state, the probability variation flag is turned off. Thereby, when the gaming state in the pachinko gaming machine 1 is in a probable variation state, the probability that it will be determined that the variable display result is “big hit” and control is made to the big hit gaming state is higher than in the normal state or the short time state. . That is, in each of the first special figure display result determination table 130A and the second special figure display result determination table 130B, when the gaming state in the pachinko gaming machine 1 is in a probabilistic state, compared to when it is in a normal state or a short time state. Therefore, the determination data is allocated to the determination result as to whether or not to control the jackpot gaming state so that the probability of determining to control the jackpot gaming state increases.

  In the setting example of the first special figure display result determination table 130A shown in FIG. 23A, a predetermined range of values ("30000" to "30099") is included in the random number MR1 for determining the special figure display result. It is assigned so as to be associated with the small hit judgment value data. On the other hand, in the setting example of the second special figure display result determination table 130B shown in FIG. 23B, the random value MR1 for determining the special figure display result is not associated with the small hit determination value data. Allocated. With such a setting, the variable display result is determined based on the fact that the first start condition for starting the special figure game using the first special figure by the first special symbol display device 4A is satisfied, When the variable display result is determined based on the fact that the second start condition for starting the special figure game using the second special figure by the second special symbol display device 4B is established, the variable display result is expressed as “ The ratio determined to be controlled in the small hit gaming state as “small hit” can be varied.

  FIG. 24 shows a configuration example of the jackpot type determination table 131 stored in the ROM 506. The jackpot type determination table 131 is used to determine the jackpot type as one of a plurality of types based on the random number MR2 for determining the jackpot type when it is determined that the variable display result is “big hit” and the game state is controlled to the big hit game state. It is a table that is referred to. In the jackpot type determination table 131, whether the value of the variation special figure designation buffer (fluctuation special figure designation buffer value) provided in the game control buffer setting unit 595 shown in FIG. 25 is “1” or “2”. Accordingly, the random number MR2 for determining the big hit type is assigned so as to be associated with a plurality of types of big hit types such as “normal”, “first probability variation” to “third probability variation”, and “surprise probability”. Here, the variable special figure designation buffer value is set to “1” when the special figure game using the first special figure is started on the first special symbol display device 4A when the first start condition is satisfied. Thus, “2” is set when the second special symbol display device 4B starts the special figure game using the second special figure when the second start condition is satisfied. Further, the jackpot type determination table 131 corresponds to the jackpot type determined based on the random number MR2 for determining the jackpot type by using the value of the jackpot type buffer provided in the game control buffer setting unit 595 (the jackpot type buffer value). Thus, table data (setting data) for setting to any one of “0” to “4” is included.

  In the setting example of the big hit type determination table 131 shown in FIG. 24, depending on whether the variation special figure designation buffer value is “1” or “2”, the big hit type determination disturbance for the “surprise” big hit type The allocation of numerical value MR2 is different. That is, when the fluctuation special figure designation buffer value is “1”, the value in the range of “82” to “99” among the random value MR2 for determining the big hit type is assigned to the big hit type of “surprise”. When the variation special figure designation buffer value is “2”, the random value MR2 for determining the big hit type is not allocated to the big hit type of “surprise”. With such a setting, the jackpot type is determined as one of a plurality of types based on the fact that the first start condition for starting the special figure game using the first special figure by the first special symbol display device 4A is satisfied. And determining the jackpot type as one of a plurality of types based on the fact that the second start condition for starting the special figure game using the second special figure by the second special symbol display device 4B is satisfied. Thus, the rate at which the jackpot type is determined to be “surprising” can be varied. Even when the fluctuation special figure designation buffer value is “2”, the random range value MR2 for determining the big hit type has a value in a predetermined range different from that when the fluctuation special figure designation buffer value is “1”. , It may be assigned to the big hit type of “Accuracy”. As an example, when the fluctuation special figure designation buffer value is “2”, the random number MR2 for determining the big hit type has a smaller number of values than when the fluctuation special figure designation buffer value is “1”. Is set to be assigned to the “big hit” big hit type, when the second start condition is satisfied, the ratio determined to be the “big hit” big hit type compared to when the first start condition is satisfied Can be reduced.

  If it is determined in the above determination that the game state is not controlled to the jackpot gaming state, it is determined whether or not the reach variable display mode is set based on the reach determination random value MR3. In the case of controlling to the jackpot gaming state, if the jackpot type is determined, the reach is always displayed in a variable display mode even if the determination based on the random value MR3 for reach determination is not performed (as a premise of jackpot Reach will appear). Further, based on the variation pattern type determination table prepared for each of these determination contents and the random value MR4 for determining the variation pattern type, the variation pattern type (if not controlled to the jackpot gaming state, non-reach loss, In the case of controlling to the normal reach and super reach, the jackpot gaming state, two types of normal reach and super reach) are determined. Furthermore, a specific variation pattern is determined based on the variation pattern table prepared for each determination content and the random value MR5 for determining the variation pattern.

  In the RAM 507 provided in the game control microcomputer 100, for example, a game control data holding area as shown in FIG. 25 is used as an area for holding various data used for controlling the progress of the game in the pachinko gaming machine 1. 590 is provided. The game control data holding area 590 shown in FIG. 25 includes a first special figure hold storage unit 591A, a second special figure hold storage unit 591B, a start data storage unit 591C, a game control flag setting unit 592, and a game control. A timer setting unit 593, a game control counter setting unit 594, and a game control buffer setting unit 595 are provided. Further, for example, a DRAM (Dynamic RAM) is used as the RAM 507, and a refresh operation is required to maintain the stored data contents. The CPU 505 has a built-in refresh register for performing this refresh operation. For example, the refresh register consists of 8 bits, and the lower 7 bits are automatically incremented each time the CPU 505 fetches an instruction from the ROM 506. Accordingly, the stored value in the refresh register is updated every execution time of one instruction in the CPU 505.

  The first special figure storage unit 591A is a special game in which a game ball wins a first starting winning opening formed by the normal winning ball apparatus 6A and the first starting condition is satisfied but the first starting condition is not satisfied. The hold data of (a special game using the first special figure by the first special symbol display device 4A) is stored. As an example, the first special figure holding storage unit 591A associates with the holding numbers in the order of winning in the first start winning opening, and the special figure display result determination acquired by the CPU 505 based on the establishment of the first starting condition by the winning. The numerical data indicating the random number value MR1 for use and the numerical data indicating the random number value MR2 for determining the big hit type are reserved data and stored until the number reaches a predetermined upper limit value (eg, “4”).

  The second special figure holding storage unit 591B is a special figure in which the game ball is won at the second start winning opening formed by the normal variable winning ball apparatus 6B and the second start condition is satisfied but the second start condition is not satisfied. Hold data of a game (a special game using the second special figure by the second special symbol display device 4B) is stored. As an example, the second special figure holding storage unit 591B associates with the holding number in the order of winning in the second start winning opening, and the special figure display result determination acquired by the CPU 505 based on the establishment of the second starting condition by the winning. The numerical data indicating the random number value MR1 for use and the numerical data indicating the random number value MR2 for determining the big hit type are reserved data and stored until the number reaches a predetermined upper limit value (eg, “4”).

  The start data storage unit 591C stores start data indicating which of the first start winning opening and the second starting winning opening the game ball has won, so that the order of winning of each game ball can be specified. As an example, an area corresponding to the upper limit value (for example, “8”) of the total reserved storage number is secured in the start data storage unit 591C, and “first” start data corresponding to winning in the first start winning opening is obtained. Alternatively, the “second” start data corresponding to the winning at the second start winning opening is stored in association with the holding number according to the winning order of each game ball.

  The game control flag setting unit 592 is provided with a plurality of types of flags that can be updated in accordance with the progress of the game in the pachinko gaming machine 1. For example, the game control flag setting unit 592 stores data indicating the flag value and data indicating the on state or the off state for each of the plurality of types of flags. In this embodiment, the game control flag setting unit 592 is provided with a special figure process flag, a common figure process flag, a big hit flag, a small hit flag, a probability change flag, a short time flag, and the like.

  The special figure process flag indicates the progress of the special figure game using the first special figure by the first special symbol display device 4A, the progress of the special figure game using the second special figure by the second special symbol display device 4B, and the like. In the step S95 of FIG. 30 executed for control and the special symbol process shown in FIG. 32, which process is to be selected and executed is instructed. The ordinary symbol process flag is selected and executed in the ordinary symbol process shown in step S96 of FIG. 30 executed to control the progress of the ordinary symbol game using the ordinary symbol by the ordinary symbol display 20. Tell what to do.

  The big hit flag is set to an on state corresponding to the determination result that the variable display result is “big hit” when the special figure game is started. On the other hand, it is cleared and turned off in response to, for example, that the jackpot symbol is stopped and displayed as a confirmed special symbol in the special symbol game. The small hit flag is set to an on state corresponding to the determination result that the variable display result is “small hit” when the special figure game is started. On the other hand, it is cleared and turned off in response to, for example, the small hit symbol being stopped and displayed as the confirmed special symbol in the special symbol game. The probability change flag is set to an on state in response to the gaming state in the pachinko gaming machine 1 being controlled to a probability change state, while being cleared to an off state in response to the end of the probability change state. . The time reduction flag is set to the on state in response to the gaming state in the pachinko gaming machine 1 being controlled to the time reduction state, and is cleared to the off state in response to the completion of the time reduction state. .

  The game control timer setting unit 593 is provided with various timers used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control timer setting unit 593 stores data indicating timer values in each of a plurality of types of timers. In this embodiment, the game control timer setting unit 593 is provided with a game control process timer, a special figure variation timer, a common figure variation timer, and the like.

  The game control process timer is for measuring, for example, the time for controlling the progress of the big hit game state or the small hit game state on the main board 11 side. As a specific example, the game control process timer stores, as a game control process timer value, data indicating a timer value corresponding to the time measured to control the progress of the big hit game state or the small hit game state. It is used as a down counter that counts down automatically.

  The special figure variation timer is for measuring, on the main board 11 side, a time for controlling the progress of the special figure game such as a special figure variation time which is the execution time of the special figure game. As a specific example, the special figure variation timer stores data indicating a timer value corresponding to the time measured in order to control the progress of the special figure game as a special figure fluctuation timer value and periodically counts down. Used as a counter.

  The universal map change timer is for measuring, on the main board 11 side, a time for controlling the progress of the normal game, such as the normal map change time which is the execution time of the normal game. As a specific example, the normal fluctuation timer stores data indicating a timer value corresponding to the time measured to control the progress of the normal figure game as a normal fluctuation timer value, and periodically counts down. Used as a counter.

  The game control counter setting unit 594 is provided with a plurality of types of counters for counting the count values used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control counter setting unit 594 stores data indicating the count value in each of a plurality of types of counters. In this embodiment, the game control counter setting unit 594 includes a random counter, a first reserved memory number counter, a second reserved memory number counter, a total reserved memory number counter, a round number counter, a first start winning determination counter, a second A start winning determination counter is provided.

  The random counter of the game control counter setting unit 594 counts a part of numerical data indicating a random value used for controlling the progress of the game separately from the random number circuit 509 so that the CPU 505 can be updated by software. belongs to. For example, the random counter of the game control counter setting unit 594 stores numerical data indicating the random number values MR1 to MR6 as random count values. As for the random number values MR2 to MR5, numerical data indicating each random number value is updated regularly or irregularly according to the execution of software by the CPU 505.

  The round number counter is for counting the number of rounds executed in the big hit gaming state. For example, in the round number counter, data indicating a count initial value “1” at the start of the big hit gaming state is set as the round number count value. When one round is completed and the next round is started, the round count value is incremented by 1 and updated. The round number counter may also count the number of executions of the variable winning operation in the small hit gaming state.

  The first start winning determination counter is a timer interrupt for game control when the first start winning signal SS1 as a detection signal transmitted from the first start opening switch 22A is in an ON state (ie, low level). It is used as an up-counter that is counted up each time when. When the first start winning determination count value that is the value of the first start winning determination counter reaches a predetermined winning determination value (for example, “2”), the game ball that has entered the first start winning opening is made effective. It is determined that it has been detected.

  The second start winning determination counter is a timer interrupt for game control when the second start winning signal SS2 as a detection signal transmitted from the second start opening switch 22B is in an ON state (ie, low level). It is used as an up-counter that is counted up each time when. When the second start winning determination count value, which is the value of the second start winning determination counter, reaches a predetermined winning determination value (for example, “2”), the game ball that has entered the second start winning opening is made effective. It is determined that it has been detected.

  The game control buffer setting unit 595 is provided with various buffers that temporarily store data used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control buffer setting unit 595 stores data indicating buffer values in each of a plurality of types of buffers. In this embodiment, the game control buffer setting unit 595 is provided with a transmission command buffer, a variable special figure designation buffer, a big hit type buffer, a start port buffer, and the like.

  The transmission command buffer is used to temporarily store setting data for transmitting a control command from the main board 11 to the sub-side control board. For example, the transmission command buffer is configured to include a plurality of (for example, “12”) buffer areas, and setting data indicating the storage address in the ROM 506 of the command table corresponding to the control command to be transmitted is stored in each buffer area. The In addition, a buffer area in which setting data is written and read in the transmission command buffer may be specified by a transmission command pointer or the like, and may be configured so that a plurality of buffer areas can be used as a ring buffer.

  The variable special symbol designation buffer includes a special symbol game using the first special symbol by the first special symbol display device 4A and a special symbol game using the second special symbol by the second special symbol display device 4B. A buffer value indicating whether the special figure game is executed is stored. As an example, the value of the fluctuation special figure designation buffer (fluctuation special figure designation buffer value) is “1” in response to the execution of the special figure game using the first special figure by the first special symbol display device 4A. Set to Further, the variable special figure designation buffer value is set to “2” in response to the execution of the special figure game using the second special figure by the second special symbol display device 4B. Then, the variable special figure designation buffer value is set to “0” in response to the completion of the special figure game.

  In the jackpot type buffer, the variable display mode of the decorative symbol when the variable display result is “big hit” is a plurality of types of jackpot types such as “normal”, “first probability variation” to “third probability variation”, and “surprise probability”. The buffer value corresponding to the determination result as one of the above is stored. As an example, based on the setting in the jackpot type determination table 131 as shown in FIG. 24, when the jackpot type is “normal”, the value of the jackpot type buffer (hit type buffer value) is set to “0”, and the jackpot type When the type is “first probability variation”, the big hit type buffer value is set to “1”, when the big hit type is “second probability variation”, the big hit type buffer value is set to “2”, and the big hit type is In the case of “third probability variation”, the big hit type buffer value is set to “3”, and when the big hit type is “surprise”, the big hit type buffer value is set to “4”.

  A game ball that has entered any of the starting winning ports is effective in the starting port buffer, among the first starting winning port formed by the normal winning ball device 6A and the second starting winning port formed by the normal variable winning ball device 6B. The buffer value corresponding to the detected value is stored as the start port buffer value. As an example, when a game ball that has entered the first start winning opening is effectively detected by the first start opening switch 22A, the start buffer value is set to “1”, and a game ball that has entered the second start winning opening. Is effectively detected by the second start port switch 22B, the start port buffer value is set to "2".

  As shown in FIG. 2, an effect control microcomputer 120 is mounted on the effect control board 12. The effect control board 12 includes a VDP (Video Display Processor) 121 that generates image data in response to a drawing command from the effect control microcomputer 120, the image display device 5, speakers 8L and 8R, and a game effect lamp 9. An effect data memory 122 for storing various data used for controlling the effect operation by the effect device such as a light emitter is also mounted. The effect control microcomputer 120 is a one-chip microcomputer having the same configuration as the game control microcomputer 100, for example, and includes an external bus interface, a clock circuit, a unique information storage circuit, a reset / interrupt controller, a CPU, a ROM, and a RAM. , CTC, random number circuit, PIP, serial communication circuit, address decoding circuit, and the like. Further, all or part of the configuration of the effect control microcomputer 120 may be different from the configuration of the game control microcomputer 100. As an example, in the case where all the numerical data serving as random number values used on the side of the effect control board 12 are updated by software, the effect control microcomputer 120 may not include the random number circuit. Further, the serial communication circuit only needs to be provided with a receiving circuit capable of receiving at least an effect control command transmitted from the main board 11, and data and commands for the image display device 5, the audio control board 13, and the lamp control board 14 are provided. Signal transmission may be performed using an external bus interface or an address decoding circuit.

  In the effect control microcomputer 120, the CPU executes the effect control program read from the ROM, thereby executing a process for controlling the effect operation by the effect electrical component (effect device). At this time, a fixed data reading operation in which the CPU reads fixed data from the ROM, a variable data writing operation in which the CPU writes various fluctuation data in the RAM and temporarily stores the data, and various fluctuation data in which the CPU is temporarily stored in the RAM. Fluctuating data reading operation for reading out, receiving operation for receiving various signals input from the outside of the production control microcomputer 120 via the external bus interface, PIP, serial communication circuit, etc., CPU for external bus interface, serial communication circuit, etc. A transmission operation for outputting various signals to the outside of the effect control microcomputer 120 is also performed. It should be noted that the one-chip microcomputer constituting the production control microcomputer 120 only needs to incorporate a RAM in addition to at least the CPU, and the ROM, random number circuit, PIP, and the like are incorporated even if they are externally attached. May be used.

  In this embodiment, a control signal, which is an effect control command transmitted from the main board 11 via the relay board 18, is supplied to a predetermined serial receiving terminal provided in the effect control microcomputer 120, and the effect control microcomputer. The data is received by a serial communication circuit built in 120.

  A scaler circuit for converting the resolution in the image data may be provided between the effect control board 12 and the image display device 5. In this case, the image data generated by the VDP 121 mounted on the effect control board 12 according to the drawing command from the effect control microcomputer 120 is supplied to the image display device 5 after the resolution is converted by the scaler circuit. . As a specific example, the scaler circuit inputs the image data with the first resolution generated by the VDP and performs the following processing on one or both of the vertical direction and the horizontal direction. The converted image data is converted to a second resolution different from the first resolution.

  For example, when converting the resolution in the vertical direction, after performing upsampling at a first sample rate along the vertical direction of the input image data, a filtering process using a filter (for example, an FIR filter) prepared in advance. Apply. Thereafter, downsampling may be performed at a second sample rate corresponding to a predetermined scaling coefficient along the vertical direction. When converting the resolution in the horizontal direction, upsampling, filtering, and downsampling similar to those in the vertical direction may be performed along the horizontal direction of the input image data. As a specific example, when image data in VGA mode (640 × 480 pixels) is generated by VDP, the image data is converted into SXGA mode (1280 × 1024 pixels) or other modes by conversion processing in the scaler circuit. Can be converted to

  On the voice control board 13, for example, an input / output driver, a voice synthesis IC, a voice data ROM, an amplifier circuit, a volume, and the like are mounted. As an example, in the voice control board 13, the sound number data indicated in the sound effect signal transmitted from the effect control board 12 is input to the voice synthesis IC via the input / output driver. The voice synthesis IC generates voice and sound effects corresponding to the sound number data and outputs them to the amplifier circuit. The amplifier circuit outputs an audio signal obtained by amplifying the output level of the speech synthesis IC to a level corresponding to the volume set by the volume to the speakers 8L and 8R. The voice data ROM stores control data corresponding to the sound number data, and the voice synthesis IC reads out the control data corresponding to the sound number data to generate sound and sound effects. The data stored in the audio data ROM may be composed of data indicating the output mode of audio and sound effects in a predetermined period in time series.

  For example, an input / output driver and a lamp driver are mounted on the lamp control board 14. As an example, in the lamp control board 14, the electrical decoration signal transmitted from the effect control board 12 is input to the lamp driver via the input / output driver. The lamp driver amplifies the electric decoration signal and supplies it to the game effect lamp 9 and the like.

  On the payout control board 15, a payout control microcomputer 150, a switch circuit 151, and the like are mounted. The switch circuit 151 receives detection signals from various switches and sensors, such as the full tank switch 26, the ball-out switch 27, the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. The switch circuit 151 takes these detection signals and transmits them to the payout control microcomputer 150. The payout control microcomputer 150 is, for example, a one-chip microcomputer similar to the game control microcomputer 100, and includes an external bus interface, a clock circuit, a specific information storage circuit, a reset / interrupt controller, a CPU, a ROM, a RAM, a CTC, A random number circuit, PIP, serial communication circuit, address decoding circuit, and the like may be provided. Further, all or part of the configuration of the payout control microcomputer 150 may be different from the configuration of the game control microcomputer 100. As an example, when numerical data that is a random number value is not used on the payout control board 15 side, the payout control microcomputer 150 may not include a random number circuit. Further, in the serial communication circuit, it is only necessary to provide at least one transmission / reception circuit capable of bidirectional serial communication with the main board 11, and data for the payout motor 51, the error display LED 74, and the launch control board 17. The command signal may be transmitted using an external bus interface or an address decoding circuit.

  In the payout control microcomputer 150, the CPU executes a payout control program read from the ROM, thereby executing processing for controlling the payout operation by the payout device including the payout motor 51 and the like. At this time, a fixed data reading operation in which the CPU reads fixed data from the ROM, a variable data writing operation in which the CPU writes various fluctuation data in the RAM and temporarily stores the data, and various fluctuation data in which the CPU is temporarily stored in the RAM. Data reading operation for reading out, receiving operation for receiving various signals input from the outside of the payout control microcomputer 150 via the external bus interface, PIP, serial communication circuit, etc., CPU for external bus interface, serial communication circuit, etc. A transmission operation for outputting various signals to the outside of the payout control microcomputer 150 is also performed. It should be noted that the one-chip microcomputer constituting the payout control microcomputer 150 may include at least RAM in addition to the CPU, and ROM, PIP, and the like may be externally attached or incorporated. Good.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply from the power supply board 10 is started and the reset signal to the game control microcomputer 100 becomes high level (off state), the game control microcomputer 100 is activated, Based on the security check program 506A read from the ROM 506 by the CPU 505, a security check process as shown in the flowchart of FIG. At this time, the game control microcomputer 100 is in the security mode, and the game control user program stored in the ROM 506 is not yet executed.

  When the security check process shown in FIG. 26 is started, the CPU 505 first executes a process for determining a time (security time) when the game control microcomputer 100 is in the security mode by executing the security check process. . At this time, the CPU 505 reads the bit value in the bit number [2-0] of the security time setting KSES stored in the program management area of the ROM 506 (step S1). Then, it is determined whether or not the read value is “000” (step S2).

  If it is determined in step S2 that the read value is “000” (step S2; Yes), the steady set time is set to a predetermined fixed time (step S3). Here, the regular setting time is constant regardless of the number of times of security check processing based on the occurrence of a system reset in the pachinko gaming machine 1 (the number of times that the gaming control microcomputer 100 enters the security mode). Is a time component. The fixed time is an invariant time component that is predetermined based on the specifications of the game control microcomputer 100 in the security time, and may be any minimum value that can be set as the security time, for example.

  If it is determined in step S2 that the read value is other than “000” (step S2; No), it is selected according to the set value shown in FIG. 10D in addition to the fixed time corresponding to the read value. The extended time is set to the steady set time (step S4). In this way, when the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, the security time as the execution time of the security check process can be selected in advance in addition to the fixed time. It can be set to any one of a plurality of extension times.

  After executing one of the processes of steps S3 and S4, the bit value in the bit number [4-3] of the security time setting KSES is read (step S5). Then, it is determined whether or not the read value is “00” (step S6).

  If it is determined in step S6 that the read value is “00” (step S6; Yes), the steady setting time is set as the security time (step S7). On the other hand, when it is determined that the read value is other than “00” (step S6; No), the variable setting time determined in accordance with the read value is added to the steady setting time to obtain the security time. (Step S8). Here, the variable setting time is a time component that changes every time the security check process is executed, and the bit value in the bit number [4-3] of the security time setting KSES is “01” (short). Mode) or “10” (long mode), and changes in different predetermined time ranges. For example, when a count value in a predetermined free-run counter is stored in a variable security time register built in the game control microcomputer 100 when a system reset occurs, in the process of step S8, for the variable security time By using the stored value of the register as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable setting time is within a predetermined time range for each system reset. It may be determined so as to change randomly. Thus, when the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the security time that is the execution time of the security check process is set as the security based on the occurrence of the system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  Here, the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, and the bit value in the bit number [4-3] of the security time setting KSES is other than “00”. In this case, both the extension time set in step S4 and the variable setting time set in step S8 are added to the fixed time, and the security time is determined. .

  After executing one of the processes in steps S7 and S8, the security code stored in the predetermined area of the ROM 506 is read (step S9). Here, in a predetermined area of the ROM 506, a security code of a calculation result obtained by calculating the data of the stored content by a predetermined calculation formula is stored in advance. As a security code generation method, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 506, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing in step S9, the encrypted arithmetic expression is decrypted and restored (step S10). Thereafter, the storage code in the predetermined area of the ROM 506 is calculated by the arithmetic expression decrypted in step S10 to specify the security code (step S11). The storage data used for the calculation for specifying the security code at this time is, for example, program data corresponding to all or part of the user program different from the security check program 506A among the storage data of the ROM 506, or predetermined table data May be all or a part of the fixed data constituting the. Then, the security code read in step S9 is compared with the security code specified in step S11 (step S12). At this time, it is determined whether or not the security codes match in the comparison result (step S13).

  If the security codes do not match in step S13 (step S13; No), it is determined that an unauthorized change has been made to the ROM 506, and the operation of the CPU 505 is shifted to a halt state (HALT). On the other hand, if the security codes match in step S13 (step S13; Yes), it is determined whether or not the security time set in the processing of step S7 or step S8 has elapsed (step S14). . At this time, if the security time has not elapsed (step S14; No), the process of step S14 is repeatedly executed and waits until the security time elapses. If it is determined in step S14 that the security time has elapsed (step S14; Yes), for example, the value of the program counter built in the CPU 505 is set to the start address (address 0000H) of the user program in the ROM 506. Thus, the execution of the game control main process is started. Thus, when the execution of the game control main process is started, the operation state of the game control microcomputer 100 is shifted from the security mode to the user mode, and the execution of the user program stored in the ROM 506 is started. Become.

  FIG. 27 is a flowchart showing an example of a game control main process executed by the CPU 505 of the game control microcomputer 100. Each process described below is executed by the CPU 505 provided in the game control microcomputer 100. An interrupt request based on various interrupt factors generated by the CTC 508, the random number circuit 509, the serial communication circuit 511, etc. provided in the game control microcomputer 100 is for causing the CPU 505 to execute predetermined interrupt processing. The concept including the CPU 505 and various circuits other than the CPU 505 is sometimes referred to as a game control microcomputer 100. When the game control main process shown in FIG. 27 is started, the CPU 505 first sets the interrupt prohibition (step S21) and sets the interrupt mode (step S22). For example, in step S22, the value (1 byte) of the specific register (I register) of the game control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output from the built-in device are synthesized. As a result, the interrupt mode [2] of the maskable interrupt in which the interrupt address is generated is set. When an interrupt that can be masked occurs, the CPU 505 performs a setting for automatically disabling the interrupt, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S23). Further, the internal register is set (initialized) as shown in FIG. 7B (step S24). Subsequent to step S24, the CTC 508 and PIP 510 are set (step S25). After the process of step S25 is executed, it may be determined whether or not the power-off signal is in an off state, for example, by checking a terminal state at a predetermined input port included in the PIP 510.

  Thereafter, the RAM 507 is set to be accessible (step S26). Subsequently, based on the signal state of the switch signal (clear signal) transmitted from the clear switch 304 installed on the power supply board 10, it is determined whether the clear switch 304 is turned on (step S27). In the process of step S27, the clear signal transmitted from the clear switch 304 may be checked a plurality of times, and it may be determined that the clear switch 304 has been turned on when the clear signal is continuously turned on. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When the clear switch 304 is OFF in step S27 (step S27; No), it is determined whether or not a backup flag provided in the game control flag setting unit 592 is ON (step S28). The state of the backup flag is set in the game control flag setting unit 592 or the like when power supply to the game control microcomputer 100 is stopped. The backup flag setting location is backed up by the backup power source, so that the state of the backup flag is saved even when the power supply is stopped. In step S28, for example, if “55H” is set in the game control flag setting unit 592 as the value of the backup flag, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state).

  If the backup flag is on in step S28 (step S28; Yes), data check of the RAM 507 is performed to determine whether the check result is normal (step S29). In the process of step S29, for example, a checksum is calculated using data stored in a specific area of the RAM 507, and the calculated checksum is compared with the checksum stored in the main checksum buffer. Here, the main checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 507 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S29 is normal (step S29; Yes), for example, the control state of the main board 11 such as the internal state of the game control microcomputer 100 or the sub-side control board (for example, the effect control board 12). A setting at the time of restoration for returning the control state to the state when the power supply is stopped is performed, and the gaming state before the power interruption is restored (step S30). As a specific example, in the process of step S30, the start address of the backup setting table stored in the ROM 506 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 507. Here, the work area of the RAM 507 is backed up by a backup power source, and initialization data for an area that may be initialized among the work areas may be set in the backup time setting table.

  When the clear switch 304 is on in step S27 (step S27; Yes), when the backup flag is off in step S28 (step S28; No), or the check result is not normal in step S29. Sometimes (step S29; No), initialization processing corresponding to power-on or system reset that is not during a power failure recovery is executed. In this initialization process, the RAM 507 is cleared (initialized) (step S31), and a work area to be a work area is set (step S32). In the process of step S31, predetermined data (for example, stored data in a random counter provided in the game control counter setting unit 594) may be set to an arbitrary value or a predetermined initial value. Further, the entire area of the RAM 507 may be initialized, or a part of the area may be initialized while the predetermined data is left as it is. When the process of step S31 is executed, the operation state of the random number circuit 509 may be initialized. The initial value may be set in the game control flag setting unit 592, the game control timer setting unit 593, the game control counter setting unit 594, the game control buffer setting unit 595, and the like by the process of step S <b> 32. At this time, a control command (initialization designation command) for initializing each sub-side control board such as the effect control board 12 may be transmitted. For example, the presentation control board 12 displays an image for notifying that the control in the pachinko gaming machine 1 is initialized on the display screen of the image display device 5 in response to the reception of the initialization designation command. It suffices if initialization notification is executed.

  After the game state before the power interruption is restored in step S30 or after the process of step S32 is executed, various circuits built in the microcomputer 100 for game control are based on the stored data in the program management area of the ROM 506. Operation setting is performed (step S33). As an example, in the process of step S33, the first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area are read, and the random number circuit setting process as shown in the flowchart of FIG. 28 is executed. The Note that the process of step S33 may be executed when the process of step S24 or the process of step S25 is executed.

  In the random number circuit setting process shown in FIG. 28, first, the CPU 505 performs setting for using the random number circuit 509 based on the bit value in the bit number [3] of the first random number initial setting KRS1 (step S51). In this embodiment, the bit value in the bit number [3] of the first random number initial setting KRS1 is set to “1” in advance, and setting to use the random number circuit 509 is performed corresponding to this bit value. Subsequently, the random number update clock RGK in the random number circuit 509 is set based on the bit value in the bit number [2] of the first random number initial setting KRS1 (step S52). For example, in response to the bit value [2] of the first random number initial setting KRS1 being set to “1” in advance, the random number clock RCLK generated by the random number clock generation circuit 112 is divided by two. As a result, the random number update clock RGK is set.

  After the setting in step S52, the random number update rule is set in the random number circuit 509 based on the bit value in the bit number [1-0] of the first random number initial setting KRS1 (step S53). For example, when the bit value in the bit number [1-0] of the first random number initial setting KRS1 is set to “00” in advance, the random number update designating the update order of the numerical data that becomes the random value in the random number sequence RSN The rule is set so as not to change after the second round. If the bit value in the bit number [1-0] of the first random number initial setting KRS1 is set to “01” in advance, the random number update rule in the random number sequence RSN is set to be changed by software after the second round. Is made. Further, when the bit value [1-0] of the first random number initial setting KRS1 is set to “10” in advance, the random number update rule in the random number sequence RSN is automatically changed after the second round. Is made.

  Subsequently, based on the bit value in the bit number [1] of the second random number initial setting KRS2, the start value at start-up in the numerical data that becomes the random value is determined (step S54). For example, when the bit value in the bit number [1] of the second random number initial setting KRS2 is set to “0” in advance, the random value start value is set to the default value “0001H”. Further, when the bit value [1] of the second random number initial setting KRS2 is set to “1” in advance, the random number start value is set to a value based on the ID number.

  Further, based on the bit value in the bit number [0] of the second random number initial setting KRS2, it is set whether or not to change the start value of the numerical data serving as the random value every time the system is reset (step S55). For example, when the bit value [0] of the second random number initial setting KRS2 is set to “0” in advance, the pachinko gaming machine 1 is activated when the power is initially turned on (activation after backup is disabled). Regardless of whether the system is reset due to system reset, the start value set in step S54 may be used as it is as the start value in the random number circuit 509. In addition, when the bit value in the bit number [0] of the second random number initial setting KRS2 is set to “1” in advance, a setting for changing the start value of the random number at every system reset is made. For example, when a count value in a predetermined free-run counter is stored in a random number start value register built in the game control microcomputer 100 when a system reset occurs, in the process of step S55, for the random number start value By using the stored value of the register as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the random number start value becomes a predetermined numerical value every time the system is reset. It may be determined so as to change randomly within a range (for example, a range including all or part of numerical data included in the count value permutation RCN generated by the random number generation circuit 553). When the setting by the processing in step S55 is completed, the random number circuit 509 may start the random value generation operation.

  It should be noted that the setting by the random number circuit setting process may be performed autonomously by the random number circuit 509 based on the stored data in the program management area without the processing of the CPU 505 being involved. In this case, when the game control microcomputer 100 is in the security mode, the random number circuit 509 may not perform the initial setting and may not perform the random value generation operation. Then, when the CPU 505 reads out the user program stored in the ROM 506 in the game control microcomputer 100 and the execution of the game control main process is started, the CPU 505 instructs the random number circuit 509 to perform initial setting, for example. In response to the signal being transmitted, the random number circuit 509 may perform the initial setting and then start the random value generation operation. Alternatively, particularly when the random number circuit 509 is externally attached to the game control microcomputer 100, the random number circuit 509 is independent of the processing in the CPU 505 even when the game control microcomputer 100 is in the security mode. Thus, the random number generation operation may be started after the initial setting based on the stored data in the program management area. The process of step S33 shown in FIG. 27 includes a process of reading the interrupt initial setting KIIS stored in the program management area and setting the priority control of maskable interrupt factors in the reset / interrupt controller 504. May be. When setting the priority order of the maskable interrupt factor, the highest priority interrupt is set according to the bit value in the bit number [3-0] of the interrupt initial setting KIIS. For example, by setting the bit value [3-0] of the interrupt initial setting KIIS to “04H” or “05H” in advance, the interrupt processing due to the interrupt factor generated in the serial communication circuit 511 has the highest priority. Can be executed. Thus, by performing priority control of maskable interrupt factors according to the bit value in bit number [3-0] of interrupt initial setting KIIS, the priority order of interrupt processing can be arbitrarily set, and the degree of freedom of design is increased. be able to.

  After the setting in step S33, random number circuit abnormality inspection processing for inspecting the presence or absence of operation abnormality in the random number circuit 509 is executed (step S34). FIG. 29 is a flowchart showing an example of the random number circuit abnormality inspection process executed in step S34.

  In the random number circuit abnormality inspection process shown in FIG. 29, the CPU 505 first clears the random number clock abnormality determination counter provided in, for example, the game control counter setting unit 594, and the random number clock abnormality determination count that is the count value. The value is initialized to “0” (step S61). Subsequently, the internal information data CIF4 stored in the bit number [4] of the internal information register CIF is read (step S62). Then, it is determined whether or not the read value in step S62 is “1” (step S63). At this time, if the frequency monitoring circuit 551 provided in the random number circuit 509 detects a frequency abnormality in the random number clock RCLK from the random number external clock terminal ERC, the bit value “1” is written as the internal information data CIF4. .

  Therefore, when it is determined in step S63 that the read value is “1” (step S63; Yes), the random number clock abnormality determination count value is updated to be incremented by 1 (step S64). At this time, it is determined whether or not the count value after the update in step S64 has reached a predetermined clock abnormality determination value (step S65). Here, the clock abnormality determination value may be a numerical value determined in advance in order to determine that the clock abnormality is detected when the frequency monitoring circuit 551 continuously detects the frequency abnormality of the random number clock RCLK. If the clock abnormality determination value has not been reached in step S65, the process returns to step S62, and determination based on the bit value of the internal information data CIF4 is performed again.

  When the clock abnormality determination value is reached in step S65 (step S65; Yes), a predetermined random number clock error process is executed (step S66), and the random circuit abnormality inspection process is terminated. In the random number clock error process, for example, a setting for transmitting a predetermined effect control command to the effect control board 12 is performed, and the effect device detects that a frequency abnormality of the random number clock RCLK has been detected. In addition, the processing may not proceed until a predetermined error canceling procedure (for example, system reset or error canceling switch operation) is taken. Further, the operation of the CPU 505 may be shifted to a halt state (HALT) without executing the random number clock error process.

  When the read value is determined to be “0” in step S63 (step S63; No), for example, the random value abnormality determination counter provided in the game control counter setting unit 594 or the like is cleared, and the count value is used. A certain random value abnormality determination count value is initialized to “0” (step S67). In the process of step S63, the read value is “0” when the bit value of the internal information data CIF4 read in step S62 is continuously “0” a plurality of times (for example, twice). May be determined.

  Subsequent to the processing in step S67, the check value used for checking whether there is an abnormality in the random number value is set to an initial value “0000H” (step S68). Then, the stored numerical data as the random value is read from the random value register 559A serving as the random value register R1D and the random value register 559B serving as the random value register R2D provided in the random number circuit 509 (step S69). For example, in the process of step S69, the bit values of the random number latch selection data RDLS1 and the random number latch selection data RDLS0 stored in the bit number [1] and the bit number [0] of the random number latch selection register RDLS are set to “0”. Specifies fetching random values by. Subsequently, the bit values of the random number acquisition specification data RDLT1 and the random value acquisition specification data RDLT0 stored in the bit number [1] and the bit number [0] of the random value acquisition specification register RDLT are set to “1”. Specifying loading into the random value register R2D or the random value register R1D. Note that setting the bit value in the bit number [1] or bit number [0] of the random number fetch specification register RDLT to “1” instructs the CPU 505 to fetch (latch) numerical data to the random number circuit 509. This corresponds to outputting a latch signal. After that, by turning on the register read signal RRS2 supplied to the random value register R2D or turning on the register read signal RRS1 supplied to the random value register R1D, the numerical data that becomes the stored random value May be read out. Note that the numerical data stored in each of the random value register R2D and the random value register R1D may be read simultaneously to check whether there is an abnormality in the random number value, or after checking whether there is an abnormality in one of the registers. The other register may be checked for abnormality.

  After reading the numerical data in step S69, the read value is set as a random number inspection reference value (step S70). Subsequently, numerical data that becomes a random value is read from the random value register 559A and the random value register 559B (step S71). Note that the read operation in step S71 may be performed in the same procedure as the read operation in step S69. In addition, a sufficient delay time may be provided between the read operation in step S69 and the read operation in step S71 so that the numerical data in the random number sequence RSN generated by the random number circuit 509 changes. After reading the numerical data in step S71, an exclusive OR operation is performed on the random number inspection reference value and the read value in step S71 (step S72). Further, a logical sum operation between the calculation result in step S72 and the check value is executed, and the calculation result is updated to be a new check value (step S73). For example, the check value may be stored in a predetermined area of the RAM 507, and each time the process of step S73 is executed, the calculation result obtained by the process may be saved as a new check value. As a result, changes in all the bits in the numerical data read from the random value register 559A and the random value register 559B are recorded, and if the bit has changed at least once during a plurality of times of reading, it corresponds in the check value. The bit value is “1”.

  Therefore, it is determined whether or not the check value is “FFFFH” (step S74). If it is (step S74; Yes), since the change of the bit value is recognized for all bits, the random number value is normal. The random number circuit abnormality inspection process is terminated by determining that the number has been updated. When it is confirmed that the random number value has been updated normally, the random number latch selection data RDLS1 and the random number latch selection stored in the bit number [1] and the bit number [0] of the random number latch selection register RDLS are selected. The bit value of the data RDLS0 is set to “1”, the random value is taken into the random value register R2D according to the signal input to the input port P1, and the random value register R1D according to the signal input to the input port P0 You may make it instruct | indicate numerical value acquisition. In this embodiment, a wiring for transmitting the first start winning signal SS1 from the first start port switch 22A is connected to the input port P0, and the second start winning signal SS2 from the second start port switch 22B is connected to the input port P1. Are connected. Thereby, when the first start winning signal SS1 is turned on, the random number value is taken into the random value register R1D, while when the second starting winning signal SS2 is turned on, the random value register R2D is entered. It is possible to take in random values.

  When it is determined in step S74 that the check value is other than “FFFFH” (step S74; No), the random number abnormality determination count value is updated to be incremented by 1 (step S75). At this time, it is determined whether or not the count value after the update in step S75 has reached a predetermined random value abnormality determination value (step S76). Here, the random value abnormality determination value is determined so that all bits of the numerical data read from the random value register 559A and the random value register 559B change at least once if the random number circuit 509 is operating normally. It may be a predetermined numerical value so as to be the number of times. If the random number abnormality determination value has not been reached in step S76, the process returns to step S71, and determination for reading numerical data as a random value from the random number circuit 509 and checking for abnormality is performed.

  If the random value abnormality determination value is reached in step S76 (step S76; Yes), a predetermined random value error process is executed (step S77), and the random circuit abnormality inspection process is terminated. In the random value error process, for example, a setting for transmitting a predetermined effect control command to the effect control board 12 is performed to notify that an abnormality in the random value is detected by the effect device. Until the error canceling procedure (for example, system reset, error canceling switch operation, etc.) is taken, the subsequent processing may not proceed. Further, the operation of the CPU 505 may be shifted to the halt state (HALT) without executing the process at the time of random value error.

  The random number circuit abnormality inspection process in step S34 is not limited to that executed by the CPU 505, and the random number circuit abnormality inspection process may be executed by a built-in circuit in the game control microcomputer 100 other than the CPU 505. As an example, the random number circuit 509 has a function of executing a random number circuit abnormality inspection process. When a frequency abnormality of the random number clock RCLK is detected or when an abnormality of the random number value is detected, the CPU 505 May be notified. The random number circuit abnormality inspection process is not limited to the process executed only in step S34. For example, every time a timer interrupt occurs in the game control microcomputer 100, a game control timer interrupt process (see FIG. 30), part or all of the random number circuit abnormality inspection process may be executed.

  After executing the random number circuit abnormality inspection process as described above in step S34 shown in FIG. 27, the game start switch is based on the signal state of the switch signal transmitted from the game start switch 31 installed on the main board 11. It is determined whether or not 31 has been turned on (step S35). In the process of step S35, the switch signal transmitted from the game start switch 35 may be checked a plurality of times, and it may be determined that the game start switch 31 is turned on when the switch signal is continuously turned on. Further, the process of step S35 is executed only when starting from the initial state without recovery (at the time of cold start), for example, when the processes of step S31 and step S32 are executed. For example, the process of step S30 is performed. Controls the progress of the game, for example, a game control timer interrupt process, regardless of the operation of the game start switch 31 at the time of start (at the time of hot start) to restore the game state before the power interruption as if executed You may make it progress to the process to do. Here, in the RAM 507 provided in the game control microcomputer 100, when an area to be a random counter provided in the game control counter setting unit 594 is backed up by a backup power source, if it is a hot start, before power interruption Since the update of numerical data serving as a random value is started using the stored data in the random counter, it is difficult to specify the random value stored in the random counter from the operation start timing of the pachinko gaming machine 1. On the other hand, at the time of cold start, for example, the random counter is cleared (initialized) in the process of step S31, so that updating of the random number value is started from a certain initial value (for example, “0” or the like) There is a possibility that the random value stored in the random counter is specified from the operation start timing of the pachinko gaming machine 1. Therefore, at the cold start, the process of step S35 is executed until the game start switch 31 is turned on, and it is difficult to specify the random number value stored in the random counter from the operation start timing of the pachinko gaming machine 1. To. As a result, the operation of the pachinko gaming machine 1 is started by connecting a so-called “hanging board” particularly when the random number value for jackpot determination (for example, the random number value MR1 for special figure display result determination) is updated only by software. Even if an illegal signal is input at a timing when a predetermined time has elapsed from the timing, an illegal big hit gaming state can be prevented. If it is determined in step S35 that the game start switch 31 is not turned on, the random number update process is executed and the random number stored in the random counter is updated by software before returning to the process of step S35. You may make it do. Accordingly, in addition to the elapsed time from the timing when the game start switch 31 is turned on, the elapsed time from the operation start timing of the pachinko gaming machine 1 to when the game start switch 31 is turned on cannot be specified. Even at cold start, it becomes difficult to specify the random value stored in the random counter, and it is possible to reliably prevent actions such as illegally generating a big hit gaming state by aiming or inputting illegal signals it can.

  If it is determined in step S35 that the game start switch 31 is off (step S35; No), the process of step S35 is repeatedly executed, and the process waits until the game start switch 31 is turned on. Thus, even after a predetermined initial setting process is executed by the game control microcomputer 100, the progress of the game, such as a game control timer interrupt process, is controlled until the game start switch 31 is turned on. Processing execution does not start. The initial setting process executed by the game control microcomputer 100 includes, for example, the entire security check process shown in FIG. 26 and the processes of steps S21 to S39 in the game control main process shown in FIG. Should be included.

  If it is determined in step S35 that the game start switch 31 is turned on (step S35; Yes), or if the process of step S35 is not executed, based on the value of the bit number [0] of the random number latch flag register. It is determined whether or not the random number value is latched, that is, whether or not numerical data is taken into the random value register 559A (step S36). If numerical data is not taken into the random value register 559A (step S36; No), the process proceeds to step S38 as it is. If the numerical data has been taken into the random value register 559A (step S36; Yes), the numerical data taken into the random value register 559A is read and discarded without being stored as it is (step S37). Then, the process proceeds to step S38.

  In step S38, it is determined whether or not the random number value is latched based on the value of the bit number [1] of the random number latch flag register, that is, whether or not numerical data is taken into the random value register 559B. If the numerical data is not taken into the random value register 559B (step S38; No), the process proceeds to step S40 as it is. If numerical data has been captured in the random value register 559B (step S38; Yes), the numerical data captured in the random value register 559B is read out and discarded without being stored as it is (step S39). Then, the process proceeds to step S40.

  In step S40, the interrupt enabled state is set, and various interrupt requests are awaited. The process of step S40 may also be included in the initial setting process executed by the game control microcomputer 100. After executing the process of step S40, for example, based on the setting of the CTC 508 in step S25, a timer interrupt for game control may be generated every 2 milliseconds. After executing the process of step S40, the random number update process is repeatedly executed (step S41).

  After entering the interrupt enabled state by executing the processing of step S40 in this way, for example, when a plurality of maskable interrupt factors occur simultaneously in part or all of the CTC 508, the random number circuit 509, the serial communication circuit 511, etc. Based on the designation by the bit value in the bit number [3-0] of the initial setting KIIS, the reset / interrupt controller 504 accepts an interrupt factor having a high priority. When the reset / interrupt controller 504 accepts an interrupt factor, it outputs an on-state interrupt request signal to, for example, an I class interrupt (IRQ) terminal provided in the CPU 505. When an on-state interrupt request signal is input to the IRQ terminal by the CPU 505, the generated interrupt factor is identified based on, for example, the result of checking the data stored in the internal register, and the vector address corresponding to the identified interrupt factor By executing the program having the first address as the interrupt address, interrupt processing based on each interrupt factor can be started.

  In the game control microcomputer 100, for example, based on the fact that the reset / interrupt controller 504 has received an interrupt request from the CTC 508, the CPU 505 executes the game control timer interrupt process shown in the flowchart of FIG. In the game control timer interrupt process shown in FIG. 30, the CPU 505 first sets the interrupt disabled state, and then executes a predetermined switch process, whereby each game ball detection switch 21, 22A, The state of the detection signal (winning detection signal) input from 22B, 23, etc. is determined (step S91). Subsequently, by executing predetermined main-side error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and if necessary, warning can be generated according to the diagnosis result (step S92). For example, in the main-side error processing, settings for notifying the occurrence of an abnormal operation may be performed in response to excessive prize balls, insufficient prize balls, or other operation errors. After that, by executing a predetermined information output process, for example, data such as jackpot information, starting information, probability variation information supplied to a hall management computer installed outside the pachinko gaming machine 1 is output (step) S93).

  Subsequent to the information output process, a random number update process is executed (step S94). Thereafter, the CPU 505 executes special symbol process processing (step S95). In the special symbol process, the value of the special symbol process flag provided in the game control flag setting unit 592 is updated according to the progress of the game in the pachinko gaming machine 1, and the first special symbol display device 4A or the second special symbol is processed. Various processes are selected and executed in order to perform control of the display operation in the display device 4B and setting of opening / closing operation of the special winning opening in the special variable winning ball device 7 in a predetermined procedure.

  Following the special symbol process, the normal symbol process is executed (step S96). The CPU 505 controls the display operation (for example, turning on / off the segment LED) on the normal symbol display 20 by executing the normal symbol process, thereby allowing the normal symbol variable display and the normal variable winning ball apparatus 6B to move. Enables setting of the tilting movement of the blade. After executing the normal symbol process, the CPU 505 executes a prize ball process for setting the number of prize balls according to the input of the winning detection signal based on the execution result of the switch process in step S91, for example (step S97). ). Subsequent to the prize ball process, the main side communication control process is executed, so that a control command is transmitted from the main board 11 to a sub-side control board such as the effect control board 12 or the payout control board 15 or the payout control is performed. Communication control for receiving a control command transmitted from the board 15 is performed (step S98).

  When such main-side communication control processing is completed, the game control timer interrupt processing is terminated after the interrupt is permitted.

  FIG. 31 is a flowchart showing an example of processing executed in step S41 shown in FIG. 27 or step S94 shown in FIG. 30 as the random number update processing. In the random number update process shown in FIG. 31, the CPU 505 first sets the interrupt prohibited state (step S501). Note that when the game control microcomputer 100 automatically enters an interrupt-inhibited state in response to the start of the random number update process, the process of step S501 need not be executed. Subsequently, for example, by updating the stored data in a predetermined area of the random counter provided in the game control counter setting unit 594, the random number MR2 for determining the big hit type is incremented by 1 (step S502). Thus, in this embodiment, the random number MR2 for determining the big hit type is updated so that it is incremented by one every time a timer interrupt occurs. After executing the processing in step S502, the reach determination random number MR3 is set as a random number to be updated (step S503).

  Then, the CPU 505 reads out numerical data indicating the random value MR6 for determining the addition value from, for example, a random counter provided in the game control counter 594 (step S504). At this time, it is determined whether or not the read value in step S504 is less than the addition determination value determined for each random value to be updated (step S505). Here, as shown in FIG. 12, the addition determination value is determined in advance corresponding to each of the random number values MR3 to MR5. If the read value is less than the addition determination value in step S505 (step S505; Yes), the random value MR6 read in step S504 is set as the addition value (step S506). On the other hand, if the read value is equal to or greater than the addition determination value in step S505 (step S505; No), a value obtained by subtracting the addition determination value from the random value MR6 read in step S504 is set as the addition value. (Step S507).

  After executing one of the processes in steps S506 and S507, the addition value is added to the random number value to be updated (step S508). At this time, it is determined whether or not the random number value after addition obtained in step S508 is less than the maximum determination value determined for each random value to be updated (step S509). Here, as shown in FIG. 12, the maximum determination value is determined in advance corresponding to each of the random number values MR3 to MR5. If the random number value after addition is less than the maximum determination value in step S509 (step S509; Yes), the random number value after addition obtained in step S508 is set as the updated random number value (step S510). On the other hand, if the random number value after addition is greater than or equal to the maximum determination value in step S509 (step S509; No), the value obtained by subtracting the maximum determination value from the random number value after addition obtained in step S508 is updated. A subsequent random value is set (step S511).

  After executing one of the processes in steps S510 and S511, the updated random number value is set in a predetermined area for storing the random number value to be updated by the random counter (step S512). In this way, the update of the random number value to be updated is completed. Following the processing of step S512, it is determined whether there is an unprocessed random number value (step S513). In this embodiment, the random number values MR3 to MR5 are sequentially set to the random number values to be updated, so that every time the random number update process is executed, all of the random number values MR3 to MR5 are updated. To be. If there is an unprocessed random value in step S513 (step S513; Yes), the next random value is set as a random value to be updated (step S514), and the process returns to step S504. . On the other hand, if there is no unprocessed random number value in step S513 (step S513; No), the interruption is permitted (step S515), and the random number update process is terminated.

  FIG. 32 is a flowchart showing an example of processing executed in step S95 shown in FIG. 30 as the special symbol process. In this special symbol process, the CPU 505 first executes a start winning determination process (step S101). 33 and 34 are flowcharts showing an example of the start winning determination process executed in step S101.

  In the start winning determination process shown in FIGS. 33 and 34, the CPU 505 first reads the input port data stored in the input port register PI (step S201). The input port data read at this time may be stored in a start winning buffer provided in the game control buffer setting unit 595, for example. Then, it is determined whether or not the bit value in the bit number [1] of the input port data read in step S201 is “1” (step S202). In this embodiment, a wiring for transmitting the second start winning signal SS2 from the second start port switch 22B is connected to the input port P1 provided in the PIP 510, and the bit value in the bit number [1] of the input port data is set. By confirming, it is possible to specify whether or not the game ball is detected by the second start port switch 22B. When the second start winning signal SS2 is in the ON state, the bit value in the bit number [1] of the input port data is “1”.

  Therefore, when it is determined as “1” in Step S202 (Step S202; Yes), the second start winning determination which is the value of the second start winning determination counter provided in the game control counter setting unit 594 is performed. The count value is updated so as to be counted up, for example, by adding 1 (step S203). On the other hand, when it is determined as “0” in step S202 (step S202; No), the second start winning determination counter is cleared and the count value is initialized to “0”. (Step S204).

  After executing one of the processes in steps S203 and S204, it is determined whether or not the bit value in the bit number [0] of the input port data read in step S201 is “1” (step S205). In this embodiment, a wiring for transmitting the first start winning signal SS1 from the first start port switch 22A is connected to the input port P0 included in the PIP 510, and the bit value in the bit number [0] of the input port data is set. By confirming, it is possible to specify whether or not the game ball is detected by the first start port switch 22A. When the first start winning signal SS1 is on, the bit value at the bit number [0] of the input port data is “1”.

  Therefore, when it is determined as “1” in Step S205 (Step S205; Yes), the first start winning determination which is the value of the first starting winning determination counter provided in the game control counter setting unit 594 is performed. The count value is updated so as to be counted up, for example, by adding 1 (step S206). On the other hand, when it is determined as “0” in step S205 (step S205; No), the first start winning determination counter is cleared and the count value is initialized to “0”. (Step S207).

  After executing one of the processes in steps S206 and S207, it is determined whether or not the first start winning determination count value has reached a predetermined determination value (for example, “2”) predetermined as a winning determination value. (Step S208). At this time, if the first start winning determination count value has reached the winning determination value (step S208; Yes), whether or not the random number value is latched based on the value of the bit number [0] of the random number latch flag register. That is, it is determined whether or not numerical data has been taken into the random value register 559A (step S209). If numerical data has not been taken into the random value register 559A (step S209; No), the first start winning determination counter is cleared and the count value is initialized to “0” (step S210). If numerical data has been taken into the random value register 559A (step S209; Yes), the value of the start port buffer (start port buffer value) provided in the game control buffer setting unit 595 is set to “1” ( Step S211). Further, the first start winning determination counter is cleared and the count value is initialized to “0” (step S212).

  When the first start winning determination count value has not reached the winning determination value in step S208 (step S208; No), or in step S209, numerical data is not taken into the random value register 559A, and the first in step S210. When the winning determination counter is cleared, it is determined whether or not the second start winning determination count value has reached the winning determination value (step S213). At this time, if the second start winning determination count value does not reach the winning determination value (step S213; No), a predetermined time until the predetermined period after the release period ends is currently set. Regardless of the time, the predetermined initial value is set (step S216), and the start winning determination process is terminated.

  On the other hand, if the second start winning determination count value has reached the winning determination value (step S213; Yes), is the random number value latched based on the value of the bit number [1] of the random number latch flag register? It is determined whether or not numerical data is captured in the random value register 559B (step S214). If numerical data has not been taken into the random value register 559B (step S214; No), the second start winning determination counter is cleared, the count value is initialized to “0” (step S215), and the open period The predetermined time until the end of the predetermined period after the time is ended is set to a predetermined initial value (step S216), regardless of what time is currently set (step S216). The process ends.

  If numerical data is captured in the random value register 559B (step S214; Yes), an opening period in which the opening control in which the movable wing piece of the electric tulip constituting the ordinary variable winning ball apparatus 6B is in the inclined position is performed It is determined whether or not a predetermined period until a predetermined time elapses after the opening period ends (step S217). If it is an open period or a predetermined period, a predetermined time until the predetermined period after the open period ends is set to a time later than the currently set predetermined time by a predetermined time (step) S218). Thereafter, the start port buffer value is set to “2” (step S219). Further, the second start winning determination counter is cleared and the count value is initialized to “0” (step S220).

  If neither the open period nor the predetermined period is reached, the numerical data fetched in the random value register 559B is read and discarded without being stored as it is (step S231). Further, the second start winning determination counter is cleared and the count value is initialized to “0” (step S232). Then, for example, by outputting a predetermined error sound from the speakers 8L and 8R, the closing control is performed in which the movable wing piece of the electric tulip constituting the normally variable winning ball apparatus 6B is in the vertical position. The player and the surrounding area (especially, a store clerk of the game store) are informed of the occurrence of an error that has been detected by the 2 start port switch 22B as having entered the second start winning port (step S233). ). Then, the process proceeds to a predetermined error process.

  After executing one of the processes in steps S212 and S220, the CPU 505 reads the reserved storage number count value corresponding to the start port buffer value (step S221). For example, when the starting port buffer value is “1”, the value of the first reserved memory number counter (first reserved memory number count value) provided in the game control counter setting unit 594 is read, and the starting port buffer value is “ If “2”, the value of the second reserved memory number counter provided in the game control counter setting unit 594 (second reserved memory number count value) is read. Then, it is determined whether or not the read value in step S221 has reached a predetermined upper limit (eg, “4”) (step S222 in FIG. 34). At this time, if the read value in step S221 does not reach the upper limit value, the starting condition for starting the variable display of the special symbol or the decorative symbol is effectively established. For example, after it is determined in step S208 shown in FIG. 33 that the first start winning determination count value has reached the winning determination value, it is determined in step S222 that the read value has not reached the upper limit value. The first start condition for executing the special symbol game using the first special symbol by the one special symbol display device 4A and the variable display of the decorative symbol is established. In addition, when it is determined in step S222 that the read value has not reached the upper limit value after it is determined in step S213 that the second start winning determination count value has reached the winning determination value in step S213 shown in FIG. The second starting condition for executing the special symbol game using the second special symbol by the two special symbol display device 4B and the variable display of the decorative symbol is established.

  Thus, when the read value has not reached the upper limit value in step S222 (step S222; No), the reserved storage number count value corresponding to the start port buffer value is incremented by 1 (step S223). For example, when the starting port buffer value is “1”, 1 is added to the first reserved memory number count value, and when the starting port buffer value is “2”, 1 is added to the second reserved memory number count value.

  Following the processing of step S223, the CPU 505 sets the start data corresponding to the start port buffer value at the head of the empty area in the start data storage unit 591C and stores it (step S224). For example, when the start port buffer value is “1”, start data indicating “first” is set, and when the start port buffer value is “2”, start data indicating “second” is set. Then, the CPU 505 determines the random number value MR1 for determining the special figure display result, the random value MR2 for determining the big hit type, the random value MR3 for determining the reach, the random value MR4 for determining the variation pattern type, and the random value for determining the variation pattern. A random number setting process for storing MR5 as reserved data is executed (step S225). For example, the CPU 505 determines the free space in either the first special figure reservation storage unit 591A or the second special figure reservation storage unit 591B depending on whether the start port buffer value is “1” or “2”. First, numerical data indicating the random number value MR1 for determining the special figure display result is set based on the numerical data extracted from the random number circuit 509. Further, random number values MR2 to MR5 are extracted from a random counter provided in the game control counter setting unit 594, and similarly stored in the first special figure reservation storage unit 591A or the second special figure reservation storage unit 591B.

  After the random number setting process is executed in step S225, a setting for transmitting a start port winning designation command corresponding to the start port buffer value is performed (step S226). For example, when the start port buffer value is “1”, the storage address (first address) of the first start port winning designation command table in the ROM 506 is stored in the buffer area designated by the transmission command pointer in the transmission command buffer. On the other hand, when the starting port buffer value is “2”, the storage address (head address) of the second starting port winning designation command table in the ROM 506 is stored in the buffer area designated by the transmission command pointer in the transmission command buffer. The start opening winning designation command set in this way is performed from the main board 11 to the effect control board 12 by executing the main side communication control process in step S98 shown in FIG. 30 after the special symbol process process is completed, for example. Is transmitted.

  Further, the CPU 505 stores the storage address of the reserved memory number notification command table in the ROM 506 in the buffer area designated by the transmission command pointer in the transmission command buffer, etc. Is set to transmit (step S227). The first start opening winning designation command table is configured to include setting data for transmitting the first starting opening winning designation command and setting data for transmitting the reserved storage number notification command. When the second start opening winning designation command table is configured to include setting data for transmitting the second starting opening winning designation command and setting data for transmitting the pending storage number notification command As a process of steps S226 and S227, only the storage address of the command table corresponding to the starting port buffer value is stored in the buffer area of the transmission command buffer, out of the first starting port winning designation command table and the second starting port winning designation command table. do it. The reserved memory number notification command set in this way is performed by, for example, executing the main start communication designation process in step S98 shown in FIG. 30 after the special symbol process process is completed. 2 is transmitted from the main board 11 to the effect control board 12 following the start opening winning designation command.

  When the read value has reached the upper limit value in step S222 (step S222; Yes), after executing the process of step S227, it is determined whether the start port buffer value is “1” or “2”. Determination is made (step S228). At this time, if the start port buffer value is “1” (step S228; “1”), the start port buffer is cleared and the buffer value is initialized to “0” (step S229), and then FIG. The process proceeds to step S213 shown in FIG. On the other hand, when the starting port buffer value is “2” (step S228; “2”), the starting port buffer is cleared and the buffer value is initialized to “0” (step S230). The start winning determination process is terminated.

  In this embodiment, when both of the first start port switch 22A and the second start port switch 22B detect the start winning of a game ball that is effective at the same time, both processes are executed by processing executed within 2 milliseconds. A process based on the fact that the switch has detected a start winning of a valid game ball is executed. That is, when it is determined in step S208 shown in FIG. 33 that the first start winning determination count value has reached the winning determination value, the processes of steps S211, S212, and S221 shown in FIG. After executing the processing of steps S222 to S227 shown in FIG. 33, the processing of step S229 is executed in response to the fact that the start port buffer value is “1” in step S228, and then the processing of step S213 shown in FIG. Proceed to processing. When it is determined in step S213 that the second start winning determination count value has reached the winning determination value, the processes in steps S219 to S221 shown in FIG. 33 are executed, and then steps S222 to S227 shown in FIG. After executing the process, the process of step S230 is executed in response to the fact that the start port buffer value is “2” in step S228, and then the start winning determination process is terminated. Thereby, even when both the first start port switch 22A and the second start port switch 22B detect the start winning of the game balls that are effective at the same time, the processing based on the detection of both effective start winnings can be completed reliably.

  After the start winning determination process is executed in step S101 shown in FIG. 32, one of the processes in steps S110 to S120 is selected and executed according to the value of the special figure process flag.

  The special symbol normal process of step S110 is executed when the value of the special symbol process flag is “0”. In the special symbol normal process, the first special symbol display device 4A and the second special symbol are based on the presence / absence of reserved data stored in the first special symbol storage unit 591A and the second special symbol storage unit 591B. It is determined whether or not to start the special game using the display device 4B. Also, in the special symbol normal processing, whether the variable display result of the special symbol, the decorative symbol, the color symbol, etc. is set to “big hit” or “small hit” based on the numerical data indicating the random value MR1 for determining the special symbol display result. A determination is made whether or not. Further, in the special symbol normal process, in response to the variable display result of the special symbol in the special symbol game, the confirmed special symbol (big hit symbol, the special symbol game by the first special symbol display device 4A and the second special symbol display device 4B) Either a small hit symbol or a lost symbol) is set.

  The variation pattern setting process in step S111 is executed when the value of the special figure process flag is “1”. This variation pattern setting process includes a pre-determined result on whether or not the variable display result is “big hit” or “small hit”, a reach determination result on whether or not the variable display state of the decorative symbol is in the reach state, etc. The process includes determining a variation pattern type as one of a plurality of types, and determining a variation pattern as a plurality of types in accordance with the determination result of the variation pattern type.

  The special symbol variation process in step S112 is executed when the value of the special symbol process flag is “2”. This special symbol variation process includes a process for setting the special symbol to be varied in the first special symbol display device 4A and the second special symbol display device 4B, and an elapsed time after the special symbol starts to vary. It includes processing to measure For example, every time the special symbol variation process of step S112 is executed, the value (special diagram variation timer value) in the special diagram variation timer provided in the game control timer setting unit 593 is decremented or incremented by one. Regardless of whether the game is a special game using the first special symbol in the first special symbol display device 4A or a special game using the second special symbol in the second special symbol display device 4B, a common timer is used. The elapsed time is measured. Further, it is also determined whether or not the measured elapsed time has reached a special figure fluctuation time corresponding to the fluctuation pattern. As described above, the special symbol variation process in step S112 is performed in the special symbol variation in the special symbol game using the first special symbol in the first special symbol display device 4A or the second special symbol in the second special symbol display device 4B. This is a process for controlling the variation of the special symbol in the special figure game using the game according to a common processing routine. When the elapsed time since the start of the special symbol variation reaches the special symbol variation time, the value of the special symbol process flag is updated to “3”.

  The special symbol stop process in step S113 is executed when the value of the special symbol process flag is “3”. In the special symbol stop process, the first special symbol display device 4A or the second special symbol display device 4B stops the change of the special symbol, and the fixed special symbol which is the variable symbol display result is stopped and displayed. A process for setting is included. Then, a determination is made as to whether one of the big hit flag and the small hit flag provided in the game control flag setting unit 592 is on. If the big hit flag is on, the special process flag The value is updated to “4”, and when the small hit flag is on, the value of the special figure process flag is updated to “8”. When both the big hit flag and the small hit flag are off, the value of the special figure process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S114 is executed when the value of the special figure process flag is “4”. This pre-opening process for the big winning opening is a process for starting the execution of the round in the big winning gaming state and setting the opening for the big winning opening based on the fact that the variable display result is “big hit” Etc. are included. At this time, for example, an upper limit of a period during which the big prize opening is in an open state may be set corresponding to the setting of the maximum number of big prize opening times. As an example, when the maximum value of the number of times of winning the big winning opening is set to “15” corresponding to the 15 round big hit state, the upper limit of the period during which the big winning opening is opened is set to “29 seconds”. On the other hand, if the maximum value for the number of times a big winning opening is opened is set to “2” corresponding to the two round big hit state, the upper limit of the period during which the big winning opening is opened is set to “0.5 seconds”. Set to.

  The special winning opening releasing process in step S115 is executed when the value of the special figure process flag is “5”. This process during opening of the big winning opening is based on the process of measuring the elapsed time since the big winning opening is opened, the elapsed time measured, the number of game balls detected by the count switch 23, and the like. Processing for determining whether or not it is time to return the winning opening from the open state to the closed state is included. And when returning a special winning opening to a closed state, the process etc. which stop supply of the solenoid drive signal with respect to the solenoid for special prize opening doors should just be performed.

  The post-opening processing for the special winning opening in step S116 is executed when the value of the special figure process flag is “6”. The post-opening process for the big prize opening includes a process for determining whether or not the number of executions of the round in which the big prize opening is in an open state has reached the maximum number of open big prize openings, This includes a process for making a setting for transmitting an end designation command when hit.

  The big hit end process in step S117 is executed when the value of the special figure process flag is “7”. In the jackpot ending process, an ending effect as an effect operation for informing the end of the jackpot gaming state is executed by an effect electric component (effect device) such as the image display device 5, the speakers 8L and 8R, and the game effect lamp 9. A process of waiting until a waiting time corresponding to a period of time elapses, a process of performing various settings corresponding to the end of the big hit gaming state, and the like.

  The small hit pre-release process in step S118 is executed when the value of the special figure process flag is “8”. This pre-opening process for small hits is a setting for starting the execution of the variable winning action in the small hit game state and opening the big winning opening based on the fact that the variable display result is “small hit”, etc. The processing to perform is included. At this time, for example, the maximum value of the number of times that the big prize opening is opened is “0” because the variable display result is “small hit”, and the upper limit of the period during which the big prize opening is opened is set to “0. “5 seconds” may be set.

  The small hit releasing process in step S119 is executed when the value of the special figure process flag is “9”. In the small hit opening process, the process of measuring the elapsed time since the big prize opening is in the open state, and the timing for returning the big prize opening from the open state to the closed state based on the measured elapsed time, etc. The process etc. which determine whether or not were included are included. When returning the big prize opening to the closed state, a process of stopping the supply of the solenoid drive signal to the solenoid for the big prize opening door may be executed.

  The small hit end process in step S120 is executed when the value of the special figure process flag is “10”. In this small hit end processing, a period during which an effect operation for notifying the end of the small hit gaming state is executed by an electric component (effect device) for effects such as the image display device 5, the speakers 8L and 8R, and the game effect lamp 9 The process of waiting until the waiting time corresponding to the elapses is included. Here, when the small hit gaming state is finished, the state of the pachinko gaming machine 1 before the small hit gaming state is continued without changing the state of the probability change flag and the short time flag.

  FIG. 35 is a flowchart showing an example of the special symbol normal process executed in step S110 of FIG. In the special symbol normal process shown in FIG. 35, the CPU 505 first determines whether or not the total reserved memory count value stored in, for example, the game control counter setting unit 594 is “0”, that is, the first reserved memory count. It is determined whether or not the total reserved memory number that is the total value of the second reserved memory number is “0” (step S241). At this time, if the total pending storage number count value is other than “0” (step S241; No), start data is read from the start data storage unit 591C (step S242). Here, the start data stored in association with the hold number “1” in the start data storage unit 591C may be read.

  In this embodiment, the first start condition and the second start condition are not distinguished from each other, and it is assumed that the special game corresponding to the previously established start condition is executed sequentially. On the other hand, for example, on the condition that the second reserved memory number is not “0”, the special figure game using the second special figure is executed in preference to the special figure game using the first special figure. You may do it. In this case, for example, if the total reserved memory number count value is other than “0” in step S241, it is determined whether or not the second reserved memory number count value is “0”. If the second reserved storage number count value is “0”, the same processing as when the start data indicating “first” is read from the start data storage unit 591C is executed, while the second hold If the stored number count value is other than “0”, the same process as when the start data indicating “second” is read from the start data storage unit 591C may be executed. Alternatively, it is determined which of the first reserved memory number and the second reserved memory number is larger, and priority is given to a special game using a special symbol corresponding to the person with the larger reserved memory number. You may make it perform. In this case, for example, if the total reserved memory number count value is other than “0” in step S241, the first reserved memory number count value is compared with the second reserved memory number count value. When the first reserved storage number count value is larger, the same processing as when the start data indicating “first” is read from the start data storage unit 591C is executed, while the second hold When the stored number count value is larger, the same processing as when the start data indicating “second” is read from the start data storage unit 591C may be executed. At this time, if the first reserved memory number count value matches the second reserved memory number count value, the special game using the first special figure may be preferentially executed, or the second special figure may be executed. A special game using the game may be preferentially executed. In this way, by giving priority to the special figure game using the special symbol corresponding to the person with the larger number of reserved memories, it is possible to reduce the occurrence of invalid start winnings.

  Following the processing of step S242, for example, by subtracting 1 from the total reserved storage number count value, the total reserved storage number is updated to be decremented by 1, and the start data storage unit 591C determines from the hold number “1”. The storage contents of the start data stored in the lower entries (for example, entries corresponding to the holding numbers “2” to “8”) are shifted upward by one entry (step S243). Then, it is determined whether the start data read in step S242 is “first” or “second” (step S244).

  If it is determined in step S244 that the start data is “first” (step S244; first), a special game using the first special figure by the first special symbol display device 4A is started. In response to the establishment of the 1 start condition, the variable special figure designation buffer value stored in the game control buffer setting unit 595 is set to “1” (step S245). Further, it is determined whether or not the random number value is latched based on the value of the bit number [0] of the random number latch flag register, that is, whether or not numerical data is taken into the random value register 559A (step S246). If the numerical data is not taken into the random value register 559A (step S246; No), the process proceeds to step S251 as it is. If numerical data has been captured in the random value register 559A (step S246; Yes), the numerical data captured in the random value register 559A is read out and discarded without being stored as it is (step S247). Then, the process proceeds to step S251.

  On the other hand, when it is determined in step S244 that the start data is “second” (step S244; second), a special game using the second special figure by the second special symbol display device 4B is started. In response to the establishment of the second start condition, the variable special figure designation buffer value is set to “2” (step S248). Further, it is determined whether or not the random number value is latched based on the value of the bit number [1] of the random number latch flag register, that is, whether or not numerical data is taken into the random number value register 559B (step S249). If numerical data is not taken into the random value register 559B (step S249; No), the process proceeds to step S251 as it is. If numerical data has been captured in the random value register 559B (step S249; Yes), the numerical data captured in the random value register 559B is read out and discarded without being retained (step S250). Then, the process proceeds to step S251.

  In step S251, the hold data is read from the special figure hold storage unit corresponding to the start data read in step S242. For example, when the start data is “first”, the reserved data stored in association with the holding number “1” in the first special figure holding storage unit 591A is stored as a random value for determining the special figure display result. The numerical data indicating MR1 and the numerical data indicating the random value MR2 for determining the jackpot type are respectively read out. On the other hand, when the start data is “second”, the hold data stored in association with the hold number “1” in the second special figure hold storage unit 151B is used for special figure display result determination. The numerical data indicating the random number value MR1 and the numerical data indicating the random number value MR2 for determining the jackpot type are respectively read out.

  Subsequent to the process of step S251, the reserved memory count value corresponding to the start data is decremented by 1, and an entry lower than the hold number “1” (for example, the hold number “ The stored contents of the pending data stored in the entries corresponding to “2” to “4”) are shifted upward by one entry (step S252). For example, when the start data is “first”, the first reserved memory number count value is decremented by 1, and the storage contents of the reserved data in the first special figure reservation storage unit 591A are shifted upward by one entry. Let On the other hand, when the start data is “second”, the second reserved memory number count value is decremented by 1, and the stored contents of the reserved data in the second special figure reservation storage unit 591B are stored one entry at a time. Shift to the top.

  After that, select and set the special figure display result determination table according to the start data as the use table for determining whether the variable display result is “big hit” or “small hit” (Step S253). The CPU 505 refers to the special figure display result determination table set in this way, whereby the numerical data indicating the special figure display result determination random number MR1 read in step S251 matches the jackpot determination value data. Is determined (step S254).

  When the numerical data indicating the random value MR1 matches the big hit determination value data in step S254 (step S254; Yes), the big hit flag provided in the game control flag setting unit 592 is set to the on state (step S255). ). At this time, the jackpot type determination table 131 shown in FIG. 24 is selected and set as a use table for determining the jackpot type as one of a plurality of types (step S256). Then, based on the numerical data indicating the jackpot type determination random value MR2 read in step S251, the jackpot type is set to “normal”, “first” by referring to the jackpot type determination table 131 set in step S256. One of a plurality of types of “1 probability variation” to “third probability variation” and “surprising accuracy” is determined (step S257). When the variable special figure designation buffer value is set to “2” in the process of step S248, a random value MR2 for determining the big hit type is assigned to the big hit type of “surprise” in the big hit type determining table 131. As a result, the jackpot type is not determined to be “accurate”. Corresponding to the jackpot type determined in step S257, the jackpot type buffer value is set to any one of “00” to “04” (step S258).

  If the numerical data indicating the random value MR1 does not match the jackpot determination value data in step S254 (step S254; No), the numerical value indicating the random number value MR1 for determining the special figure display result read in step S251. It is determined whether or not the data matches the loss determination value data (step S259). At this time, if it does not coincide with the loss determination value data (step S259; No), the small hit flag is set to the on state as being matched with the small hit determination value data (step S260).

  After executing one of the processes of step S258 and step S260, or when matching with the loss determination value data in the process of step S259, corresponding to the determination result of the variable display result and the determination result of the jackpot type Then, a confirmed special symbol is set (step S261). As an example, when the numerical data indicating the random number value MR1 matches the loss determination value data in step S259, the loss pattern corresponding to the preliminary determination result indicating that the variable display result is “lost” The special symbol indicating the symbol “-” is set as the confirmed special symbol. On the other hand, if the numerical data indicating the random value MR1 matches the jackpot determination value data in step S254, “1”, “3” which become jackpot symbols according to the determination result of the jackpot type in step S257. , One of the special symbols indicating the number “7” is set as the confirmed special symbol. That is, according to the determination result that the jackpot type is “normal”, the special symbol indicating the number “3” that is the normal jackpot symbol is set as the confirmed special symbol. Further, according to the determination result that the big hit type is any one of “first probability variation” to “third probability variation”, the special symbol indicating the number “7” that becomes the probability variation big hit symbol is set as the confirmed special symbol. Further, according to the determination result that the big hit type is “surprise”, the special symbol indicating the number “1” that becomes the two round big hit symbol is set as the confirmed special symbol. Furthermore, when the numerical data indicating the random number MR1 does not match the loss determination value data in step S259, a small hit symbol is obtained corresponding to the preliminary determination result that the variable display result is “small hit”. The special symbol indicating the number “5” is set as the confirmed special symbol.

  After the confirmed special symbol is set in step S261, the value of the special symbol process flag is updated to “1” corresponding to the variation pattern setting process (step S262), and then the special symbol normal process is terminated. . If the total number of reserved memories is “0” in step S241 (step S241; Yes), a predetermined demo display setting is performed (step S263), and the special symbol normal process is terminated.

  Hereinafter, a specific operation example in the pachinko gaming machine 1 will be described. In the main board 11, the security check program 506A stored in the ROM 506 or the like is stored in the ROM 506 or the like when the initial power is supplied from the power board 10 (when power is turned on without a backup power source) or when the CPU 505 is restarted after a system reset occurs. Is read out and executed, the gaming control microcomputer 100 enters the security mode.

  At this time, as a process corresponding to the security check program 506A, for example, a security check process as shown in FIG. 26 is executed. Here, the security time when the game control microcomputer 100 is in the security mode is set in advance in the bit number [2-0] or the bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 506. Depending on the stored bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000” (step S2 shown in FIG. 26; No), the setting contents as shown in FIG. Correspondingly, in addition to the fixed time, any one of a plurality of extension times that can be selected in advance can be set as a time component included in the security time (step S4). If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00” (step S6; No), the short mode or the long mode as shown in FIG. 10C is supported. Then, a variable setting time that changes in a predetermined time range each time the initial setting process is executed based on system reset or power-on can be set as a time component included in the security time (step S8).

  Until the security time set in this way has elapsed (step S14; No), the execution of the game control main process by the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 may not be started during the period in which the game control microcomputer 100 is in the security mode. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, and the analysis result of the game control processing program By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent actions such as illegally generating a big hit gaming state.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the pachinko gaming machine 1. In this case, the extended time set in step S4 shown in FIG. 26 can be made different for each model of the pachinko gaming machine 1, and the operation start timing of the random number circuit 509 is determined from the operation start timing of the pachinko gaming machine 1. It becomes difficult to specify. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time set in step S8 is varied for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the pachinko gaming machine 1.

  FIG. 36 is a timing chart for explaining the operation of the random number circuit 509 built in the game control microcomputer 100 mounted on the main board 11. FIG. 36A shows the control clock CCLK generated by the control clock generation circuit 111 mounted on the main board 11. FIG. 36B shows the random number clock RCLK generated by the random number clock generation circuit 112. As shown in FIGS. 36A and 36B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCLK are different from each other. It does not become an integral multiple of the other oscillation frequency.

  As shown in FIG. 36B, the random number clock RCLK rises from a low level to a high level at timings T10, T11, T12,. The random number clock RCLK is supplied to the random number external clock terminal ERC of the game control microcomputer 100 and input to the clock terminal CK in the clock flip-flop 552 provided in the random number circuit 509 shown in FIG. The clock flip-flop 552 responds to the rising edge of the random number clock RCLK input to the clock terminal CK with the latch clock RC0 fed back from the negative phase output terminal (inverted output terminal) Q bar to the D input terminal. Are taken in (latched) and output as a random number update clock RGK from the positive phase output terminal (non-inverted output terminal) Q. As a result, the random number update clock RGK rises from the low level to the high level at the timings T10, T12, T14,..., As shown in FIG. The signal has an oscillation frequency. For example, if the oscillation frequency of the random number clock RCLK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Since the oscillation frequency of the random number clock RCLK is neither an integer multiple nor a fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK. Different frequency. The random number generation circuit 553 updates the numerical data in the count value permutation RCN in response to, for example, the rising edge of the random number update clock RGK. The random number sequence change circuit 555 changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553 based on the setting of the random number update rule by the random number sequence change setting circuit 556 as a random number sequence RSN. Output. Thus, the numerical data in the random number sequence RSN is updated in response to the rising edge of the random number update clock RGK, for example, as shown in FIG.

  The latch clock RC0 output from the clock flip-flop 552 is an inverted signal of the random number update clock RGK, the oscillation frequency thereof is the same as the oscillation frequency of the random number update clock RGK, and its phase is equal to the phase of the random number update clock RGK and π It differs by (= 180 °). The latch clock RC0 is branched into a latch clock RC1 and a latch clock RC2 at a branch point BR1. Therefore, for example, as shown in FIG. 36E, each of the latch clocks RC0, RC1, and RC2 becomes an oscillation signal whose signal state changes in a common cycle. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B.

  In response to the rising edge of the latch clock RC1, the latch flip-flop 557A receives the first start winning signal SS1 (actually the inversion of SS1) transmitted from the first start port switch 22A and supplied to the input port P0. Signal) is taken (latched) and output from the output terminal Q as a start winning latch signal SL1. Then, if the capturing method in the random number latch selector 558A is designated as signal input to the input port P0, the start winning latch signal SL1 is output as the random number latch signal LL1. Thereby, for example, the first start winning signal SS1 whose signal state changes between the off state (low level) and the on state (high level) at the timing shown in FIG. 36F is the timing at which the latch clock RC1 rises. After being taken into the latch flip-flop 557A at T11, T13, T15,..., The random number latch signal LL1 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. And output from the random number latch selector 558A. Here, the first start winning signal SS1 transmitted from the first start opening switch 22A is turned off when the start winning of the game ball at the first start winning opening formed by the normal winning ball apparatus 6A is detected. Change to ON state. The random number latch signal LL1 output from the latch flip-flop 557A via the random number latch selector 558A is supplied to the random number value register 559A serving as the random number value register R1D, and in the random number sequence RSN output from the random number sequence change circuit 555. Used to obtain numerical data. Thus, the latch flip-flop 557A and the random number latch selector 558A acquire numerical data as a random number value using the latch clock RC1 based on the detection of the start winning of the game ball at the first start winning opening. The random number latch signal LL1 is generated separately from the case where the start winning of the game ball at the second start winning opening is detected.

  In response to the rising edge of the latch clock RC2, the latch flip-flop 557B receives the second start winning signal SS2 (actually, the inversion of SS2) transmitted from the second start port switch 22B and supplied to the input port P1. Signal) is taken (latched) and output from the output terminal Q as a start winning latch signal SL2. Then, if the capturing method in the random number latch selector 558B is designated as signal input to the input port P1, the start winning latch signal SL2 is output as the random number latch signal LL2. Thus, for example, the second start winning signal SS2 whose signal state changes between the off state (low level) and the on state (high level) at the timing shown in FIG. 36I is the timing at which the latch clock RC2 rises. After being taken into the latch flip-flop 557B at T11, T13, T15,..., The random number latch signal LL2 whose signal state changes between the off state and the on state at timings T14 and T15 as shown in FIG. And output from the random number latch selector 558B. Here, the second start winning signal SS2 transmitted from the second start opening switch 22B is turned off when the start winning of the game ball at the second start winning opening formed by the normal variable winning ball apparatus 6B is detected. Changes from ON to ON. The random number latch signal LL2 output from the latch flip-flop 557B via the random number latch selector 558B is supplied to the random number value register 559B serving as the random number value register R2D, and the random number sequence RSN output from the random number sequence change circuit 555 Used to obtain numerical data. In this way, the latch flip-flop 557B and the random number latch selector 558B acquire numerical data as a random number value using the latch clock RC2 based on the detection of the start winning of the game ball at the second start winning opening. The random number latch signal LL2 is generated separately from the case where the start winning of the game ball at the first start winning opening is detected.

  The random value register 559A serving as the random value register R1D responds to the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 in response to the rising edge of the random number latch signal LL1 input from the random number latch selector 558A to the clock terminal. Then, the numerical data serving as stored data is updated (latched). The random value register 559B serving as the random value register R2D responds to the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 in response to the rising edge of the random number latch signal LL2 input from the random number latch selector 558B to the clock terminal. Then, the numerical data serving as stored data is updated (latched).

  For example, as shown in FIG. 36 (G), when a rising edge is generated at which the random number latch signal LL1 changes from the off state to the on state at timing T11, the random number sequence change circuit 555 outputs it at this timing T11. As shown in FIG. 36 (H), the numerical data in the random number sequence RSN is taken into the random value register R1D and acquired as numerical data that becomes a random value. As a result, in the random value register 559A serving as the random value register R1D, the numerical data used as the random number value based on the detection of the start winning of the game ball at the first start winning opening is used as the game at the second starting winning opening. It can be acquired and stored separately from the case where the starting winning of the ball is detected.

  Further, for example, as shown in FIG. 36 (J), when a rising edge occurs in which the random number latch signal LL2 changes from the OFF state to the ON state at timing T13, the random number sequence change circuit 555 starts at timing T13. As shown in FIG. 36 (K), the numerical data in the output random number sequence RSN is taken into the random value register R2D and acquired as numerical data that becomes a random value. As a result, the random value register 559B serving as the random value register R2D, based on the detection of the start winning of the game ball at the second start winning opening, converts the numerical data used as the random number value into the game at the first starting winning opening. It can be acquired and stored separately from the case where the start winning of the ball is detected.

  Thus, the random value register 559A responds to the rising edge of the start winning latch signal SL1 generated by the latch flip-flop 557A using the latch clock RC1 and the random number latch signal LL1 output from the random number latch selector 558A. Numerical data in the random value RSN is acquired. The numerical data stored in the random number value register 559A is determined in step S208 shown in FIG. 33 when the first start winning determination count value has reached the winning determination value (step S208; Yes). This is read out by the CPU 505 based on the detection of a valid winning game ball winning by the mouth switch 22A. At this time, in steps S357 and S358, the random number value MR1 for determining the special figure display result and the random value MR6 for determining the addition value are set using the numerical data read from the random value register 559A.

  In addition, the random value register 559B responds to the start winning latch signal SL2 generated by the latch flip-flop 557B using the latch clock RC2 and the rising edge of the random number latch signal LL2 output from the random number latch selector 558B. Numerical data in the random number sequence RSN is acquired. The numerical data stored in the random value register 559B is determined to have reached the second start winning determination count value in step S213 shown in FIG. 33 (step S213; Yes). This is read out by the CPU 505 based on the detection of a valid game ball start winning by the mouth switch 22B. At this time, in steps S357 and S358, the random number value MR1 for determining the special figure display result and the random value MR6 for determining the addition value are set using the numerical data read from the random number value register 559B.

  As described above, in the random number circuit 509, the clock flip-flop 552, the random number generation circuit 553, the random number sequence change circuit 555, and the like acquire numerical data that becomes a random number value based on the start winning of the game ball at the first start winning opening. Based on the combination of the latch flip-flop 557A, the random number latch selector 558A, and the random value register 559A configured as described above, and numerical data that becomes a random value based on the starting winning of the game ball at the second starting winning opening is obtained. The latch flip-flop 557B, the random number latch selector 558B, and the combination of the random value register 559B are shared. Therefore, the random number update clock RGK output from the clock flip-flop 552 and supplied to the random number generation circuit 553 and used for updating the numerical data in the count value permutation RCN and the numerical data in the random number sequence RSN is the first starting prize opening. A common random number update configuration for acquiring numerical data that is a random value based on a starting winning of a game ball and a configuration that acquires numerical data that is a random value based on a starting winning of a gaming ball at the second starting winning opening This is a clock signal.

  When it is determined in step S14 shown in FIG. 26 that the security time has elapsed (step S14; Yes), the CPU 505 reads the user program stored in the ROM 506, and the game control main process as shown in FIG. Executed. Then, for example, a random number circuit setting process as shown in FIG. 28 is executed as the setting process in step S33. In this case, the random number circuit 509 starts the operation of generating numerical data to be a random value based on the setting in the random number circuit setting process by the CPU 505. After the random number value generation operation by the random number circuit 509 is started in this way, the process of step S35 is repeatedly executed until the ON operation of the game start switch 31 installed on the main board 11 is detected, and the process of step S40 is performed. Is not set to enable interrupts. Therefore, even after the update operation of the numerical data by the random number circuit 509 is started, until the ON operation of the game start switch 31 is detected, for example, a pachinko game such as a game control timer interrupt process shown in FIG. The game control process for controlling the progress of the game in the machine 1 is not started. This makes it difficult to specify the operation start timing of the random number circuit 509 and the update operation of the numerical data from the start timing of the game control process, and aiming based on the analysis result of the game control process program, so-called “hanging board” , And an illegal signal is input at a predetermined timing, so that an action such as illegally generating a big hit gaming state can be surely prevented.

  If the bit value in the bit number [0] of the second random number initial setting KRS2 as shown in FIG. 9B is set to “1”, the random number circuit 509 generates it by the process of step S55 shown in FIG. The start value of the numerical data to be a random value to be changed can be changed at every system reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify numerical data read from the random value register 559A and the random value register 559B included in the random number circuit 509. It is possible to reliably prevent actions such as illegally generating a big hit gaming state by aiming based on the analysis result of the control processing program or inputting a fraud signal at a predetermined timing by connecting a so-called `` hanging board '' it can.

  As described above, in the pachinko gaming machine 1 in this embodiment, when the random number latch flag data RDFM0 is “1” in the random number circuit 509, that is, when the numerical data is taken into the random number value register R1D, a new random number is generated. Even when a numerical value capture request is generated, new numerical data is not captured in the random value register R1D. In such a state, the numerical data in the random value register R1D is read and the random number latch is read. Until the flag data RDFM0 is cleared, new numerical data cannot be taken into the random value register R1D.

  For this reason, the numerical data is latched when the game ball has won the first start winning opening 6A, stored in the random value register R1D, and thereafter, until the stored numerical data is read, the random number latch flag data RDFM0. Is in the “1” state, the stored numerical data is retained, and even if the game start signal SS1 is input during that time, the new numerical data is not overwritten. Thus, even if noise is applied to the signal line of the detection signal of the first start port switch 22A due to static electricity or the like, the numerical data does not change. The jackpot lottery is not performed using numerical data different from the numerical data latched at the timing when the game ball is won.

  Note that the configuration in which new numerical data is not captured in the random value register R1D while the numerical data is captured in the random value register R1D may be configured to prohibit latching of the new numerical data. In addition, although new numerical data is latched, the writing to the random value register R1D may be prohibited.

  In addition, the electric tulip type character that forms the normally variable winning ball apparatus 6B is the second start by changing the movable wing piece from the vertical position to the inclined position for a certain period when the big game is a big hit. The release control that enables the game ball to enter the winning opening is performed. If the second start port switch 22B detects that the game ball has entered the second start winning port while this release control is being performed, the second start condition is satisfied (however, the second start condition is satisfied). (Except when the special figure storage unit 591B is already in the state of four reservations). When the closing control is performed in which the movable wing piece of the electric tulip-shaped accessory forming the normal variable winning ball apparatus 6B is in the vertical position, the game ball can essentially enter the second starting winning hole. Therefore, it is prohibited to establish the second start condition (however, as described later, until the predetermined period elapses from the end of the opening control, the establishment of the second starting condition is prohibited even if the closing control is started). Not)

  However, even during the closing control of the electric tulip-shaped accessory forming the ordinary variable winning ball apparatus 6B, for example, a game ball enters due to noise on the signal line of the second start port switch 22B. If it is mistakenly detected (in this case, the second start condition is not satisfied), numerical data is latched in the random value register R2D. The numerical data latched at this time is also held in the random value register R2D unless it is read out. After that, when the game is won at the second start winning opening by controlling the opening of the electric tulip-shaped accessory that forms the normal variable winning ball apparatus 6B by winning the normal game, the start condition is satisfied. However, there arises a new problem that the big hit lottery is performed by the numerical data latched at a timing different from the winning timing of the game ball to the second starting winning opening that satisfies the second starting condition.

  On the other hand, in the pachinko gaming machine 1 according to this embodiment, the second starting condition is established in the first place while the closing control of the electric tulip-type accessory forming the normally variable winning ball apparatus 6B is being performed. If numerical data is latched in the random value register R2D when it is not obtained, the numerical data in the random value register R2D is read out as a dummy. As a result, the random number latch flag is cleared, and new numerical data can be taken in. In such a case, since the numerical data of the random number register R2D is read as a dummy, the numerical data latched at a timing different from the winning timing of the game ball to the second starting winning opening 6B that satisfies the starting condition. A lottery lottery will not be performed.

  By the way, even when the game ball wins the second start winning opening just before the opening control of the electric tulip-shaped accessory forming the ordinary variable winning ball apparatus 6B is completed, for example, a ball clogging occurs. In some cases, this is detected by the second start port switch 22B after the opening control has ended. In the pachinko gaming machine 1 according to this embodiment, even after the opening control of the electric tulip-shaped accessory forming the normally variable winning ball apparatus 6B is completed, the second start opening switch is used during a predetermined period thereafter. When the winning of the game ball is detected by 22B, the numerical data latched in the random value register R2D is not read as a dummy, but is read as usual and stored as start data (however, (Excluding the case where the 4th reserved memory has already been stored in the second special figure reserved storage unit 591B). Therefore, in such a case, the process can be performed assuming that the second start condition is effectively satisfied.

  Furthermore, when two game balls win the second start winning opening at the same time immediately before the opening control of the electric tulip-shaped accessory forming the normally variable winning ball apparatus 6B is finished, clogging is likely to occur. Then, when a winning of the first game ball among the two game balls is detected by the second start port switch 22B in a predetermined period after the release control is finished, the predetermined period is extended. If the winning of the second game ball is detected by the second start port switch 22B by the extended predetermined period, the numerical data extracted for the detection by the second start port switch 22B of each game ball Are read out as usual and stored as start data (except for the case where the four special storage units 591B are already in a state of four storages). Therefore, in such a case, the process can be performed assuming that the second start condition is effectively satisfied by any of the two game balls winning.

  On the other hand, in the period during which the closing control of the electric tulip-shaped accessory forming the ordinary variable winning ball apparatus 6B is performed, even during a predetermined period after the opening control ends (in the case of being extended, the extended period) If there is an erroneous detection of the second start port switch 22B in the absence period, numerical data in the random value register R2D is read out as a dummy, and error notification is performed by outputting sound from the speakers 8L and 8R. The fact that the second start port switch 22B erroneously detected the winning of the game ball during such a period may mean that an illegal act such as mixing noise into the signal line of the second start port switch 22B was performed. high. By performing error notification when the second start port switch 22B erroneously detects a winning of a game ball during such a period, it is possible to prevent such fraud.

  Further, in the state where the numerical data is taken into the random value register R1D, a configuration is adopted in which the stored numerical data is held until the stored numerical data is read. In this case, If the starting condition is not satisfied even if a game ball wins in the first start winning opening 6A, for example, in the state where four reserved memories are already stored in the first special figure holding storage unit 591A, When the game ball wins, numerical data is latched in the random value register R1D. The numerical data latched at this time is also held in the random value register R1D unless it is read out. After that, when the special figure game is ended and a new special figure game is started, when the reserved ball in the first special figure reservation storage unit 591A is decremented by one, the game ball wins the first start winning opening 6A. In this case, the start condition is satisfied, but a big win lottery is performed based on numerical data latched at a timing different from the winning timing of the game ball to the first start winning opening 6A that satisfies the start condition. Will cause serious problems.

  On the other hand, in the pachinko gaming machine 1 according to this embodiment, numerical data is stored in the random number value register R1D at the time when a new special figure game is started based on the hold storage of the first special figure hold storage unit 591A. Is latched, that is, whether the random number latch flag is set, and if the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D is read as a dummy. It has become. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, numerical data is stored in the random value register R1D by winning a game ball in the first start winning opening 6A in a state where four reservation memories are already stored in the first special figure reservation storage unit 591A, and the state Even if is held, a new special game is started and the holding memory becomes empty, and at the same time, the newly latched numerical data can be stored in the random value register R1D. As a result, the numerical data held in the random number register R1D in the state where the holding memory is full, that is, the game ball winning timing to the first starting winning opening 6A that satisfies the starting condition is latched at a timing different from the timing. A big hit lottery is not performed using numerical data.

  The above-described effects are that the random value register R1D, the random value register R2D, the random number latch flag data RDFM0, the random number latch flag data RDFM1, the first start winning port 6A and the first starting port switch 22A, and the second starting winning port 6B. The same occurs when the second start port switch 22B and the first special figure reservation storage unit 591A are read as the second special figure reservation storage unit 591B.

  Further, in the game control main process of FIG. 27, after it is determined in step S35 that the game start switch 31 has been turned on, numerical data is latched in the random value registers R1D and R2D before the interrupt is permitted in step S40. Whether the random number latch flag is set, and if the numerical data is latched in the random number registers R1D and R2D, the numerical data in the random number registers R1D and R2D is used as a dummy. It is designed to read. Generally, when the power is turned on or the system is reset, the power supply voltage supplied from the power supply board 10 is also unstable, and erroneous detection of the first start winning port switch 22A and the second start port switch 22B is likely to occur. Although the game ball has not won the first start winning opening 6A or the second starting winning opening 6B, it is likely that the numerical data is latched in the random value registers R1D and R2D. In such a case, since the numerical data of the random number registers R1D and R2D are read in dummy, the winning timing of the game balls to the first start winning port 6A and the second starting winning port 6B that satisfy the start condition The big hit lottery is not performed using numerical data latched at different timings.

  In addition, by setting the bit value in the bit number [4-3] of the security time setting KSES to a value other than “00”, the initial setting process is executed every time the system is reset or the power is turned on. The variable setting time that changes can be set as a time component included in the security time. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, and the analysis result of the game control processing program By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent actions such as illegally generating a big hit gaming state.

  Also, by setting the bit value in the bit number [2-0] of the security time setting KSES to a value other than “000”, any one of a plurality of extension times that can be selected in advance in addition to the fixed time is set as the security time. It can be set as an included time component. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, and the analysis result of the game control processing program By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent actions such as illegally generating a big hit gaming state.

  In the random number circuit 509 built in or externally attached to the game control microcomputer 100, a latch flip-flop 557B, a random number latch selector 558B, and a random number value are obtained by a combination of the latch flip-flop 557A, the random number latch selector 558A, and the random value register 559A. Separately from the combination of the registers 559B, the numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 is captured and stored so as to update the numerical data serving as the random number value. Thus, even when a game ball enters a plurality of start areas, such as the first and second start winning openings, and a start win occurs, numerical data that is an accurate random number value can be acquired. The clock flip-flop 552, the random number generation circuit 553, the random number sequence change circuit 555, and the like include a latch flip-flop 557A, a random number latch selector 558A, a random value register 559A, a latch flip-flop 557B, and a random number latch selector 558B. The random number update clock RGK used for updating the count value permutation RCN and the random number sequence RSN by being supplied to the random number generation circuit 553 is shared with each combination of the random number value register 559B and the random number value register 559B. This is a common random number update clock signal. Thereby, the circuit configuration in the random number circuit 509 can be simplified, and the manufacturing cost of the pachinko gaming machine 1 can be reduced. The latch flip-flops 557A and 557B are latches whose signal states change at a common cycle by branching the latch clock RC0 generated by the common clock flip-flop 552 at the branch point BR1. Using the clocks RC1 and RC2, the start winning latch signal SL1 and the starting winning latch signal SL2 for generating numerical data as random numbers are generated. This can also simplify the circuit configuration of the random number circuit 509 and reduce the manufacturing cost of the pachinko gaming machine 1.

  Further, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other. The oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. In this way, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. From the operation timing of the CPU 505, the random number circuit 509 generates the random number generation circuit 553 and the random number sequence change circuit 555. It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of the numerical data serving as the random number value in the random number circuit 509 from the operation timing of the CPU 505. Also, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. In this way, synchronization between the control clock CCLK and the internal system clock SCLK and the latch clocks RC1 and RC2 is prevented, and the random number circuit 509 takes in numeric data as a random value from the operation timing of the CPU 505. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 505.

  The CPU 505 built in the game control microcomputer 100 executes, for example, a random number circuit setting process as shown in FIG. 28 as the setting process in step S33 shown in FIG. Until the game start switch 31 installed on the main board 11 is detected to be turned on, the process of step S35 is repeatedly executed to control the progress of the game in the pachinko gaming machine 1. The execution of the game control process is not started. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data update operation from the start timing of the game control process. Therefore, it is possible to reliably prevent aiming based on the result of analyzing the start timing of the game control process and the input of an illegal signal due to connection of a so-called “hanging board”. When the random number circuit 509 is externally attached to the game control microcomputer 100, for example, the random number circuit 509 performs program management independently of the processing in the CPU 505 before the CPU 505 executes the processing in step S35. A random number generation operation may be started after initial setting based on the storage data of the area.

  In the random number circuit 509 built in or externally attached to the game control microcomputer 100, the random number generation circuit 553 corresponds to the bit value [0] of the second random number initial setting KRS2 being “1”. The start value of numerical data in the count value permutation RCN output from the random number sequence RSN and the random number sequence RSN output from the random number sequence change circuit 555 can be changed at each system reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A and the random value register 559B included in the random number circuit 509. Aiming based on the analysis result of the control processing program or the input of an illegal signal due to the connection of a so-called “hanging board” can be surely prevented.

  In the external bus interface 501 provided in the game control microcomputer 100, the internal resource access control circuit 501A allows external data other than the internal circuit such as the CPU 505 to externally read the internal data of the game control microcomputer 100 such as data stored in the ROM 506. Limited. Thereby, it is possible to prevent a game control processing program such as a game control user program stored in the ROM 506 from being read from the outside of the game control microcomputer 100 and provided for analysis or the like. Further, it is possible to reliably prevent aiming based on the analysis result of the game control processing program and input of an illegal signal due to connection of a so-called “hanging board”.

  In the random number circuit 509 built in or externally attached to the game control microcomputer 100, when the frequency monitoring circuit 551 detects a frequency abnormality in the random number clock RCLK, the random number circuit 509 stores the bit number [4] in the internal information register CIF. The bit value of the internal information data CIF4 is set to “1”. Then, the CPU 505 determines that the number of times that the read value of the internal information data CIF4 is continuously determined to be “1” in step S63 shown in FIG. 29 has reached the clock abnormality determination value in step S65, for example. When it is determined that an abnormality has occurred in the operation state of the random number circuit 509. Thereby, it is possible to reliably prevent an illegal act by inputting an illegal signal as the random number clock RCLK.

  The CPU 505 incorporated in the game control microcomputer 100 repeats the process of step S71 shown in FIG. 29, for example, to the random number value fetch designation register RDLT corresponding to the output of the latch signal to the random number circuit 509. The bit value “1” is written, and the numerical data stored in the random value register 559A and the random value register 559B is read a plurality of times. Then, all the bits of the numerical data read out by executing the processes of steps S72 to S74 are monitored, and an abnormality has occurred in the operation state of the random number circuit 509 in step S76 based on the presence or absence of bit data that does not change. It is determined whether or not. As a result, it is possible to reliably and easily detect that an abnormality has occurred in the operating state of the random number circuit 509 and prevent fraud.

  In the random number circuit 509 built in or externally attached to the gaming control microcomputer 100, when the first winning opening switch 22A detects the starting winning of the gaming ball at the first starting winning opening formed by the normal winning ball apparatus 6A. In addition, the combination of the latch flip-flop 557A, the random number latch selector 558A, and the random number value register 559A captures the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 so as to update the numerical data serving as the random number value. Remember me. On the other hand, when the starting winning of the game ball at the second starting winning opening formed by the normal variable winning ball apparatus 6B is detected by the second starting opening switch 22B, the latch flip-flop 557B, the random number latch selector 558B, The numerical value data in the random number sequence RSN output from the random number sequence change circuit 555 is captured and stored so that the numerical value data to be the random number value is updated by the combination of the numerical value registers 559B. As a result, even when a game ball enters (start winning prize) in both the first starting winning opening and the second starting winning opening within a short time, the random number value acquired corresponding to one starting win is It is possible to reliably prevent the inconvenience of being used as a random value corresponding to the starting prize.

  The CPU 505 incorporated in the game control microcomputer 100, in step S256, when the numerical data indicating the random value MR1 for determining the special figure display result matches the jackpot determination value data in step S254 shown in FIG. After the jackpot type determination table 131 shown in FIG. 24 is set as a usage table, the jackpot type is determined as one of a plurality of types in step S257. In the jackpot type determination table 131, any one of the jackpot types is selected based on the fact that the first start condition for starting the special game using the first special figure by the first special symbol display device 4A is satisfied. And determining whether the jackpot type is one of a plurality of types based on the fact that the second start condition for starting the special figure game using the second special figure by the second special symbol display device 4B is satisfied. The table data is configured so that the rate at which the big hit type is determined to be “accurate” differs depending on the case of determination. Thereby, the player's expectation for being controlled to the two round big hit state according to which one of the first start condition and the second start condition is satisfied can be made different, and the game entertainment can be improved. In particular, when the second start condition is satisfied, the big hit type is not determined to be “surprising accuracy”, so that the big start winning opening is easily controlled in the wide open state such as the probability changing state or the short time state. It is possible to prevent the gaming interests from deteriorating when the type is “accurate”, and it is possible to increase the frequency at which award balls are paid out in the probability variation state or the short time state.

  For example, a clear switch 304 as shown in FIG. When the CPU 505 of the game control microcomputer 100 determines that the clear switch 304 is turned on in step S27 shown in FIG. 27, the CPU 505 executes the processing of step S31 and step S32 to thereby execute the random number circuit 509. The game control including the operation state is initialized. Then, the game start switch 31 is installed on the main board 11 as shown in FIG. 2, for example, to initialize the operation state of the random number circuit 509 and start the execution of the game control processing program. Since it is required to turn on both the clear switch 304 installed on the main board 11 and the game start switch 31 installed on the main board 11, it is possible to prevent fraudulent acts such as aiming.

  The random number circuit 509 built in or externally attached to the game control microcomputer 100 is, for example, the step shown in FIG. 28 by the CPU 505 when the bit value in the bit number [0] of the second random number initial setting KRS2 is “1”. Corresponding to the execution of the process of S55, etc., the start value of the numerical data that becomes a random value is changed every time the system is reset. At this time, for example, a start value that is changed every time the system is reset may be determined by using a count value of a free-run counter built in the game control microcomputer 100. As a result, the initial value can be determined by using different initial value determination data depending on the timing of system reset or the like, and illegal acts due to shooting or the like can be prevented.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, any one of the opening period in which the opening control in which the movable wing piece of the electric tulip constituting the ordinary variable winning ball apparatus 6B is in the inclined position and the predetermined period after the opening period ends is performed. The numerical data that is output to the random number value register 559B when the detection signal of the second start port switch 22B is output when it is not the period is immediately read and discarded when the numerical data is acquired. It was. Of course, if the goal is to make a big lottery using numerical data fetched into the random value register 559B at the timing when the second start condition is satisfied, the second start condition is prohibited from being satisfied at the latest. The numerical data captured in the random value register 559B may be read out until the electric tulip-shaped accessory constituting the ordinary variable winning ball apparatus 6B to be released is next controlled to be released. That is, the numerical data fetched into the random number value register 559B when it is not any of the opening period and the predetermined period after the opening period ends is obtained by outputting the detection signal of the second start port switch 22B. It can be read and discarded at any timing from when the “T” is taken until the electric tulip-shaped accessory constituting the normally variable winning ball apparatus 6B is controlled to be opened next.

  In the above embodiment, when the game ball wins the first start winning opening 6A or the second start winning opening 6B and the start condition is established based on this, the first start winning opening 6A or the second start winning prize is obtained. The numerical data (random number) itself captured by winning the mouth 6B is stored in the first special figure storage unit 591A or the second special figure storage unit 591B. Then, the jackpot lottery or the jackpot type lottery is executed based on the random numbers stored in the first special figure storage unit 591A or the second special figure reservation storage unit 591B when starting the variable symbol display of the special symbol and the decorative symbol. I was supposed to do. On the other hand, when the game ball wins the first start winning opening 6A or the second start winning opening 6B and the start condition is established based on this, the game ball enters the first start winning opening 6A or the second start winning opening 6B. A jackpot lottery or a jackpot type lottery may also be performed based on the random number captured by winning, and the lottery result may be stored in the first special figure storage unit 591A or the second special figure reservation storage unit 591B. .

  In the above-described embodiment, the extension time set in step S4 shown in FIG. 26 corresponds to the bit value in the bit number [2-0] of the security time setting KSES, and a plurality of extension times that can be selected in advance. As described above, it has been described that this extended time is not changed at every system reset. However, the present invention is not limited to this. For example, the extension time added to the fixed time is determined as one of a plurality of extension times for each system reset by the setting in the user program stored in the ROM 506. May be. In this case, the extension time set in step S4 is defined to be longer than the longest variable setting time that can be set in step S8. Then, after a rough extension time is determined in step S4, a detailed extension time may be determined in step S8. As a result, the security time for entering the security mode when the power of the pachinko gaming machine 1 is turned on or when the system is reset can be greatly changed every time the system is reset. It becomes more difficult to specify the start timing and the numerical data to be updated.

  Further, for example, the extended time set in step S4 shown in FIG. 26 may be determined using an ID number assigned to each chip constituting the game control microcomputer 100. As an example, an extension time corresponding to the calculated value is executed by executing a part or all of an operation for performing a predetermined scramble process on the ID number and an operation such as addition / subtraction / multiplication / division using the ID number. May be set. In this case, the extension time may be randomly determined for each system reset, for example, by changing an arithmetic expression used for determining the extension time for each system reset. Furthermore, the count value of the free run counter, the ID number, and the like, for example, the arithmetic expression for determining the extension time using the ID number is determined corresponding to the count value of the free run counter stored at the time of system reset. The extended time may be determined randomly at each system reset by using a combination of the above. In addition, when changing the start value of the random number generated by the random number circuit 509 at each system reset, the start value of the random number can be changed by using a combination of the count value of the free-run counter and the ID number. You may decide.

  In the above embodiment, the random number clock generation circuit 112 provided outside the game control microcomputer 100 has an oscillation frequency different from the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111. It has been described that the random number clock RCLK is generated and supplied to the random number circuit 509. However, the present invention is not limited to this, and the clock signal supplied to the CPU 505 of the game control microcomputer 100 and the clock signal supplied to the random number circuit 509 are included in a common clock generation circuit. May be generated using the oscillation signal generated by the above. In this case, for example, a frequency divider for generating the random number clock RCLK and the control clock CCLK is provided, and the latch clocks RC0, RC1, RC2 are synchronized with the control clock CCLK or the internal system clock SCLK. What is necessary is just to set the frequency division ratio etc. in each frequency divider so that it may become difficult to produce. The control clock generation circuit 111 and the random number clock generation circuit 112 may be provided in whole or in part inside the game control microcomputer 100 or outside the game control microcomputer 100. May be.

  In the above embodiment, the random number circuit 509 is supplied with the random number clock RCLK generated by the random number clock generation circuit 112, and the random number update clock RGK and the latch clock RC0 are generated by the clock flip-flop 552. As explained. However, the present invention is not limited to this, and an oscillation signal serving as the random number update clock RGK or the latch clock RC0 may be generated outside the random number circuit 509, such as the random number clock generation circuit 112, for example. Alternatively, a circuit for generating the random number update clock RGK and a circuit for generating the latch clock RC0 may be separately provided in the random number circuit 509. As an example, while generating a random number update clock RGK by a flip-flop similar to the clock flip-flop 552, an inversion circuit for inverting the signal state of the random number update clock RGK is provided, and a signal output from the inversion circuit is latched. It may be used as the clock RC0.

  In the above embodiment, the clear switch 304 is installed on the power supply board 10, and the game start switch 31 is installed on the main board 11 separately from the clear switch 304. However, the present invention is not limited to this. For example, one of the power supply board 10 and the main board 11 may be provided with one switch that serves both as the clear switch 304 and the game start switch 31. As a result, for example, even when an illegal act such as fixing the game start switch 31 with a tape is fixed, the clear switch 304 is simultaneously operated to clear (initialize) the control contents. It is possible to prevent cheating by. However, in the above embodiment, the security time for entering the security mode can be changed by setting the extension time in step S4 shown in FIG. 26 or setting the variable setting time in step S8. When the clear switch 304 and the game start switch 31 are not used together, even if an illegal act is performed on the game start switch 31, the operation start timing of the random number circuit 509 or the random number by software is determined from the operation start timing of the pachinko gaming machine 1. It is difficult to specify the start timing of the update operation, and the effect of preventing fraudulent acts such as aiming is sufficiently high.

  In the above embodiment, when setting random values used in the main board 11 such as numerical data indicating the random number value MR1 for determining the special figure display result and numerical data indicating the random value MR6 for determining the added value, It explained as what performs processing by. However, the present invention is not limited to this. For example, processing by software may be performed when setting a random value used in a sub-side control board such as the effect control board 12. As an example, the CPU of the effect control microcomputer 120 mounted on the effect control board 12 executes a random number value used to determine the final stop symbol that becomes the final decorative symbol in the variable display of the decorative symbol, or the notice effect. The random value used for determining whether or not may be set by performing processing by software.

  In the above embodiment, the external reading of the internal data of the game control microcomputer 100 such as all or part of the data stored in the ROM 506 is limited by the internal resource access control circuit 501A provided in the external bus interface 501. did. However, the present invention is not limited to this. For example, the connection terminal for externally reading out the data stored in the ROM 506 by the game control microcomputer 100 is sealed so that the external device cannot be connected to the provider of the pachinko gaming machine 1. It may be possible to limit external reading of the ROM 506 by stopping it.

  In the embodiment described above, the first start winning opening formed by the normal winning ball apparatus 6A and the second starting winning opening formed by the normal variable winning ball apparatus 6B are described as being provided as a plurality of start areas. However, the present invention is not limited to this, and a plurality of starting regions such as three or more may be provided. In this case, a start condition for executing a special game using different special symbols may be established based on the detection of a start winning game ball in each start area. Or, for example, a special game using the same special symbol is executed based on the detection of a start winning game ball in a part (at least two) of the starting areas of three or more starting areas. The starting condition for doing so may be satisfied. In addition, even if a start winning of a game ball is detected in any start area among a plurality of start areas, a special game using a common (or one set) special symbol is executed. The start condition may be satisfied. In this case, the start condition for starting the special game may be established in the same order as the order in which the start winnings of the game balls are detected in the plurality of start areas. Alternatively, a priority is given to a plurality of start areas, and a start condition for starting a special game based on detection of a start winning game ball in a start area having a high priority is set as a start area having a low priority. The starting condition based on the detection of the start winning of the game ball may be established with priority.

  In the above-described embodiment, the small hit game state is controlled based on the fact that the variable display result is “small hit”, and the game state is not changed after the small hit game state ends. On the other hand, when the variable display result is “big hit”, it is controlled to the two round big hit state based on the fact that the big hit type becomes “surprise”, and after the two round big hit state is finished, it is controlled to the positive change state. Explained as being. However, the present invention is not limited to this, and instead of or in addition to the case where the big hit type is “accurate” or the variable display result is “small hit”, A case of “suddenly normal” may be provided. As an example, “suddenly short time” and “suddenly normal” are included in the jackpot type when the variable display result is “big jackpot”. In this case, the jackpot type determination table 131 includes table data for assigning the random number MR2 for determining the big hit type to the “suddenly short” or “sudden normal” big hit types in accordance with the fluctuation special figure designation buffer value. What is necessary is just to be comprised. When the variable display result is “big hit” and the big hit type is “suddenly short”, the two round big hit state is controlled in the same way as the big hit type is “surprise”, and the two round big hit state ends. After that, unlike the case where the big hit type is “accuracy”, it is controlled to the short time state. On the other hand, when the variable display result is “big hit”, when the big hit type is “suddenly normal”, the two round big hit state is controlled in the same way as when the big hit type is “surprise”, and the two round big hit state ends. After that, unlike the case where the jackpot type is “surprise”, the normal state is controlled. Thereby, a player's expectation with respect to the gaming state controlled after the end of the two round big hit state can be enhanced, and the gaming interest can be improved.

  In the above-described embodiment, it has been described that the game state such as the probability change state or the time-short state can be controlled after the big hit gaming state based on the variable display result being “big hit”. In the probability variation state and the short-time state, it is described that the control that is advantageous to the player is performed by increasing the possibility of the game ball entering the second start winning opening and easily establishing the second start condition. . However, the present invention is not limited to this. For example, in the probability variation state, the probability variation control is continuously performed, and the advantageous release control that increases the possibility that the game ball enters the second start winning opening is performed. The high base state and the high probability low base state in which the probability variation control is performed but the advantageous release control is not performed may be included. Also, in the short-time state, a low-accuracy base state where the special figure fluctuation time is shortened and advantageous opening control is performed, and a low-accuracy low-base state where the special figure fluctuation time is shortened but advantageous opening control is not performed. May be included. As an example, depending on whether the big hit type is “first probability change” to “third probability change” or “surprise probability”, after the big hit gaming state, the high accuracy high base state and the high probability low base state It may be controlled either. As another example, depending on whether the big hit type is “first probability change” to “third probability change” or “surprise probability”, the high-accuracy high base state and the high-accuracy low base state are You may make it make the ratio controlled to either differ mutually.

  In the embodiment described above, the “left”, “middle”, and “right” decorative symbol display areas 5L, 5C, and 5R are provided in the display area of the image display device 5, and the decorative symbol display areas 5L, 5C, and 5R are provided. In the above description, it is assumed that one decorative symbol is stopped and displayed so that the final decorative symbol that is the final stop symbol is stopped and displayed on one predetermined effective line. However, the present invention is not limited to this. For example, in the “left”, “middle”, and “right” decorative symbol display areas 5L, 5C, and 5R, three locations of “upper”, “middle”, and “lower” are provided. It is also possible that the decorative symbols can be stopped and displayed, and the finalized decorative symbols that will be the final stopped symbols are stopped and displayed on five or eight active lines.

  In the above embodiment, the pachinko gaming machine 1 provided with the first special symbol display device 4A and the second special symbol display device 4B has been described, but the present invention is also applied to a pachinko gaming machine provided with one special symbol display device. Part of can be applied. In this case, for example, the combination of the latch flip-flop 557B, the random number latch selector 558B, and the random value register 559B included in the random number circuit 509 shown in FIG. 13 is not used, and the security time is set to a predetermined time range for each system reset. It is only necessary that the security time can be changed, or the security time can be set to any of a plurality of pre-selectable extended times in addition to the fixed time.

  In addition, the device configuration of the pachinko gaming machine 1, the data configuration, the processing shown in the flowchart, the various display operations including the display operation of the display image in the display area of the image display device 5, etc. depart from the spirit of the present invention. Changes and modifications can be made arbitrarily without departing from the scope. In addition, the gaming machine of the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of a winning ball, but responds to detection of a winning ball by enclosing the gaming ball. It can also be applied to enclosed game machines that give points.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 4A, 4B Special symbol display device 5 Image display device 11 Main board 12 Production control board 22A, 22B Start switch 31 Game start switch 100 Microcomputer for game control 501 External bus interface 501A Internal resource access restriction circuit 502 Clock Circuit 503 Unique information storage circuit 504 Reset / interrupt controller 505 CPU
506 ROM
507 RAM
508 CTC
509 Random number circuit 510 PIP
511 Serial communication circuit 512 Address decoding circuit 551 Frequency monitoring circuit 552 Clock flip-flop 553 Random number generation circuit 554 Start value setting circuit 555 Random number sequence change circuit 556 Random number sequence change setting circuit 557A, 557B Latch flip-flop 558A, 558B Random number latch selector 559A, 559B random number value register

Claims (1)

Based on the detection signal, it is possible to display the variation, and when a specific condition is satisfied, the gaming machine can be controlled to an advantageous state advantageous to the player,
The detection signal includes a first detection signal and a second detection signal,
Numerical value updating means for updating numerical data;
Numerical data storage means for storing numerical data updated by the numerical value update means in a numerical data storage area based on the output of the detection signal;
After the numerical data is stored in the numerical data storage area, until the stored numerical data is read, the storage of new numerical data by the numerical data storage means is restricted, and the stored numerical values are stored. Numeric data holding means capable of holding data,
Numerical data reading means for reading numerical data stored in the numerical data storage area;
Determining means for determining whether or not to control to the advantageous state using the numerical data read by the numerical data reading means;
Non-volatile storage means storing control data;
Data read restriction means for restricting reading of the control data stored in the nonvolatile storage means from outside;
Regardless of whether the variation display based on the first detection signal or the variation display based on the second detection signal, a common variation timing means for measuring the time of the variation display;
Variable means for changing the execution period of a predetermined initial setting process including a security check process for checking whether or not the storage content of the nonvolatile storage means has been changed.
A gaming machine characterized by that.

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