JP5935978B2 - Pulse generation circuit - Google Patents

Description

  The present invention relates to a pulse generation circuit, and more particularly, to a pulse generation circuit that improves a short pulse generation technique using an intermittent multiplication circuit that operates a multiplication circuit intermittently to enable further short pulse generation.

  2. Description of the Related Art Conventionally, communication and radar using short pulse signals of UWB (Ultra Wide Band) technology have been developed as short pulse generation techniques. This ultra-wideband wireless is one of wireless communication systems, and is a wireless technology capable of high-speed communication at a short distance, and transmits and receives data by spreading it over an extremely wide frequency band of about 1 GHz. Since the data transmitted in each frequency band is only as strong as noise, there is an advantage that it does not interfere with wireless devices using the same frequency band and consumes less power. Position measurement, radar, wireless communication This is a very unique wireless application technology.

In order to make a short pulse signal a signal having only a component of a desired frequency band, a method of extracting only a specific frequency component by limiting the frequency band of the pulse signal with a filter, or intermittently oscillating the oscillation circuit with a pulsed control signal There are a method of operating, a method of generating a short pulse signal by inputting a pulsed control signal into a mixer and windowing a carrier signal.
These short pulse generation circuits have low power consumption operation and high on / off ratio as required performance. In addition, the low power consumption operation is an important performance when mounted on any device. For this reason, a high on / off ratio is an important performance for improving communication quality in communication using a short pulse signal.

However, since the conventional short pulse generation circuit uses an amplifier circuit to achieve a high on / off ratio, it has a problem of increasing power consumption and a problem of increasing the circuit scale. doing. There is also a problem that the output signal waveform is distorted.
In order to solve these problems, for example, the one described in Patent Document 1 uses an intermittent multiplier circuit that operates the multiplier circuit intermittently, operates with low power consumption, and realizes a very high on / off ratio. A short pulse generation circuit is proposed.

  FIG. 1 is a circuit configuration diagram for explaining a conventional pulse generation circuit, which is described in Patent Document 1 described above. In the figure, reference numeral 101 denotes an oscillation circuit, 102 denotes a control signal generation circuit, 103 denotes an intermittent multiplication circuit, 104 denotes a filter, 105 denotes an output terminal, and 201 to 204 denote signal waveforms. The oscillation circuit 101 and the intermittent multiplication circuit 103 are active circuits composed of active elements. The oscillation circuit 101 outputs a continuous signal and inputs it to the intermittent multiplication circuit 103. The intermittent multiplier 103 generates a short pulse signal by operating intermittently according to the control signal output from the control signal generator 102. The filter 104 removes spurious components of the short pulse signal.

  2A to 2D are timing charts of signals and control signals in the block configuration diagram shown in FIG. The vertical axis is all voltage, and the horizontal axis is time. The oscillation circuit 101 outputs the continuous signal 201 and inputs it to the intermittent multiplication circuit 103. The control signal generation circuit 102 outputs a control signal 202 and inputs it to the intermittent multiplication circuit 103. The control signal 202 acts on an active element that constitutes the intermittent frequency multiplier 103. The operating point of the FET constituting the intermittent multiplication circuit 103 is controlled by the voltage value of the control signal 202. By controlling the operating point of the FET, it is possible to increase the conversion gain in a section where the voltage value of the control signal 202 is high (hereinafter referred to as “on section”) and to reduce the conversion gain in a section where the voltage value is low (hereinafter referred to as “off section”). Therefore, the main component in the off section of the signal 203 is a signal having the frequency f0 / 2, and the frequency f0 component output from the intermittent multiplier 103 has a large amplitude value in the on section and the off section, and the difference between the on / off sections is on / off. The off ratio (unit: dB).

  The signal 203 output from the intermittent multiplication circuit 103 is input to the filter 104. The filter 104 is a spurious suppression filter that passes a signal in the frequency f0 band and suppresses other frequency band components, and is, for example, a BPF (band pass filter) or a BEF (band elimination filter). Further, it is desirable that the band of the filter 104 is a band that is at least twice the reciprocal of the pulse width of the On section of the signal 203, thereby preventing waveform rounding when the signal 204 is output from the filter 104. The filter 104 passes the signal 203 in the frequency f0 band and suppresses the signal in the frequency f0 / 2 band. Thereby, the output terminal 105 can output the short pulse signal 204 having a high on / off ratio having a frequency component in the frequency f0 band.

  The balun circuit is disclosed in, for example, Patent Document 2. A double balanced mixer circuit is disclosed in, for example, Patent Document 3.

JP 2008-35467 A JP-A-10-126196 JP 2010-62753 A

  However, the above-described pulse generation circuit described in Patent Document 1 has a problem due to the use of an intermittent multiplication circuit or an active amplification element. In other words, it is difficult to generate short pulses due to the delay between input and output and the recovery time of the amplifier (transistor), and the circuit scale is simplified due to the need for a filter circuit to suppress the generated aperias. There is a problem that cannot be achieved.

  The present invention has been made in view of such a problem, and an object of the present invention is to improve the pulse rising accuracy by using a differentiator having an excellent impulse / step response and generate the output of the differentiator. An object of the present invention is to provide a pulse generation circuit having a function of suppressing high frequency components.

The present invention has been made in order to achieve the object, the invention according to claim 1, in pulse generating circuit, and at least one differentiator which differentiates the input signal capture rise of the pulse a pulse signal processing circuit and a subtracter for outputting a pulse signal by subtracting the signals from at least the differentiator, difference in any DC level to input pulse signal from the pulse signal processing circuit A balun circuit that generates a dynamic signal and a double balanced mixer circuit that generates a differential pulse signal by superimposing a carrier on the differential signal generated from the balun circuit.

The invention of claim 2 is the invention according to claim 1, wherein the balun circuit includes a primary coil before Kipa pulse signal is input, is adjacent to the primary coil, wherein A secondary coil that outputs a differential signal and a center tap that sets the DC level are provided.
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the balun circuit further includes a variable capacitance circuit that suppresses a high frequency by using LC tuning. .

The invention of claim 4 is the invention according to claim 2 or 3, wherein the impedance ratio of the secondary coil with respect to the primary coil is two or more.
Also, the invention of claim 5 the invention according to any of claims 1-4, wherein the pulse signal processing circuit, a differentiator for differentiating the first input signals, from the fine fraction instrument An attenuator that adjusts the amplitude of the signal, an integrator that integrates the first input signal, a phase shift circuit that adjusts the amount of fluctuation in the phase of the second input signal that is opposite in phase to the first input signal, and characterized that a subtractor for outputting a Kipa pulse signal before by adding the signals from the signal and the phase shift circuit from the signal and the integrator from the attenuator. Example 1

The invention according to claim 6 is the invention according to claim 5 , wherein the differentiator is a variable phase differentiator. (Example 2)
The invention according to claim 7 is the invention according to claim 5 or 6 , wherein the integrator is a variable phase integrator. (Example 2)
The invention according to claim 8 is the invention according to any one of claims 1 to 7 , wherein the adder / subtracter has a configuration of a directional coupler or a hybrid ring. (Examples 1 and 2)

The invention according to claim 9 is the invention according to any one of claims 1 to 8 , wherein at least one of the differentiator, the integrator, the phase shift circuit, and the attenuator comprises a passive element. It is characterized by that. (Examples 1 and 2)
According to a tenth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the pulse signal processing circuit includes a differentiator that differentiates a first input signal, and the first input signal. be equipped with an integrator for integrating the second input signals of opposite phase, and a subtracter for outputting a Kipa pulse signal before by adding the signals from the signal and the integrator from said differentiator It is characterized by. (Example 3)

The invention described in claim 11 is the invention described in claim 10 , characterized in that the differentiator is a variable phase differentiator. (Example 3)
The invention according to claim 12 is the invention according to claim 10 or 11 , wherein the integrator is a variable phase integrator. (Example 3)
The invention described in claim 13 is characterized in that, in the invention described in claim 10, 11 or 12 , the adder / subtracter has a configuration of a directional coupler or a hybrid ring. (Example 3)
The invention according to claim 14 is the invention according to any one of claims 1 to 13 , wherein at least one of the differentiator and the integrator comprises a passive element. (Example 3)

The invention according to claim 15 is the first differentiation according to any one of claims 1 to 4 , wherein the pulse signal processing circuit directly differentiates the input signal to capture the rising edge of the pulse. A phase shift circuit that determines a pulse width by adjusting a phase fluctuation amount of the input signal using a phase fluctuation amount adjustment signal; and an attenuator that adjusts an amplitude of the signal from the phase shift circuit using a gain adjustment signal. , Pa and adding or subtracting the signal from the second differentiator and, signal and the second differentiator from said first differentiator which differentiates the signal from the attenuator catch falling of the pulse And an adder / subtractor for outputting a pulse signal. Example 4

According to a sixteenth aspect of the present invention, in the fifteenth aspect , the first and second differentiators are variable phase differentiators. (Example 5)
The invention according to claim 17 is the invention according to any one of claims 1 to 4 , wherein the pulse signal processing circuit differentiates the first input signal to capture the rising edge of the pulse; An integrator that integrates a second input signal that is opposite in phase to the first input signal input to the differentiator, a high-pass filter that band-limits the signal from the integrator according to a reference signal level, and the differentiator wherein a signal from the addition or subtraction of a signal from the high-pass filter, characterized in that it comprises a subtractor for outputting a pulse signal. (Example 6)
The invention described in claim 18 is the invention described in claim 17 , wherein the differentiator is a variable phase differentiator, the integrator is a variable phase integrator, and the high-pass filter is a programmable integrator. It is characterized by. (Example 7)

The invention according to claim 19 is the invention according to claim 17 or 18 , wherein the adder / subtracter has a configuration of a common mode extraction circuit. (Examples 6 and 7)
According to a twentieth aspect of the invention, in the invention of the nineteenth aspect , the common mode extraction circuit includes first and second common-source amplifiers. (Examples 6 and 7)

  According to the present invention, at least one of a differentiator, an integrator, an attenuator, a phase shift circuit, and a three-input adder / subtractor constituting the pulse generation circuit is constituted by a passive element, and the high frequency component generated by the output of the differentiator is generated. By having a suppression function, it is possible to minimize current consumption and distortion, and since the input signal is an operation signal, a pulse generation circuit that is friendly to the surrounding environment in consideration of unnecessary radiation should be realized. Can do.

It is a circuit block diagram for demonstrating the conventional pulse generation circuit. (A) thru | or (d) is a figure which shows the timing chart of the signal in the block block diagram shown in FIG. 1, and a control signal. It is a block block diagram for demonstrating embodiment of the pulse generation circuit which concerns on this invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram for explaining Example 1 of a pulse generation circuit according to the present invention. (A) thru | or (i) is a figure which shows the node voltage of each part of the pulse generation circuit based on this invention shown in FIG. It is a specific circuit block diagram of the differentiator shown in FIG. (A), (b) is a figure which shows the step response of the differentiator shown in FIG. FIG. 5 is a specific circuit configuration diagram of the integrator shown in FIG. 4. (A), (b) is a figure which shows the step response of the integrator shown in FIG. (A), (b) is a concrete circuit block diagram of the phase shift circuit shown in FIG. (A), (b) is a figure which shows the gain-phase frequency characteristic of the primary delay element in the phase shift circuit shown to Fig.10 (a), (b). (A), (b) is a concrete circuit block diagram which shows the other example of the phase shift circuit shown in FIG. (A), (b) is a figure which shows the gain-phase frequency characteristic in the phase shift circuit shown to Fig.12 (a), (b). It is a specific circuit block diagram of the attenuator shown in FIG. FIG. 5 is a circuit configuration diagram of the three-input adder / subtracter shown in FIG. 4. FIG. 5 is a circuit configuration diagram illustrating another example of the three-input adder / subtracter illustrated in FIG. 4. FIG. 5 is a specific circuit configuration diagram of a common mode extraction circuit as the two-input adder / subtracter illustrated in FIG. 4. 172, FIG. 15 “Common Mode Extraction Circuit 1” FIG. 16 is another specific circuit configuration diagram of the common mode extraction circuit as the two-input adder / subtracter illustrated in FIG. 15. (A), (b) is a block diagram of the hybrid ring as an adder / subtracter. (A), (b) is a block diagram of the hybrid ring as an adder / subtracter. (A), (b) is a block diagram of still another hybrid ring as an adder / subtracter. FIG. 5 is a circuit configuration diagram of a balun circuit with a center tap according to the first embodiment illustrated in FIG. 4. It is a figure which shows the specific structure of the balun circuit with a center tap shown in FIG. FIG. 5 is a circuit configuration diagram showing the double balanced mixer circuit shown in FIG. 4. (A) thru | or (c) is a figure which shows the circuit of a differential pair, and its characteristic. It is a circuit block diagram for demonstrating Example 2 of the pulse generation circuit which concerns on this invention. (A) thru | or (i) is a figure which shows the node voltage of each part of the pulse generation circuit based on this invention shown in FIG. It is a specific circuit block diagram of the variable phase differentiator shown in FIG. It is a specific circuit block diagram of the integrator type variable phase circuit shown in FIG. It is a circuit block diagram for demonstrating Example 3 of the pulse generation circuit which concerns on this invention. (A) thru | or (g) is a figure which shows the node voltage of each part of the pulse generation circuit based on this invention shown in FIG. FIG. 31 is a circuit configuration diagram of a balun circuit with a center tap according to the first embodiment illustrated in FIG. 30. It is a circuit block diagram for demonstrating the pulse signal processing circuit in Example 4 of the pulse generation circuit based on this invention. It is a circuit block diagram for demonstrating the pulse signal processing circuit in Example 5 of the pulse generation circuit based on this invention. It is a circuit block diagram for demonstrating the pulse signal processing circuit in Example 6 of the pulse generation circuit based on this invention. It is a circuit block diagram for demonstrating the pulse signal processing circuit in Example 7 of the pulse generation circuit based on this invention.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 3 is a block diagram for explaining an embodiment of the pulse generation circuit according to the present invention. In the figure, reference numeral 1 denotes a pulse signal processing circuit, 2 denotes a balun circuit, and 3 denotes a mixer circuit. The pulse generation circuit of the present invention is a pulse generation circuit that generates a short pulse signal by intermittently operating according to a control signal.

The pulse signal processing circuit 1 includes at least one differentiator that differentiates an input signal to catch the rising edge of the pulse, and an adder / subtracter that outputs at least a signal by adding / subtracting a signal from the differentiator. is there.
The balun circuit 2 used in the present invention is a balun circuit with a center tap, and generates a differential signal of an arbitrary DC level by inputting a short pulse signal from the pulse signal processing circuit 1. A primary side coil to which a short pulse signal is input, a secondary side coil that is adjacent to the primary side coil and outputs a differential signal, and a center tap for setting a DC level. It further includes a variable capacitance circuit that uses it to suppress high frequencies. Further, it is desired impedance ratio of the secondary coil to the primary coil is two or more. This balun circuit is a circuit for converting electrical signals in a balanced and unbalanced state, such as a coaxial cable and a two-wire feeder. Balun is a term that combines the acronyms of balance and unbalance, and is generally called a balance-unbalance converter.

  The mixer circuit 3 used in the present invention is a double balanced mixer circuit that generates a differential pulse signal by superimposing a carrier on the differential signal generated from the balun circuit 2. Impedance input. In general, a double balanced mixer (DBM) circuit is called a double balanced modulator, and both a signal LO from a local oscillator and an RF signal from an antenna can be input differentially. It means a mixer (mixer) that

The pulse generation circuit of the present invention suppresses generation of a high-frequency component due to generation of a short pulse with carriers superimposed and use of a differential waveform, and generates a pulse having a short width. Therefore, a differentiator and attenuator for capturing the rising edge of the pulse with high accuracy, an integrator for changing the shape of the short pulse to one with less high frequency, and a phase shift circuit for creating the falling edge of the pulse A 3-input adder / subtracter for waveform synthesis, a balun circuit with a center tap for setting the DC level to a value suitable for the double-balanced mixer in the next stage, and a double-balanced mixer circuit for superposing carriers Since the differentiator, the attenuator, the integrator, and the center-tapped balun circuit are composed of passive elements, the pulse generation circuit of the present invention can be used with very low power consumption. Also, by adjusting the level of the output of the differentiator with an attenuator, and adding or subtracting the output of the attenuator and the output of the integrator, a short pulse with less high frequency components than the output of the differentiator itself and the rectangular wave output Is obtained.
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 is a circuit configuration diagram for explaining the first embodiment of the pulse generation circuit according to the present invention. In the figure, 10 is a pulse signal processing circuit, 11 is a differentiator, 12 is an integrator, 13 is a phase shifter (phase shifter circuit), 14 is an attenuator, 15 is a 3-input adder / subtractor, and 16 is a center. A balun circuit with a tap, 17 is a double balanced mixer circuit. The pulse signal processing circuit 10 corresponds to the pulse signal processing circuit 1 shown in FIG. 3, the center tap-equipped balun circuit 16 corresponds to the balun circuit 2 shown in FIG. 3, and the double balanced mixer circuit 17 This corresponds to the mixer circuit 3 shown in FIG.

  The pulse generation circuit of the present invention is a pulse generation circuit that generates a short pulse signal by operating intermittently by a control signal. The pulse signal processing circuit 10 includes a differentiator 11 for differentiating the first input signal, an attenuator 14 for adjusting the amplitude of the signal from the differentiator 11, an integrator 12 for integrating the first input signal, A phase shift circuit 13 that adjusts the phase fluctuation amount of the second input signal that is opposite in phase to the input signal 1, a signal from the attenuator 14, a signal from the integrator 12, and a signal from the phase shift circuit 13. And an adder / subtractor 15 for adding and outputting a short pulse signal.

The center tap-equipped balun circuit 16 generates a differential signal of an arbitrary DC level by inputting a short pulse signal from the pulse signal processing circuit 10, and includes a primary side coil to which the short pulse signal is input, A secondary side coil that is adjacent to the primary side coil and outputs a differential signal, and a center tap that sets a DC level, and further includes a variable capacitance circuit that suppresses high frequency using LC tuning. ing. Further, it is desired impedance ratio of the secondary coil to the primary coil is two or more.

The double balanced mixer circuit 17 generates a differential pulse signal by superimposing a carrier on the differential signal generated from the center tap-equipped balun circuit 16, and is a high impedance input.
That is, the differentiator 11 differentiates the first input signal 101a to catch the rising edge of the pulse. The attenuator 14 adjusts the amplitude of the signal 102 from the differentiator 11 by multiplying the attenuation ATT by the gain adjustment signal 112.

  The integrator 12 integrates the first input signal 101a to suppress high frequency components. The phase shift circuit 13 adjusts the phase variation amount of the second input signal 101b having the opposite phase to the first input signal 101a by the phase variation control signal 110. The 3-input adder / subtractor 15 adds and subtracts the signal 105 from the attenuator 14, the signal 103 from the integrator 12, and the signal 104 from the phase shift circuit 13, and outputs a short pulse signal 106.

The differentiator 11 may be an RC differentiator or an LC differentiator. The integrator 212 is a variable phase integrator and has an integrator configuration including a resistance element and a capacitance element. The attenuator 14 has a configuration of a resistance tap including a plurality of resistance elements and a plurality of switches.
The phase shift circuit 13 has an integrator configuration including a resistance element and a capacitance element. The phase shift circuit 13 has an all-pass filter configuration including a resistance element and a capacitance element. The adder / subtractor 15 has a directional coupler or hybrid ring configuration. At least one of the differentiator 11, the integrator 12, the phase shift circuit 13, and the attenuator 14 is a passive element.

  With such a configuration, the pulse generation circuit includes a balun circuit with a center tap for setting the DC level to a value suitable for the double balanced mixer of the next stage, and a double balanced mixer circuit for superposing carriers. The at least one of the differentiator, integrator, phase shift circuit, and attenuator that composes the circuit is composed of passive elements and has the function of suppressing high frequency components generated by the output of the differentiator, thereby reducing current consumption and distortion. Since it can be minimized and the input signal is an operation signal, it is possible to realize a pulse generation circuit that is friendly to the surrounding environment in consideration of unnecessary radiation.

  FIGS. 5A to 5I are diagrams showing node voltages of respective parts of the pulse generation circuit according to the present invention shown in FIG. 4, and FIG. 5A is a diagram showing first and second input signals. 5B is a diagram showing a signal from a differentiator, FIG. 5C is a diagram showing a signal from an integrator, FIG. 5D is a diagram showing a signal from a phase shift circuit, and FIG. e) shows a signal from the subtractor, FIG. 5 (f) shows a short pulse signal output from the 3-input adder / subtractor (adder in the first embodiment), and FIG. 5 (g) shows the center. FIG. 5H is a diagram showing a differential clock signal, and FIG. 5I is a diagram showing a signal from a double balanced mixer circuit.

The amplitude of the first input signal 101a shown in FIG. 5A is + A, the amplitude of the second input signal 101b is -A, and the first input signal 101a and the second input signal 101b are differential. Input signal. The maximum value of the signal 102 from the differentiator 11 shown in FIG. 5B gradually approaches 0 at + A.
Further, the signal 103 from the integrator 12 shown in FIG. 5C is asymptotic to + A at t = 0 and amplitude is 0, and at t = t2. Further, the signal 104 from the phase shift circuit 13 shown in FIG. 5D has an amplitude of −A at t = t1. A signal 105 from the subtractor 14 shown in FIG. 5E is an output signal obtained by multiplying the signal 102 from the differentiator 11 by the attenuation amount ATT according to the information of the gain adjustment signal 112. This attenuation amount ATT ≦ 1.

The signal 106 from the three-input adder / subtractor 15 shown in FIG. 5 (f) is obtained by adding the signal 105 from the attenuator 14, the signal 103 from the integrator 12, and the signal 104 from the phase shift circuit 13. The signal 102 of the differentiator 11 is dominant in the vicinity of t = 0 in a short pulse signal. In the range of 0 <t <t1, the dominant factor transitions from the differentiator to the integrator.
That is, as t increases, a convex waveform that is characteristic of the output of the integrator is observed. This type of waveform is closer to a sine wave than the combination of a straight + 90 ° angle seen in a rectangular wave and therefore has fewer high frequency components.

  In order to reduce the influence of the high frequency component of the peak amplitude of the differentiator 11, the signal 103 from the integrator 12 is added to the signal 102 from the differentiator 11 via the attenuator 14. That is, in the three-input adder / subtractor 15, the signal 105 from the attenuator 14 and the signal 103 from the integrator 12 are added. Further, in order to cancel the DC component of the integrator 12 and obtain a steep fall, the transition from 0 to −A of the signal 104 from the phase shift circuit 13 is added at the time t = t1.

That is, at t = t1, the loss of force reaches near 0 due to the influence of the edge of −A included in the signal 104 from the phase shift circuit 13. Eventually, the signal 1006 from the three-input adder / subtractor 15 becomes 0 after the integrator asymptotic time t = t2. Thus, the pulse width of the output signal 106 of the present invention can be made shorter than the signal 102 from the differentiator 11.
Further, the signals 107a and 107b from the center-tapped balun circuit 16 shown in FIG. 5 (g) drive the double balanced mixer circuit 17, so that an appropriate operating point is set while performing a differential conversion from a single. The output obtained by passing through the balun circuit 16 with a center tap. The operating point of the DC is added to the center tap and is determined by the reference signal level.

  Further, the differential clock signals 109a and 109b shown in FIG. 5 (h) are differential input signals to the double balanced mixer circuit 17. Further, the signals 108a and 108b from the double balanced mixer circuit 17 shown in FIG. 5 (i) are differential in the envelopes (short pulse waveforms) of the signals 107a and 107b from the center-tapped balun circuit 16. Clock signals 109a and 109b operate. A desired output is obtained.

  The high frequency component resulting from the envelope of the output signal of the differentiator in the first embodiment is used by 1) attenuating the output of the differentiator with an attenuator. 2) By adding the convex signal above the integrator output (without attenuation) to the concave signal below the output of the differentiator (after attenuation), We were able to synthesize a waveform in which the convex waveform of the output was won, in other words, a waveform closer to a sine wave than a rectangular wave. 3) The generation of the falling edge uses addition of a step waveform having a higher frequency component than the differential waveform, that is, for the falling edge. It can be assumed that high-frequency components as high as the rising edge are not included. For these three reasons, the high frequency components can be greatly reduced compared to the case where the differentiator is used alone.

When a repetitive signal is used as the input signals 101a and 101b, it is necessary to provide a circuit that masks one of rising and falling edges. The mask circuit is usually composed of a switch inserted in series in the signal path and a control signal for turning on / off the switch.
FIG. 6 is a specific circuit configuration diagram of the differentiator shown in FIG. In the figure, Vi (t) indicates an input voltage, i (t) indicates an input current, Vc (t) indicates a capacitor terminal voltage, V _R (t) indicates a resistance terminal voltage, and q (t) indicates a capacitor charge. .

  In FIG. 6, a first-order differentiator based on R and C is shown, but a second-order differentiator based on L and C or a higher-order differentiator can also be used. That is, the differentiator 11 may be an RC differentiator or an LC differentiator. The greatest advantage of using this kind of differentiator is the edge enhancement function. As a result, it is possible to generate a rising edge with better accuracy than a general short pulse generator using a switching element or the like.

The time response of the differentiator shown in FIG. 6 is V _R (t) = Vi (t) −Vc (t) and q (t) = 0, so that V _R (t) = 0 (t <0 ), Eexp (−t / R ₁ C ₁ ) (t ≧ 0).
7 (a) and 7 (b) are diagrams showing step responses of the differentiator shown in FIG. 6. FIG. 7 (a) shows the step input signal of the differentiator, and FIG. 7 (b) shows the step input signal. The corresponding response signal is shown. According to FIGS. 7A and 7B, the step response rises in proportion to the derivative of the input, attenuates according to an exponential function having a time constant R ₁ C ₁ , and gradually approaches 0. I understand.

FIG. 8 is a specific circuit configuration diagram of the integrator shown in FIG. As with the differentiator described above, this integrator is also a first-order differentiator based on R and C. However, a higher-order integrator can also be used as a second-order integrator based on L and C. Further, the time response of the integrator shown in FIG. 8 is represented by V _C (t) = 0 (t <0), E (1−exp (−t / R ₂ C ₂ )) (t ≧ 0). .
9A and 9B are diagrams showing the step response of the integrator shown in FIG. 8, where FIG. 9A shows the step input and FIG. 9B shows the step response. It was confirmed that the time constant in the transient state of the integrator was expressed by the product of R and C, similar to the time constant of the differentiator.

10A and 10B are specific circuit configuration diagrams of the phase shift circuit shown in FIG. 4, and FIG. 10A is a circuit configuration diagram without a phase variation adjustment signal. (B) shows a circuit configuration diagram when there is a phase variation adjustment signal. In this example, the phase fluctuation amount is made variable by turning on / off Sc and S _2R in series with R or C by the phase fluctuation amount adjustment signal 110. A circuit such as a variable capacitance control circuit (varactor) may be used instead of Sc and C _2B .

The phase shift circuit 13 has a configuration of an integrator (first-order lag element) including a resistance element and a capacitance element. The transfer function in this case is
H (s) = V2 / V1 = 1 / (1 + SC ₂ R ₂ )
It is represented by

FIGS. 11A and 11B are diagrams showing the gain-phase frequency characteristics of the first-order lag element in the phase shift circuit shown in FIGS. 10A and 10B. FIG. 11A shows gain-frequency characteristics, and FIG. 11B shows phase-frequency characteristics. The phase shift circuit described above is characterized in that the phase is delayed by 45 ° when the pole frequency is 1 / 2πR ₂ C ₂ .
12A and 12B are specific circuit configuration diagrams showing another example of the phase shift circuit shown in FIG. 4, and FIG. 12A shows a circuit configuration without a phase variation adjustment signal. FIG. 12B shows a circuit configuration diagram when there is a phase variation adjustment signal. This phase shift circuit has a configuration of an all-pass filter including a resistance element and a capacitance element.
In this example, the phase fluctuation amount is made variable by switching on / off of Sc in series with C by the phase fluctuation amount adjustment signal 110. Even in this circuit, the same effect can be obtained by switching R as shown in FIG. 12B or changing C to a variable capacitance control circuit (varactor).

FIGS. 13A and 13B are diagrams showing the gain-phase frequency characteristics in the phase shift circuit shown in FIGS. 12A and 12B. FIG. 13A shows gain-frequency characteristics, and FIG. 13B shows phase-frequency characteristics.
As shown in FIGS. 13A and 13B, the all-pass filter is a generic term for a gain-frequency characteristic that is flat and changes only in phase. In addition to the phase shift circuit shown in FIGS. 12A and 12B, there are many circuits.

This phase shift circuit can also obtain an arbitrary amount of phase shift by changing R and C in the same manner as the circuit of the first-order lag element.
The phase shift amount θ is represented by θ = −2 tan ⁻¹ (ω / 2πα ₀ ).
θ = 0 when ω = 0
When ω = 2πα ₀ , θ = −90 °
When ω = ∞, θ = −180 °
It becomes.
The transfer function is
H (s) = (S−α ₀ ) / (S + α ₀ ) α ₀ = 1 / R ₀ C ₀
θ = -2 tan ⁻¹ (ω / 2πα ₀ )
It is represented by

FIG. 14 is a specific circuit configuration diagram of the attenuator shown in FIG. The attenuator 14 has a configuration of a resistance tap including a plurality of resistance elements Ra, Rb, Rc and a plurality of switches Sa, Sb, Sc.
By adjusting the attenuation amount of the attenuator 14 so that the amplitude of the input of the adder / subtracter at the rising timing of the delay pulse is the same, a pulse having a sharp falling edge can be obtained. This is shown in FIG. 5 (f).
The transfer function in this case is
H (s) = V2 / V1 = 1 (Sa; closed) = (Rc + Rb) / (Ra + Rb + Rc) (Sb; closed)
It is represented by

  The truth table between the attenuator gain adjustment signals Ca, Cb, Cc and the states of the switches Sa, Sb, Sc and the corresponding transfer function are shown in Table 1 below.

  FIG. 15 is a specific circuit configuration diagram of the three-input adder / subtracter shown in FIG. 4. Reference numerals 15a and 15b in the drawing denote first and second two-input adder / subtractors. The three-input adder / subtracter 15 in this embodiment can be achieved by cascading the first and second two-input adder / subtractors 15a and 15b. Since the passive adder / subtractor always has a loss, the path loss differs between the inputs 102, 103, and 104. It is not preferable to lead the output 102 of the differentiator 11 with the attenuator 4 between them to the port 104 of the three-input adder / subtractor 15 and should be connected to the port 102 or 103. Whether the output of the integrator 12 or the output 104 of the phase shift circuit 13 is connected to the port 104 largely depends on the path loss due to the circuit configuration, but in the following description, the operation is easily understood. Thus, the port 105 (output of the attenuator) is connected to the input 1 (port A) of FIG. 19A (described later), and the port 103 (output of the integrator) is connected to FIG. 19A (described later). Is connected to input 2 (port C) of FIG. 19, the added output of the first adder 15a is output to port B of FIG. 19A (described later), and the added output of the first adder 15a is changed to the second output. 2 is connected to the input 1 (port A) as the input of the adder 15b, and the port 104 (output of the phase shift circuit) is connected to the input 2 (port C) of FIG. The addition output of the second adder 15b is as shown in FIG. Is output to the port B to be described later).

FIG. 16 is another specific circuit configuration diagram of the three-input adder / subtracter shown in FIG. 4 and shows a wired OR type three-input adder / subtractor using three MOS transistors. This circuit is composed of three independent source-grounded amplifiers and a load resistor R _L. When M1, M2, and M3 have the same (W / L; ratio of channel width (W) to channel length (L)), the output of the 3-input adder / subtractor 15 is proportional to the added value of the inputs 105, 103, and 104. An output 106 is obtained. When this circuit is used, a function equivalent to that of the attenuator can be realized by selecting W1 / L of M1 <M2, W / L of M3, so that the attenuator can be omitted.

FIG. 17 is a specific circuit configuration diagram of the common mode extraction circuit as the 2-input adder / subtracter shown in FIG. The adder / subtractor 15 described above has a configuration of a common mode extraction circuit. This common mode extraction circuit has a resistance division configuration including a plurality of resistance elements.
The transfer function of this common mode extraction circuit is represented by Vcom = (V1 + V2) / 2. Although this transfer function and gain have the disadvantage of being half that of the adder circuit, they have many advantages in that they are wideband, can be miniaturized, and can provide high accuracy.

FIG. 18 is another specific circuit configuration diagram of the common mode extraction circuit as the two-input adder / subtracter shown in FIG. 15. By using a wired OR type circuit configuration of two independent source-grounded amplifiers, a common mode is shown. The signal is extracted. Further, in order to extract a three-input common mode, a wired OR type circuit configuration of three independent source-grounded amplifiers may be used. M1 and M2 are common mode amplification transistors, _RL is a load resistor, M0 is Ibas, R1 and R2 are bias voltage generation circuits, Vac1 and Vac2 are input voltages, Vout is an output voltage, and Vdd is a positive power supply voltage. Show. Vout is approximately proportional to Vac1 + Vac2, and is a wired OR connection of two source grounded amplifiers.

FIGS. 19A and 19B are configuration diagrams of a rat race hybrid ring used as an adder / subtracter, and are diagrams showing the state of each port when the port A of the adder / subtractor is an input. FIG. 19A is a diagram in which the ports C and A are insulated, and FIG. 19B is a diagram in which the port A and -3 dB signals of the port A input are output to the ports B and D.
FIGS. 20A and 20B are configuration diagrams of a rat race hybrid ring used as an adder / subtracter. FIG. 20A shows a state of each port when the port C of the adder / subtractor is an input. FIG. Ports C and A are insulated from each other, and FIG. 20B is a diagram in which a -3 dB signal of port C input is output to ports B and D.

  In any of FIGS. 19A and 19B and FIGS. 20A and 20B described above, a distance between a 0 (or 360 °) phase signal and a 180 ° phase signal is used for insulation. It can be seen that the -3 dB signal also realizes λ / 4 × n (n = 1, 3, 5,... Odd) as a function of distance.

  The rat race hybrid ring is a generally known circuit in a high frequency circuit. Ports AB, BC, and CD are spaced apart by λ / 4, and ports AD are spaced 3λ / 4 apart. With this arrangement, the input / output relationship between the ports is as follows. First, when a signal is input to port C, a wave that travels through the ring by 5λ / 4 clockwise from port C and a wave that travels λ / 4 counterclockwise from port C arrive at port B. Since these two waves are in phase, the sum is output to port B. Similarly, in both ports D and B, the clockwise and counterclockwise waves are added and output. A wave that travels λ clockwise from port C and a wave that travels λ / 2 counterclockwise from port C arrive at port A. Since these two waves are out of phase, they are canceled out, and port A is isolated from port C. Accordingly, the port A is completely unrelated, and when viewed from the port C, the port B and the port D are arranged symmetrically. That is, the input from the port C is equally distributed to the ports B and D and output. At this time, the outputs from ports B and D are in phase. Next, when a signal is input to port A, similarly, port C is completely irrelevant, and when viewed from port A, it looks like a circuit in which two ports B and D are arranged. That is, the input from port A is distributed to ports B and D and output. At this time, the phases of the outputs from the ports B and D are reversed (180 ° phase is different).

21A and 21B are configuration diagrams of still another rat race hybrid ring used as an adder / subtractor. FIG. 21A is a diagram showing the behavior of the output port B, and FIG. 6 is a diagram illustrating the behavior of an output port D.
An adder / subtracter realized by using port A as input 1, port C as input 2, port B as an addition port, and port D as a subtraction port is shown. If the port B, which is the same distance from the ports A and C, is used as the phase reference, the signal from the port C has the same phase at the ports B and D, and the signal from the port A has the opposite phase at the ports B and D. Therefore, it can be seen that port B is addition and port D is subtraction.

  FIG. 22 is a circuit configuration diagram of the balun circuit with a center tap according to the first embodiment illustrated in FIG. 4. In general, the balun circuit is a circuit that uses a single end for differential conversion, and a balun circuit with a center tap that can cut the DC and operate the secondary side at an arbitrary DC level is preferable. It is assumed that the primary side uses a single end and the secondary side uses a differential balance. Note that the signal 106 from the three-input adder / subtractor 15 is input to the primary coil L1, the secondary coil L2, and the primary input terminal. Further, the signals 107a and 107b from the center-tapped balun circuit 16 are output to the secondary differential output terminal. The signal 111 to the center tap is a reference signal level and sets the DC operating point of the output signal.

  FIG. 23 is a diagram showing a specific structure of the balun circuit with a center tap shown in FIG. In the drawing, the inner side shows the primary side coil of the L1 portion shown in FIG. 22, and the outer side shows the secondary side coil of the L2 portion shown in FIG. An example of a balun circuit that can achieve an impedance ratio of 2 or more even at a frequency of 10 GHz or more is shown. In order to obtain the impedance ratio L2 / L1> 2, the winding ratio is usually set to √2 or more. However, since the present invention assumes applications with a fundamental frequency of 10 GHz or higher, it is difficult to achieve a winding ratio. However, recently, a balun circuit that can be used up to an impedance ratio of 3 or more and a frequency near 100 GHz by adding the wiring width of the structure shown in FIG. 23 to the design parameters has been reported. The balun circuit used in the present invention is also assumed to be a balun circuit in which a center tap is added to the secondary side based on the structure shown in FIG.

24 is a circuit configuration diagram showing the double balanced mixer circuit shown in FIG. The feature of this double balanced mixer circuit is that when the inputs 106a and 106b are DC, no carrier component is output from the outputs 107a and 107b. Therefore, in the present invention as well, short pulses with superimposed carriers are utilized. Generation is in progress. Furthermore, this double balanced mixer circuit is also an important requirement for ON / OFF operation with a high input impedance and a small signal. From this viewpoint, the above double balanced mixer circuit is preferable. Q1 and Q2 are NPN transistors, R _L is a load resistance, Itail is a current flowing through a tail current source, and signals 107a and 107b from the center-tapped balun circuit 17 are input to the NPN transistors Q1 and Q2. The differential clock signals 109a and 109b are inputted to the NPN transistors Q3, Q4, Q5 and Q6, and the signals 108a and 108b are outputted from the double balanced mixer circuit 17.

25 (a) to 25 (c) are diagrams showing a differential pair circuit and its characteristics, FIG. 25 (a) is a circuit diagram of the differential pair, and FIG. 25 (b) is a DC characteristic of the differential pair. FIG. 25C shows the DC characteristics of the differential pair, showing the relationship between the differential input voltage and the differential output voltage. The horizontal axis of FIG.25 (b) and FIG.25 (c) is shown by the thermal voltage (Vt),
Vt = kT / q (k is Boltzmann constant, T is temperature, q is electron charge)
Is approximately 26 mV (at 300 K). In particular, in FIG. 25B, it was found that 4 × Vt≈100 mV is required to turn on / off the current flowing through the bipolar transistor (BJT).

  FIG. 26 is a circuit configuration diagram for explaining Example 2 of the pulse generation circuit according to the present invention. In the figure, reference numeral 20 is a pulse signal processing circuit, 21 is a differentiator type variable phase circuit (variable phase differentiator), 22 is an integrator type variable phase circuit (variable phase integrator), 23 is a phase shift circuit, and 24 is an attenuator. (Attenuator), 25 is a three-input adder / subtracter, 26 is a balun circuit with a center tap, and 27 is a double balanced mixer circuit.

That is, the pulse generation circuit shown in FIG. 26 includes a pulse signal processing circuit 20, a balun circuit 26 with a center tap, and a double balanced mixer circuit 27. The pulse signal processing circuit 20 includes a differentiator variable phase circuit 21. And an integrator variable phase circuit 22, a phase shift circuit 23, an attenuator 24, and a three-input adder / subtractor 25.
In the pulse generation circuit of the second embodiment, the differentiator 11 and the integrator 12 in the first embodiment shown in FIG. 3 are each provided with a phase variable function, and a differentiator type variable phase circuit (variable phase differentiator) 21 and The integrator type variable phase circuit (variable phase integrator) 22 is used, and the output 202 of the differentiator type variable phase circuit 21 is provided with a gain adjusting function by the attenuator 24. Further, the phase shift circuit 23 is used to add and subtract three inputs. The output 25 of the differentiator variable phase circuit 21, the output 203 of the integrator variable phase circuit 22, and the output 204 of the phase shift circuit 23 are input to the calculator 25.

  The pulse generation circuit according to the second embodiment is a pulse generation circuit that generates a short pulse signal by operating intermittently with a control signal, as in the first embodiment. The differentiator type variable phase circuit 21 is phase-variable by the first phase change amount control signal 210, and differentiates the first input signal 201a to capture the rising edge of the pulse. The attenuator 24 adjusts the amplitude of the signal 202 from the differentiator 21 by multiplying the attenuation ATT by the gain adjustment signal 214. The integrator-type variable phase circuit 22 is phase-variable by the second phase change amount control signal 211 and integrates the first input signal 201a to suppress high frequency components.

  The phase shift circuit 23 adjusts the amount of phase fluctuation of the second input signal 201 b having the opposite phase to the first input signal 201 a by the third phase change amount control signal 212. The 3-input adder / subtractor 25 adds and subtracts the signal 205 from the attenuator 24, the signal 203 from the integrator variable phase circuit 22 and the signal 204 from the phase shift circuit 23, and outputs a short pulse signal 206. It is.

The center-tapped balun circuit 26 generates a differential signal of an arbitrary DC level by inputting a short pulse signal from the pulse signal processing circuit 20, and includes a primary side coil to which the short pulse signal is input, A secondary side coil that is adjacent to the primary side coil and outputs a differential signal, and a center tap that sets a DC level, and further includes a variable capacitance circuit that suppresses high frequency using LC tuning. ing. Further, it is desired impedance ratio of the secondary coil to the primary coil is two or more.

The double balanced mixer circuit 27 generates a differential pulse signal by superimposing a carrier on the differential signal generated from the center tap balun circuit 26, and is a high impedance input.
As described above, the pulse generation circuit in the second embodiment is for achieving further suppression of high-frequency components as compared with the first embodiment described above, and has a function of changing the phases of the differentiator and the integrator. . Thereby, the non-edge (intermediate portion) waveform of the short pulse waveform can be brought close to a sine wave with an increased degree of freedom, and the high frequency can be reduced.

  A differential circuit constituting a pulse generation circuit comprising a balun circuit with a center tap for setting a DC level to a value suitable for a double balanced mixer in the next stage and a double balanced mixer circuit for superposing carriers. At least one of the integrator, integrator, phase shift circuit, and attenuator is composed of passive elements, and has a function to suppress high frequency components generated by the output of the differentiator, thereby minimizing current consumption and distortion. In addition, since the input signal is an operation signal, it is possible to realize a pulse generation circuit that is friendly to the surrounding environment in consideration of unnecessary radiation.

  FIGS. 27A to 27I are diagrams showing node voltages of respective parts of the pulse generation circuit according to the present invention shown in FIG. 26, and FIG. 27A is a diagram showing first and second input signals. FIG. 27B is a diagram showing a signal from the differentiator type variable phase circuit, FIG. 27C is a diagram showing a signal from the integrator type variable phase circuit, and FIG. 27D is a diagram showing the signal from the phase shift circuit. FIG. 27E shows a signal from the subtractor. FIG. 27F shows a short pulse signal output from the 3-input adder / subtracter (adder in the second embodiment). FIG. 27 (g) is a diagram showing a signal from a balun circuit with a center tap, FIG. 27 (h) is a diagram showing a differential clock signal, and FIG. 27 (i) is a diagram showing a signal from a double balanced mixer circuit. It is.

  The amplitude of the first input signal 201a shown in FIG. 27A is + A, the amplitude of the second input signal 201b is -A, and the first input signal 201a and the second input signal 201b are differential. Input signal. The phase time constant of the signal 202 from the differentiator variable phase circuit 21 shown in FIG. 27B is controlled through the first phase variation control signal 210. However, the first phase variation control signal 210 does not affect the peak amplitude. The maximum value gradually approaches 0 at + A. The phase time constant of the signal 203 from the integrator type variable phase circuit 22 shown in FIG. 27C is controlled through the second phase variation control signal 211. The signal 203 has an amplitude of 0 at t = 0 and asymptotically approaches + A at t = t2.

The signal 204 from the phase shift circuit 23 shown in FIG. 27D has an amplitude of -A at t = t1. The signal 205 from the subtractor 24 shown in FIG. 27E is an output signal obtained by multiplying the signal 202 from the differentiator variable phase circuit 21 by the attenuation ATT according to the information of the gain adjustment signal 214. is there. This attenuation amount ATT ≦ 1.
Further, the signal 206 from the three-input adder / subtracter 25 shown in FIG. 27 (f) includes a signal 205 from the attenuator 24, a signal 203 from the integrator variable phase circuit 22, and a signal 204 from the phase shift circuit 23. Is a short pulse signal. In the vicinity of t = 0, the signal 202 of the differentiator variable phase circuit 21 is dominant. In the range of 0 <t <t1, the dominant factor transitions from the differentiator to the integrator.

  That is, as t increases, a convex waveform that is characteristic of the output of the integrator is observed. This type of waveform is closer to a sine wave than the combination of a straight + 90 ° angle seen in a rectangular wave and therefore has fewer high frequency components. At t = t1, the loss of force reaches near 0 due to the influence of the edge of −A included in the signal 204 from the phase shift circuit 23. Eventually, the signal 206 from the 3-input adder / subtractor 25 becomes 0 after the integrator asymptotic time t = t2.

  That is, in order to reduce the influence of the high frequency component of the peak amplitude of the differentiator variable phase circuit 21, the signal 203 from the integrator variable phase circuit 22 is transmitted from the differentiator variable phase circuit 21 via the attenuator 24. The signal 202 is added. That is, in the three-input adder / subtractor 25, the signal 205 from the attenuator 24 and the signal 203 from the integrator type variable phase circuit 22 are added. Further, in order to cancel the DC component of the integrator type variable phase circuit 22 and obtain a steep fall, a transition from 0 to −A of the signal 204 from the phase shift circuit 23 is added at the time t = t1. . Thus, the pulse width of the output signal 206 of the present invention can be made shorter than that of the signal 202 from the differentiator variable phase circuit 21.

Further, the signals 207a and 207b from the center tap-equipped balun circuit 26 shown in FIG. 27 (g) drive the double balanced mixer circuit 27, so that an appropriate operating point is set while performing a differential conversion from a single. The output obtained by passing through the balun circuit 26 with a center tap. The operating point of the DC is added to the center tap and is determined by the reference signal level.
The differential clock signals 209a and 209b shown in FIG. 27H are differential input signals to the double balanced mixer circuit 27. Also, the signals 208a and 208b from the double balanced mixer circuit 27 shown in FIG. 27 (i) are differential in the envelopes (short pulse waveforms) of the signals 207a and 207b from the balun circuit 26 with center tap. Clock signals 209a and 209b operate. A desired output is obtained.

  The high frequency component resulting from the envelope of the output signal of the differentiator in the second embodiment is used by 1) attenuating the output of the differentiator with an attenuator. 2) By adding the convex signal above the integrator output (without attenuation) to the concave signal below the output of the differentiator (after attenuation), We were able to synthesize a waveform in which the convex waveform of the output was won, in other words, a waveform closer to a sine wave than a rectangular wave. 3) The generation of the falling edge uses addition of a step waveform having a higher frequency component than the differential waveform, that is, for the falling edge. It can be assumed that high-frequency components as high as the rising edge are not included. For these three reasons, the high frequency components can be greatly reduced compared to the case where the differentiator is used alone.

When a repetitive signal is used for the input signals 201a and 201b, a circuit for masking one of the rising edge and the falling edge needs to be placed in front. The mask circuit is usually composed of a switch inserted in series in the signal path and a control signal for turning on / off the switch.
FIG. 28 is a specific circuit diagram of the differentiator variable phase circuit shown in FIG. The phase change amount is changed by switching the series capacitance value of the time constant of the differentiator type variable phase circuit (variable phase differentiator) according to the phase change amount control signal Cnt1A. For example, when S _1A is turned on and the capacity of the differentiator becomes C ₁ + C _1A , the attenuation of the differentiator becomes smoother than when the capacity is only C ₁ . Here, an amplitude and a set of amplitudes at a point after a certain time has elapsed from the time with reference to “phase”. Thereby, it can be understood that the phase of a system having a large time constant is delayed.

  The operational truth values and series capacitance values of the differentiator type variable phase circuit are shown in Table 2 below.

It should be noted that the second embodiment also has the same effect as the first embodiment described above.
FIG. 29 is a specific circuit diagram of the integrator type variable phase circuit shown in FIG. The phase change amount is changed by switching the parallel capacitance value of the time constant of the integrator type variable phase circuit (variable phase integrator) in accordance with the phase change amount control signal Cnt2A. An equivalent circuit state change can be obtained by switching R instead of switching C. Table 3 shows the operation truth value and parallel capacitance of the variable phase integrator.

A specific circuit configuration diagram of the attenuator of the pulse generation circuit according to the present invention shown in FIG. 26 is the same as that of the attenuator shown in FIG. The attenuator 24 has a configuration of a resistance tap including a plurality of resistance elements Ra, Rb, Rc and a plurality of switches Sa, Sb, Sc.
By adjusting the attenuation amount of the attenuator 24 so that the amplitude of the input of the adder / subtracter at the rising timing of the delay pulse is the same, a pulse having a sharp falling edge can be obtained. This is shown in FIG. 27 (f).

FIG. 30 is a circuit configuration diagram for explaining Example 3 of the pulse generating circuit according to the present invention. In the figure, reference numeral 30 is a pulse signal processing circuit, 31 is a differentiator type variable phase circuit (variable phase differentiator), 32 is an integrator type variable phase circuit (variable phase integrator), 33 is an adder / subtractor, and 34 is a center tap. A balun circuit 35 is a double balanced mixer circuit.
That is, the pulse generation circuit shown in FIG. 30 includes a pulse signal processing circuit 30, a balun circuit 34 with a center tap, and a double balanced mixer circuit 35. The pulse signal processing circuit 30 includes a differentiator variable phase circuit 31. And an integrator-type variable phase circuit 32 and an adder / subtractor 33.

The pulse generation circuit of the third embodiment has a configuration in which the attenuator 24 and the phase shift circuit 23 in the second embodiment shown in FIG.
The pulse generation circuit according to the third embodiment is a pulse generation circuit that generates a short pulse signal by operating intermittently with a control signal, similarly to the first and second embodiments described above. The differentiator-type variable phase circuit 31 is phase-variable by the first phase change amount control signal 308, and differentiates the first input signal 301a to capture the rising edge of the pulse. The integrator-type variable phase circuit 32 is phase-variable by the second phase change amount control signal 309 and integrates the first input signal 301b to suppress high frequency components.

The center-tapped balun circuit 34 generates a differential signal of an arbitrary DC level by inputting the short pulse signal 304 from the pulse signal processing circuit 30, and the primary coil to which the short pulse signal is input. And a variable-capacitance circuit that is adjacent to the primary side coil and outputs a differential signal, and a center tap that sets a DC level, and that suppresses high frequency using LC tuning. I have. Further, it is desired impedance ratio of the secondary coil to the primary coil is two or more.
The double balanced mixer circuit 35 generates a differential pulse signal by superimposing a carrier on the differential signal generated from the center tap balun circuit 34, and is a high impedance input.

  As described above, the pulse generation circuit according to the third embodiment does not suppress the high frequency by bringing the input of the double balanced mixer circuit close to the sine wave input, but normally turns the double balanced mixer circuit on and off. The high frequency inherent to the differential waveform is not transmitted to the output. Specifically, 1) obtaining a high gain by setting the impedance ratio between the primary and secondary of the center tap balun circuit to 1: 2 or more, and 2) a double balanced mixer circuit for effective use of the voltage gain. Is a bipolar transistor (BJT) that is turned on / off with a small amplitude. 3) A high-frequency input is reduced by providing a tuned function to the balun circuit with a center tap. ) The input amplitude condition necessary for on / off when the above condition is disclosed is analytically clarified, and a high-frequency suppression short pulse generation circuit that does not consume power is realized.

  31 (a) to 31 (g) are diagrams showing node voltages of respective parts of the pulse generation circuit according to the present invention shown in FIG. 30, and FIG. 31 (a) is a diagram showing first and second input signals. 31 (b) is a diagram showing a signal from a differentiator type variable phase circuit, FIG. 31 (c) is a diagram showing a signal from an integrator type variable phase circuit, and FIG. 31 (d) is an adder / subtracter (this embodiment). FIG. 31E shows a signal from a balun circuit with a center tap, FIG. 31F shows a differential clock signal, and FIG. 31E shows a short pulse signal output from an adder in Example 3. FIG. 31G shows a signal from the double balanced mixer circuit.

What is important here is that 1) the transformer impedance ratio is 1: 2 or more, 2) the input part of the double balanced mixer circuit is the transformer side 50Ω, the mixer side Hiz, and 3) the double balanced The mixer input at the moment of turning on / off the mixer circuit is required to be 100 mV _OP or more.

Next, according to 1) to 3), the input differential signal input level necessary for turning the double balanced mixer circuit on and off is obtained. First, it can be seen from 3) that a double-balanced mixer circuit input requires a differential input of 100 mV _OP of 200 mV _PP and a single end of 400 mV _PP . Since the voltage amplitude is doubled from 50Ω to Hiz and doubled by the impedance ratio of the transformer, it can be seen that a 1/4 mV _PP differential input is required at the input end.

  The expected effects are as follows: 1) Tr is switched on when the mixer is on. 2) Tr is switched off when the mixer is off. 3) For the above reasons, the high-frequency component inherent in the differential waveform does not appear in the output of the double balanced mixer circuit. In addition, an LC tuning circuit is mounted on the transformer input unit to suppress high frequency components.

  The amplitude of the first input signal 301a shown in FIG. 31A is + A, the amplitude of the second input signal 301b is -A, and the first input signal 301a and the second input signal 301b are differential. Input signal. The phase time constant of the signal 302 from the differentiator variable phase circuit 31 shown in FIG. 31B is controlled through the first phase variation control signal 308. However, the first phase variation control signal 308 does not affect the peak amplitude. The maximum value is + A, and when t = t1, the amplitude becomes E and gradually approaches 0. Further, the phase time constant of the signal 303 from the integrator type variable phase circuit 32 shown in FIG. 31C is controlled through the second phase variation control signal 309. This signal 303 has an amplitude of 0 at t = 0 and asymptotically approaches -E at t = t2.

  Further, the signal 304 from the adder / subtractor 33 shown in FIG. 31D is obtained by adding the signal 302 from the differentiator variable phase circuit 31 and the signal 303 from the integrator variable phase circuit 32 to add a short pulse signal. In the vicinity of t = 0, the signal 302 of the differentiator type variable phase circuit 31 is dominant. In the range of 0 <t <t1, the dominant factor transitions from the differentiator to the integrator. The signal 304 from the adder / subtractor 33 is +50 mV at t = t1, zero-crosses at t = t2, and asymptotically approaches −A after the elapse of time due to the influence of the integrator type variable phase circuit 32.

That is, in the adder / subtractor 33, the signal 303 from the integrator variable phase circuit 32 is changed to the signal from the differentiator variable phase circuit 31 in order to reduce the influence of the high frequency component of the peak amplitude of the differentiator variable phase circuit 31. 302 is added. Thus, the pulse width of the output signal 304 of the adder / subtractor 33 can be made shorter than the signal 302 from the differentiator variable phase circuit 31.
In addition, the signals 305a and 305b from the center tap-equipped balun circuit 34 shown in FIG. 31 (e) drive the double balanced mixer circuit 35, so that an appropriate operating point is set while performing a differential conversion from single. The output obtained through the balun circuit 34 with a center tap. The low frequency component of the output of the integrator is removed due to the influence of the LC tuner arranged at the input section. Since the transformer has the effect of removing the DC component, no HPF is required. The DC level of the output signal is set to a point where the next stage double balanced mixer circuit is easy to operate by the DC cut and center tap of the transformer. The frequency of the LC tuning circuit is controlled by a tuning frequency control signal, and the DC level is determined by the reference signal level.

  The differential clock signals 307a and 307b shown in FIG. 31 (f) are differential input signals to the double balanced mixer circuit 35. Further, the signals 306a and 306b from the double balanced mixer circuit 35 shown in FIG. 31 (g) are differential in the envelopes (short pulse waveforms) of the signals 305a and 305b from the center tap balun circuit 34. Clock signals 307a and 307b operate. A desired waveform output in which the carrier is turned on / off with a short pulse is obtained.

FIG. 32 is a circuit configuration diagram of the center tap-equipped balun circuit of the third embodiment shown in FIG. 30 and has an LC tuning circuit on the primary side and an impedance ratio (L2 / L1) of 2 or more. The balun circuit with a center tap is shown. In the third embodiment, since there is no high-frequency component suppression function as in the first and second embodiments, the high-frequency component is suppressed using LC tuning. When the basic frequency of the generated short pulse is f0, the capacity of the variable capacitor C1 is adjusted through the band control signal so that f0 = 1 / 2π√L1L1.
Various pulse signal processing circuits of the pulse generation circuit according to the present invention will be described below.

FIG. 33 is a circuit configuration diagram for explaining a pulse signal processing circuit in a fourth embodiment of the pulse generating circuit according to the present invention. In the figure, reference numeral 40 is a pulse signal processing circuit, 41 is a phase shift circuit, 42 is an attenuator, 43a is a first differentiator, 43b is a second differentiator, and 44 is an adder / subtractor. .
The pulse signal processing circuit 40 according to the fourth embodiment includes a phase shift circuit 41, an attenuator 42, a first differentiator 43a, a second differentiator 43b, and an adder / subtractor 44.

  The pulse generation circuit of the present invention is a pulse generation circuit that generates a short pulse signal by operating intermittently by a control signal. The first differentiator 43a differentiates the input signal 401 directly to capture the rising edge of the pulse. The phase shift circuit 41 determines the pulse width by adjusting the phase fluctuation amount of the input signal 401 using the phase fluctuation amount adjustment signal 407.

  The attenuator 42 adjusts the amplitude of the signal 402 from the phase shift circuit 41 by a gain adjustment signal 408. The second differentiator 43b differentiates the signal 403 from the attenuator 42 to catch the falling edge of the pulse. The adder / subtractor 44 adds and subtracts the signal 404 from the first differentiator 43a and the signal 405 from the second differentiator 43b to output a short pulse signal 406.

  In other words, the pulse signal processing circuit directly adjusts the amount of fluctuation of the phase of the input signal by the first differentiator 43a that directly differentiates the input signal to catch the rising edge of the pulse, and the pulse width by adjusting the phase fluctuation amount adjustment signal 407. A phase shift circuit 41 for determining the amplitude, an attenuator 42 for adjusting the amplitude of the signal from the phase shift circuit 41 by the gain adjustment signal 408, and a second signal for differentiating the signal from the attenuator 42 to catch the falling edge of the pulse. A differentiator 43b, and an adder / subtractor 44 that adds and subtracts the signal 404 from the first differentiator 43a and the signal 405 from the second differentiator 43b to output a short pulse signal 406 are provided.

  The node voltage of each part of the pulse generation circuit according to the present invention will be described below. The amplitude of the input signal 401 is A. The signal 402 from the phase shift circuit 41 can generate a shorter pulse due to the phase fluctuation of the phase shift circuit 41, indicating that the input signal 401 has been delayed by t1 by passing through the phase shift circuit 41. . This signal 402 becomes the input signal of the attenuator 2.

The signal 404 of the first differentiator 43a has an amplitude of A × ATT (attenuation rate) at time t1. The signal 403 from the attenuator 42 is adjusted so that the input of the second differentiator 43b is A × ATT. The attenuation rate (ATT) of the attenuator 42 is 1 or less.
The output signal 405 of the second differentiator 43 b is input to the adder / subtractor 44. Since the first differentiator 43a and the second differentiator 43b have the same structure, the operation is not affected even if the order of the attenuator 42 and the second differentiator 43b is changed. The slopes of the signal 404 from the first differentiator 43a and the signal 405 from the second differentiator 43b are such that τ = R1C1 when the time constant τ of the differentiator comprising the capacitive element C1 and the resistive element R1 is equal. It depends on.

  Further, the output signal 406 that has finished addition / subtraction between the output 404 of the first differentiator 43a and the output 405 of the second differentiator 43b is an output that has undergone addition / subtraction compared to the signal 404 of the first differentiator 43a. The Paris width of the signal 406 is narrower and the falling edge is sharper. That is, the short pulse output signal 406 output from the subtractor 44 is equal to the amplitude of the signal 404 from the first differentiator 43a and the second differentiation at the timing when the signal 405 from the second differentiator 43b rises. By adjusting the attenuator 42 so that the peak amplitude of the signal 405 from the attenuator 43b is the same, a short pulse with a sharp falling edge can be obtained.

  FIG. 34 is a circuit configuration diagram for explaining a pulse signal processing circuit in a fifth embodiment of the pulse generating circuit according to the present invention. In the figure, reference numeral 50 is a pulse signal processing circuit, 51 is a phase shift circuit, 52 is an attenuator, 53a is a first variable phase differentiator, 53b is a second variable phase differentiator, and 54 is an adder / subtractor. Is shown. That is, the first differentiator 43a and the second differentiator 43b shown in FIG. 33 are composed of the first variable phase differentiator 53a and the second variable phase differentiator 53b.

  As in the fourth embodiment, the pulse generation circuit according to the fifth embodiment is a pulse generation circuit that generates a short pulse signal by operating intermittently with a control signal. The first variable phase differentiator 53a directly differentiates the input signal 501 to capture the rising edge of the pulse, and the phase is varied by the first time constant adjustment signal 509. The phase shift circuit 51 determines the pulse width by adjusting the phase fluctuation amount of the input signal 501 by the phase fluctuation amount adjustment signal 507.

  The attenuator 52 adjusts the amplitude of the signal 502 from the phase shift circuit 51 by a gain adjustment signal 508. The second variable phase differentiator 53b differentiates the signal 503 from the attenuator 52 to capture the falling edge of the pulse, and the phase is varied by the second time constant adjustment signal 510. The subtractor 54 subtracts the signal 504 from the first variable phase differentiator 53a and the signal 505 from the second variable phase differentiator 53b to output a short pulse signal.

As described above, the pulse generation circuit according to the fifth embodiment uses the two variable phase differentiators 53a and 53b, and can arbitrarily set the shape of the envelope between the pulse edges. The time constants of the two variable phase differentiators 53a and 53b are changed by the first time constant adjustment signal 509 and the second time constant adjustment signal 510.
The node voltage of each part of the pulse generation circuit according to the present invention will be described below. The amplitude of the input signal 501 is A. The signal 502 from the phase shift circuit 51 can generate a shorter pulse due to the phase fluctuation of the phase shift circuit 51, indicating that the input signal 501 has been delayed by t1 by passing through the phase shift circuit 51. . This signal 502 becomes the input signal of the attenuator 52.

Further, it is preferable that the time constant of the signal 504 of the first variable phase differentiator 53a is selected to be larger than the time constant of the signal 505 from the second variable phase differentiator 53b from the viewpoint of making the pulse waveform close to a rectangle. Similar to the fourth embodiment, the output amplitude of the first variable phase differentiator 13a at t = t1 is A × ATT (attenuation rate).
The signal 503 from the attenuator 52 is adjusted so that the input of the second variable phase differentiator 53b is A × ATT.

The time constant of the output signal 505 of the second variable phase differentiator 53b is selected to be smaller than the time constant of the first variable phase differentiator 53a. In the fifth embodiment, as in the fourth embodiment, even if the order of the attenuator 52 and the second variable phase differentiator 53b is changed, the operation is not affected.
The output signal 506 after the addition and subtraction of the signal 504 of the first variable phase differentiator 53a and the signal 505 of the second variable phase differentiator 53b has a time constant of the first variable phase differentiator 53a. Since it is larger than the time constant of the variable phase differentiator 53b of 2, a low frequency signal of + exists in the region of t> t1. On the other hand, the shape of the pulse is close to a rectangle, and it can be seen that the operation is as intended.

FIG. 35 is a circuit configuration diagram for explaining a pulse signal processing circuit in Embodiment 6 of the pulse generating circuit according to the present invention. In the figure, reference numeral 60 is a pulse signal processing circuit, 61 is a differentiator, 62 is an integrator, 63 is a first high-pass filter (HPF), and 64 is an adder / subtracter.
The pulse signal processing circuit 60 according to the sixth embodiment includes a differentiator 61, an integrator 62, a first high-pass filter (HPF) 63, and an adder / subtractor 64.

  The pulse generation circuit of the present invention is a pulse generation circuit that generates a short pulse signal by operating intermittently by a control signal. The differentiator 61 differentiates the first input signal 601 to capture the rising edge of the pulse. The integrator 62 integrates a second input signal 602 having a phase opposite to that of the first input signal 601 input to the differentiator 61. The first high-pass filter 63 limits the band of the signal 604 from the integrator 62 by the reference signal level 608.

The adder / subtractor 64 adds and subtracts the signal 603 (605) from the differentiator 61 and the signal 606 from the first high-pass filter 63 to output a short pulse signal 607. In the sixth embodiment, the signal 603 from the differentiator 61 is input to the adder / subtractor 64 as a signal 605 without passing through the first high-pass filter 63.
The differentiator 61 may be an RC differentiator or an LC differentiator. The integrator 62 has an integrator configuration including a resistance element and a capacitance element. The first high-pass filter 63 may be a programmable integrator and includes a resistance element and a capacitance element.

The adder / subtractor 64 has a directional coupler or hybrid ring configuration. Further, a second high-pass filter (not shown) that limits the band of the signal from the differentiator 61 may be provided between the differentiator 61 and the adder / subtractor 64. At least one of the differentiator 61, the integrator 62, and the first high-pass filter 63 is composed of a passive element.
That is, the pulse signal processing circuit 60 differentiates the first input signal 601 to catch the rising edge of the pulse, and the second input having the opposite phase to the first input signal 601 input to the differentiator 61. An integrator 62 that integrates the signal 602, a high-pass filter 63 that limits the band of the signal from the integrator 62 by the reference signal level 608, and a signal 603 from the differentiator 61 and a signal 605 from the high-pass filter 63 are added and subtracted. And an adder / subtractor 64 for outputting a short pulse signal 607.

  With such a configuration, at least one of the differentiator, the integrator, the high-pass filter, and the adder / subtractor constituting the pulse generation circuit is configured by a passive element, thereby minimizing current consumption and distortion. In addition, since the input signal is an operation signal, it is possible to realize a pulse generation circuit that is friendly to the surrounding environment in consideration of unnecessary radiation.

The node voltage of each part of the pulse generation circuit according to the present invention will be described below. The amplitude of the first input signal 601 is + A. The amplitude of the second input signal 602 is -A. The maximum value of the signal 603 from the differentiator 61 is + A, and asymptotically approaches 0 with its time constant τ ₁ = R ₁ C ₁ . The amplitude at t = t1 is E. Further, the signal 605 after passing through the first high-pass filter 63 of the signal 603 from the differentiator 61 is the same as the signal 603 because there is no influence.

Further, the signal 604 from the integrator 62 is asymptotic to -A with t = 0 and 0 with a time constant τ ₂ = R ₂ C ₂ . The value of R ₂ C ₂ is designed so that the amplitude at t = t1 is −E. The signal 606 from the first high-pass filter 63 is a signal after passing through the first high-pass filter 63 of the signal 604 from the integrator 2, and the time when the output 606 starts asymptotically toward 0 is t2. And

  The signal 607 from the adder / subtractor 64 has passed through the first high pass filter 63 of the signal 603 from the differentiator 61 and the first high pass filter 63 of the signal 604 from the integrator 62. This is an output signal obtained by adding the subsequent signal 606. Since the amplitude at t = t1 is + E for the signal 605 and −E for the signal 606, the amplitude is 0 for the output signal 607. Thus, the pulse width of the output signal 607 of the present invention can be made shorter than the signal 603 of the differentiator 61.

  FIG. 36 is a circuit configuration diagram for explaining a pulse signal processing circuit in a seventh embodiment of the pulse generating circuit according to the present invention. In the figure, 70 is a pulse signal processing circuit, 71 is a differentiator type variable phase circuit (variable phase differentiator), 72 is an integrator type variable phase circuit (variable phase integrator), 73 is an attenuator (Attenuator), Reference numeral 74 denotes a programmable high-pass filter (HPF), and 75 denotes a common mode extraction circuit. That is, the pulse generation circuit shown in FIG. 36 includes a differentiator variable phase circuit 71, an integrator variable phase circuit 72, an attenuator 73, a programmable high-pass filter 74, and a common mode extraction circuit 75.

  In the pulse generation circuit according to the seventh embodiment, the differentiator 61 and the integrator 62 in the sixth embodiment shown in FIG. 35 are each provided with a phase variable function so that the differentiator variable phase circuit 71 and the integrator variable phase circuit. 72, a gain adjusting function by the attenuator 73 is provided to the output of the integrator type variable phase circuit 72, and a common mode extraction circuit 75 is used instead of the adder / subtractor 64.

The pulse generation circuit according to the seventh embodiment is a pulse generation circuit that generates a short pulse signal by operating intermittently with a control signal, as in the sixth embodiment.
The differentiator type variable phase circuit 71 is phase-variable by a phase change amount control signal 709 and differentiates the first input signal 701 to capture the rising edge of the pulse. Further, the integrator-type variable phase circuit 72 is phase-variable by the phase change amount control signal 709 and receives a second input signal 702 having a phase opposite to that of the first input signal 701 input to the differentiator-type variable phase circuit 71. To integrate. The attenuator 73 adjusts the amplitude of the signal 704 from the integrator-type variable phase circuit 72 by the gain adjustment signal 710, and has a configuration of a resistance tap including a plurality of resistance elements and a plurality of switches.

  The programmable high-pass filter 74 limits the band of the signal 705 from the attenuator 73 by the reference signal level 711. The common mode extraction circuit 75 outputs the short pulse signal 708 by adding and subtracting the signal 703 from the differentiator variable phase circuit 71 and the signal 707 from the programmable high-pass filter 74 as inputs. Reference numeral 75 denotes a resistance division configuration including a plurality of resistance elements. The common mode extraction circuit 15 includes first and second common-source amplifiers.

  As described above, the pulse generation circuit according to the seventh embodiment can arbitrarily select the pulse width obtained by combining the phase variable function and the attenuator. Further, by using the common mode extraction circuit, signal processing independent of the signal frequency can be performed, and the circuit can be widened. The purpose of the seventh embodiment is to minimize the surplus signal generated in the vicinity of t = t2 of the output signal 607 from the adder / subtractor 64 in the sixth embodiment.

The node voltage of each part of the pulse generation circuit according to the present invention will be described below. The amplitude of the first input signal 701 is + A. The amplitude of the second input signal 702 is -A. The first input signal 701 and the second input signal 702 constitute a differential input.
Further, the maximum value of the signal 703 from the differentiator variable phase circuit 71 is + A, and asymptotically approaches 0 with its time constant. The amplitude at t = t1 is A / 2. Further, the signal 704 from the integrator type variable phase circuit 72 becomes 0 at t = 0, and asymptotically approaches -A with its time constant. The phase of the integrator-type variable phase circuit 72 is changed in phase so that the time when the amplitude of the differentiator-type variable phase circuit 71 is A / 2 and the time when the amplitude of the integrator-type variable phase circuit 72 is maximum are the same. Adjustment is performed with a control signal 709. That is, the time constant of the integrator variable phase circuit 72 is adjusted using the phase change amount control signal 709 so that the amplitude of the signal 704 is approximately −A at t = t1.

  Further, the signal 705 from the attenuator 73 has an amplitude of −A / 2 at the time t1. That is, the gain adjustment signal 710 is used to adjust the integrator variable phase circuit 72 so that the amplitude is halved. Further, the signal 707 from the programmable high-pass filter 74 increases or decreases the tail length of the signal 707 by increasing or decreasing the magnitude of R of the programmable high-pass filter 74 using the phase change amount control signal 709. A portion (tail portion) that gradually approaches 0 in this waveform is referred to as “tail”. The short pulse signal 708 output from the common mode extraction circuit 75 adjusts the time constant of the programmable high-pass filter 74 and cancels tail. That is, tail is adjusted using the phase change amount control signal 709, and adjustment is performed so that components after t> t1 of the short pulse signal 708 become zero. Therefore, the short pulse signal 708 output from the common mode extraction circuit 75 is shorter than the pulse width of the signal 703 from the differentiator variable phase circuit 71.

  As described above, the pulse signal processing circuits 40, 50, 60, and 70 shown in FIGS. 33 to 36 are connected to the balun circuit with a center tap and the double balanced mixer circuit, so that the pulse generation circuit as in the present invention is provided. With such a configuration, the same effects as those of the pulse generation circuit described in the first to third embodiments can be obtained.

1 pulse signal processing circuit 2 balun circuit 3 mixer circuit 11, 61 differentiator 12, 62 integrator 13, 23, 41, 51 phase shift circuit 14, 24, 42, 52, 73 attenuator 15, 25 3-input adder / subtractor 15a , 15b 2-input adder / subtractor 16, 26, 34 Center-tapped balun circuits 17, 27, 35 Double balanced mixer circuit 20, 30, 40, 50, 60, 70 Pulse signal processing circuit 21, 31, 71 Differentiator type variable Phase circuit (variable phase differentiator)
22, 32, 72 Integrator type variable phase circuit (variable phase integrator)
33, 44, 54, 64 Adder / Subtractor 43a First Differentiator 43b Second Differentiator 53a First Variable Phase Differentiator 53b Second Variable Phase Differentiator 63 First High Pass Filter (HPF)
74 Programmable High Pass Filter (HPF)
75 Common Mode Extraction Circuit 101 Oscillation Circuit 102 Control Signal Generation Circuit 103 Intermittent Multiplication Circuit 104 Filter 105 Output Terminals 201-204 Signal Waveform

Claims (20)

In the pulse generating circuit,
And at least one differentiator capture rise of the pulse by differentiating the input signal, and a pulse signal processing circuit and a subtracter for outputting a pulse signal by subtracting the signals from at least the differentiator,
A balun circuit for generating a differential signal of an arbitrary DC level to input pulse signal from the pulse signal processing circuit,
And a double balanced mixer circuit for generating a differential pulse signal by superimposing a carrier on the differential signal generated from the balun circuit. The balun circuit is
A primary coil before Kipa pulse signal is input,
A secondary coil that is adjacent to the primary coil and outputs the differential signal;
The pulse generation circuit according to claim 1, further comprising: a center tap that sets the DC level.   3. The pulse generation circuit according to claim 1, wherein the balun circuit further includes a variable capacitance circuit that suppresses a high frequency by using LC tuning. Pulse generating circuit according to claim 2 or 3, wherein the impedance ratio of the secondary coil with respect to the primary coil is two or more. The pulse signal processing circuit is
A differentiator for differentiating the first input signal; an attenuator for adjusting the amplitude of the signal from the differentiator; an integrator for integrating the first input signal; and an antiphase of the first input signal. a phase shift circuit for adjusting the variation of the phase of the second input signal, a Kipa pulse signal before by adding the signals from the signal and the phase shift circuit from the signal and the integrator from the attenuator pulse generating circuit according to any one of claims 1 to 4, characterized that an output to the adder-subtracter. 6. The pulse generation circuit according to claim 5 , wherein the differentiator is a variable phase differentiator. 7. The pulse generation circuit according to claim 5 , wherein the integrator is a variable phase integrator. Pulse generating circuit according to any one of claims 1 to 7 wherein the adder and subtracter, characterized in that a configuration of a directional coupler or a hybrid ring. Pulse generating circuit according to any one of claims 1 to 8 wherein at least one of the differentiator and the integrator and the phase shift circuit and the attenuator is characterized in that it consists of a passive element. The pulse signal processing circuit is
A differentiator for differentiating the first input signal; an integrator for integrating a second input signal having an opposite phase to the first input signal; and a signal from the differentiator and a signal from the integrator are added. pulse generating circuit according to any one of claims 1 to 4, characterized in that it comprises a subtractor for previous output Kipa pulse signals. The pulse generation circuit according to claim 10 , wherein the differentiator is a variable phase differentiator. 12. The pulse generation circuit according to claim 10 , wherein the integrator is a variable phase integrator. 13. The pulse generation circuit according to claim 10, 11 or 12 , wherein the adder / subtracter has a configuration of a directional coupler or a hybrid ring. Pulse generating circuit according to any one of claims 11 to 13 wherein at least one of the differentiator and the integrator, characterized in that it consists of a passive element. The pulse signal processing circuit is
A first differentiator that directly differentiates an input signal to capture a rising edge of a pulse; a phase shift circuit that determines a pulse width by adjusting a phase fluctuation amount of the input signal using a phase fluctuation amount adjustment signal; From an attenuator for adjusting the amplitude of the signal from the phase shift circuit by a gain adjustment signal, a second differentiator for differentiating the signal from the attenuator to capture the falling edge of the pulse, and the first differentiator pulse generating circuit according to any one of claims 1 to 4, characterized in that it comprises a signal between the adder-subtracter for outputting a pulse signal and a signal by adding or subtracting from the second differentiator. 16. The pulse generation circuit according to claim 15 , wherein the first and second differentiators are variable phase differentiators. The pulse signal processing circuit is
A differentiator that differentiates the first input signal to capture the rising edge of the pulse, an integrator that integrates a second input signal that is opposite in phase to the first input signal that is input to the differentiator, and the integrator a high-pass filter that band-limited signal by a reference signal level from a characterized in that it comprises a subtractor for outputting a signal with pulse signals and a signal by adding or subtracting from said high pass filter from said differentiator pulse generating circuit according to any one of claims 1 to 4. 18. The pulse generation circuit according to claim 17 , wherein the differentiator is a variable phase differentiator, the integrator is a variable phase integrator, and the high-pass filter is a programmable integrator. The pulse generation circuit according to claim 17 or 18 , wherein the adder / subtractor has a configuration of a common mode extraction circuit. The pulse generation circuit according to claim 19 , wherein the common mode extraction circuit includes first and second common-source amplifiers.

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