JP5929587B2 - Duplicate product judgment circuit, integrated circuit device having the same, and duplicate product judgment method - Google Patents

Description

  The present invention relates to a duplicated article determination circuit, an integrated circuit device having the same, and a duplicated article determination method.

  The duplicate product determination circuit is a circuit that reverse-engineers a regular integrated circuit (LSI), analyzes the LSI structure, and determines that the product is a duplicate product manufactured based on the analysis result.

  In recent years, third-party products that use LSIs that replicate legitimate LSIs have been regarded as problems. For example, a replica of a mobile phone SIM card or the like has a large economic loss because it can be used illegally by attaching it to the mobile phone. In particular, in recent years, computer tools have been developed that automatically reproduce circuit structures from photographs of LSI multi-layer patterns, and countermeasures against illegal copies are becoming increasingly important.

  Various means have been proposed for detecting such illegally manufactured copies. For example, Patent Documents 1, 2, 3 and the like.

JP-T 09-501529 JP 2003-233537 A JP 2003-216499 A

  However, when the LSI structure is analyzed by a reverse engineer, it is not easy to prevent the same replica product from being manufactured, and if the configuration is the same as the regular product, the replica product may be detected. It's not easy.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a duplicate product determination circuit capable of easily detecting a replica product of an LSI, an integrated circuit device having the same, and a determination method thereof.

The first aspect of the duplicate product determination circuit is a copy product judgment circuit built in the integrated circuit device to be judged,
A pair of wires to which signals are input;
A ferroelectric capacitor provided between the wiring pair;
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to the wiring pair, and the ferroelectric capacitor has a polarization state corresponding to the first signal. After that, a second signal having a potential opposite to that of the first signal is input to the wire pair, and whether the signal is a genuine product based on the signal of the wire pair at a predetermined timing after the input. A determination is made as to whether it is a duplicate.

  According to the first aspect, a replica of LSI can be detected.

It is a figure which shows the structure of the replica determination circuit in this Embodiment. It is a figure explaining operation | movement of the duplicate determination circuit in this Embodiment. It is another figure explaining operation | movement of the duplicate determination circuit in this Embodiment. It is a figure explaining the determination operation | movement by the duplicate product determination circuit of FIG. It is a figure which shows the determination process of the duplicate determination circuit in 1st Embodiment. It is a figure which shows the determination process of the duplicate determination circuit in 1st Embodiment. It is a figure which shows an example of the system which has LSI and the control part which have the duplicate determination circuit in this Embodiment. 3 is a configuration diagram of a duplicate product determination circuit 3. FIG. It is a figure which shows the determination operation | movement (authentication operation | movement) whether LSI9 by the host computer 10 is a regular product or a replication product. It is a figure which shows the determination operation | movement (authentication operation | movement) whether LSI9 by the host computer 10 is a regular product or a replication product. FIG. 6 is a timing chart of an operation (authentication operation) for determining whether the LSI 9 is a genuine product or a duplicate product by the host computer 10. It is a circuit diagram of a duplicate product determination circuit unit in the case of a duplicate product. It is a figure which shows the determination operation | movement (authentication operation | movement) whether the host computer 10 is LSI9 regular goods or a replication goods. FIG. 6 is a timing chart of the operation (authentication operation) for determining whether the host computer 10 is a genuine product or a duplicate product. It is a figure which shows the duplicate detection operation in 2nd Embodiment. It is a flowchart figure of the duplicate detection operation | movement in 2nd Embodiment. It is a figure which shows an example of the system which has LSI and the control part which have the duplicate determination circuit in 2nd Embodiment. 2 is a circuit diagram of a clock selection circuit 11. FIG. It is a figure which shows the determination operation (authentication operation | movement) whether LSI9 by the host computer 10 is a regular product or a replication product. It is a figure which shows the determination operation | movement (authentication operation | movement) whether LSI9 by the host computer 10 is a regular product or a replication product. FIG. 6 is a timing chart of an operation (authentication operation) for determining whether the LSI 9 is a genuine product or a duplicate product by the host computer 10. It is a figure which shows the determination operation | movement (authentication operation | movement) whether LSI9 by the host computer 10 is a regular product or a replication product. FIG. 6 is a timing chart of a determination operation (authentication operation) by the host computer 10 as to whether the LSI 9 is a regular product or a copy product. It is a circuit diagram of the duplicate product determination circuit unit in the third embodiment. It is a timing chart figure which shows the determination operation | movement by the replica determination circuit in 3rd Embodiment. It is a timing chart figure at the time of performing said process S21-S24 in the example of 1st Embodiment. It is a figure which shows the example of data written in the memory used for the duplicate determination operation | movement in 4th Embodiment. It is a figure which shows the latch data AL in process S33 in each address at the time of performing the duplicate determination operation | movement in 4th Embodiment. It is a figure which shows LSI with a duplicate determination circuit and host computer in 5th Embodiment.

  FIG. 1 is a diagram showing a configuration of a duplicate product determination circuit in the present embodiment. The duplicate product determination circuit has a ferroelectric capacitor FC between a signal wiring to which a signal corresponding to data A is input and a signal wiring to which a signal corresponding to data B is input. A latch circuit such as a flip-flop FF is included. A latch clock CLK is supplied to the latch circuit FF by a control circuit (not shown). The latch circuit FF latches the signal level of the signal wiring in response to the edge of the latching clock CLK after a predetermined time from the signal input of the data A and B. It is determined whether or not the product is a duplicate based on the latch data corresponding to the latched signal level.

  The duplicate product determination circuit shown in FIG. 1 has a switch SW between the ferroelectric capacitor FC and the signal wiring. Then, as shown in FIG. 1A, the switch SW is turned on when the duplicate product determination is performed, and the ferroelectric capacitor FC is connected between both signal wirings. Further, as shown in FIG. 1B, the switch SW is made non-conductive (off) during normal operation to disconnect the ferroelectric capacitor FC from both signal wires. This avoids an increase in the parasitic capacitance of the signal wiring during normal operation.

  Therefore, when the duplicate product determination circuit is a duplicate product judgment dedicated circuit, it is not necessary to provide the switch SW, and the ferroelectric capacitor FC may be directly connected to both signal wirings.

  The ferroelectric capacitor FC has the property of being polarized in the direction of the electric field when an electric field is applied between the electrodes and maintaining the polarization state even when the application of the electric field is stopped. Furthermore, when a voltage in the same direction as the polarization direction is applied, the capacitor capacity appears small, and when a voltage in the direction opposite to the polarization direction is applied, the capacitor capacity appears large.

  The capacitance characteristics of this ferroelectric capacitor cannot be obtained simply from a photograph of an LSI, and it is impossible from a photograph image to manufacture a ferroelectric capacitor having the same characteristics. Therefore, the duplicate product determination circuit of the present embodiment uses the capacitance characteristics of the ferroelectric capacitor to determine whether the LSI is a regular product or a duplicate product. The principle will be described with reference to FIG.

  FIG. 2 is a diagram for explaining the operation of the duplicate product determination circuit in the present embodiment. First, as a basic configuration of the duplicate product determination circuit, a circuit having a ferroelectric capacitor FC between a pair of signal wirings netA and netB is shown in the upper left of FIG. The hysteresis characteristics of the interelectrode voltage V and the charge Q of the ferroelectric capacitor FC are shown. This hysteresis characteristic is a capacitance characteristic that varies depending on the manufacturing parameters of the ferroelectric film of the ferroelectric capacitor FC.

  As shown in (1) in Fig. 2, when data 1 (H level) is input to signal wiring netA and data 0 (L level) is input to netB, an electric field is applied to ferroelectric capacitor FC in the direction of the downward arrow. And polarization occurs. At this time, if the downward electric field is made to correspond to the negative voltage, the polarization state of the ferroelectric capacitor transits from the zero point H1 or H3 of the electric field on the hysteresis characteristic curve to the negative voltage point H2.

  After that, as shown in (2) in FIG. 2, when both signal lines netA and netB are set to data 0 (L level), the electric field is zero in the ferroelectric capacitor, and the point H3 on the hysteresis characteristic curve is reached. Transitions and a downward polarization state remains.

  When the signal wiring netA transitions from the state (2) in FIG. 2 to the data 1 (H level) and netB data 0 (L level) as shown in (3), it is applied to the ferroelectric capacitor. Since the electric field direction and the polarization direction coincide with each other, the amount of charge from the signal wiring netA to the ferroelectric capacitor FC is small, and the H level signal of the signal wiring netA rises without much delay. That is, on the hysteresis characteristic polarity, the transition is from the point H3 to the point H2, and the change in the amount of charge in the ferroelectric capacitor corresponding to the vertical axis is small.

  On the other hand, when the signal wiring netA transitions to the data 0 (L level) and netB data 1 (H level) state from (2) in FIG. 2 to (4), it is applied to the ferroelectric capacitor. Therefore, the charge direction from the signal line netA to the ferroelectric capacitor FC is large, and the H level signal of the signal line netB rises with a large delay. That is, on the hysteresis characteristic polarity, the transition is from the point H3 to the point H4, and the amount of charge in the ferroelectric capacitor corresponding to the vertical axis is largely changed.

  As described above, after the H and L level signals are input to the pair of signal wirings as shown in (1) and (2) in FIG. 2 to form a polarization state corresponding to the signal in the ferroelectric capacitor FC, ( When the same signal as (1) is input to a pair of signal wires as in 3), the signal delay is small, and the signal wire netA becomes H level at time t1 after the input. Conversely, after (1) and (2), if a signal opposite to (1) is input to a pair of signal wires as shown in (4), there will be a lot of signal delay, and netB will be Still at L level.

  The difference in the delay characteristics depends on the hysteresis characteristics of the ferroelectric capacitor. Therefore, if the voltage change of the pair of signal wirings is checked based on the correct delay characteristic of the regular product, a duplicate product having a delay characteristic different from that of the regular product can be detected.

  The detection method is (4) after (1) and (2) in FIG. 2 to detect the L level, and then after (5), the (4) state (that is, the (4) state is repeated again. This is a method for confirming that the H level is detected by inputting the same signal. The L level of the signal wiring that rises with a delay when a reverse signal is input to a pair of signal wirings is detected, and the H level of the signal wiring that rises without a delay when the same signal is input to a pair of signal wirings Is detected. Since the detection timing t1 corresponds to the characteristics of a regular ferroelectric capacitor, in a duplicated product having characteristics different from those of a regular product, the signal wiring is different from the voltage level of the signal wiring expected for the regular product. Are detected. For example, when the characteristic of the ferroelectric capacitor of the replica is small, the two detection levels are H and H levels, and conversely, when the delay is large, the detection levels are L and L levels.

  Note that the voltage between the ferroelectric capacitors FC is 0V even if the L, L level or H, H level of the same potential is applied to the signal wiring netA, netB after (1) (2) in FIG. Therefore, the polarization state does not change.

  FIG. 3 is another diagram for explaining the operation of the duplicated article determination circuit in the present embodiment. In the duplicate product determination circuit shown in FIG. 3, as in FIG. 1, a switch SW, a ferroelectric capacitor FC, and a switch SW are provided in series between a pair of signal wirings netA and netB. At the time of authentication to detect a duplicate product, as shown in Fig. 3 (1), both switches SW are turned on, a signal is sent to a pair of signal wires netA and netB (data 1 (H level) to netA, netB to Data 0 (L level) is input to set the ferroelectric capacitor FC in a downward polarization state. This is the polarization creation process. After that, as shown in FIG. 3 (2), with both switches SW turned on, a signal opposite to (1) is input to the pair of signal wires netA and netB, and the rise of the signal wire netB is delayed. On the contrary, the genuine product and the duplicate product are discriminated based on whether or not it is detected that the same signal as in (1) is input and the rise is not delayed. This is the authentication process.

  On the other hand, as shown in FIG. 3 (3), during normal operation, both switches SW are turned off so that the capacitance of the ferroelectric capacitor FC cannot be seen in the signal wires netA and netB, and the signal delay of the signal wires is reduced. lose.

  FIG. 4 is a diagram illustrating a determination operation by the duplicate product determination circuit of FIG. Signals netA and netB are indicated as A and B in FIG. 4, and signals latched by the latch circuit FF are indicated as AL and BL. In FIG. 4, data 1 (H level) and data 0 (L level) are respectively input to the signal wiring netA and netB in the polarization creation process, and the signal waveforms for the four types of signal combinations in the subsequent authentication process are shown. , Latch signals AL and BL are shown. The latch timing is a time t1 that is a predetermined time after the signal input time t0 to the signal wiring in the authentication process. This time t1 corresponds to the delay time of the signal wiring based on the characteristics of the ferroelectric capacitor, and there is no delay when the same signal is input as when creating the polarization, and the delay when the opposite signal is input. It is a timing between existing timings. Thereby, it is possible to detect the case with delay and the case without delay using the timing of time t1.

  When the L level is input to both signal wirings in the authentication process (the first line in FIG. 4), no electric field is applied to the ferroelectric capacitor, and no charge is charged to or discharged from the ferroelectric capacitor. The wirings A and B remain at the L level, and the latch signals AL and BL are both at the L level. Similarly, when the H level is input to both signal wirings in the authentication process (third line in FIG. 4), there is no charge / discharge of the electric field, both signal wirings A and B rise without delay, and latch signals Al, Both BLs go high. A combination of these input signals is not used in the authentication process.

  In the present embodiment, when the same signal H level and L level as in the polarization creation process are input to both signal wirings A and B in the authentication process (second line in FIG. 4), the polarization direction of the ferroelectric capacitor, Since the electric field directions applied by the signals coincide with each other, the rise of the signal on the signal wiring A is not delayed. Therefore, the latch signals AL and BL are at the H and L levels.

  On the contrary, when the signal L level and H level opposite to the polarization creation process are input to both signal wirings A and B in the authentication process (fourth line in FIG. 4), depending on the polarization direction of the ferroelectric capacitor and the signal Since the applied electric field direction is reversed, the signal rise of the signal wiring B is delayed. Therefore, the latch signals AL and BL at the time t1 after a predetermined time from the signal input time t0 in the authentication process become L and L levels.

  Therefore, in the duplicate product detection operation, the authentication process in the second and fourth lines in FIG. 4 is used.

  The above is the basic operation of the duplicate product determination circuit in the present embodiment. Specific implementation will be described below.

[First Embodiment]
FIG. 5 and FIG. 6 are diagrams showing the determination process of the duplicate product determination circuit in the first embodiment. 5 and 6 are given the same process numbers.

  5 includes the signal wiring pair shown in FIG. 1, a ferroelectric capacitor FC provided between the signal wiring pair, and a latch circuit FF that latches a signal of the signal wiring. . The switch between the ferroelectric capacitor FC and the signal wiring is not shown for simplicity.

  In FIG. 5, two sets of signal wiring pairs are connected to the data output terminals of the non-volatile memory at A3 / A2 and A1 / A0, respectively. Entered. The latch circuit FF latches the signal wiring signal at a timing after a predetermined time from the output timing of the nonvolatile memory. In addition, in order to input a signal for the authentication operation to the two pairs of signal wirings, a control circuit or a host computer (hereinafter referred to as a control unit) not shown in FIG. And lead. By reading the data written in the write operation, the signal of the written data is input to the signal wiring pair. The operation described below is based on the assumption that a replica product determination circuit is provided on a genuine chip.

  First, in step S1 of FIG. 6, the control unit previously writes, for example, data A [3: 0] = 1010 to address # 00 of the nonvolatile memory, and for example, data A [3: 0] = Write 0110.

  Next, in step S2, the control unit reads data A [3: 0] = 1010 at address # 00 in a state where the switch SW is turned on and the ferroelectric capacitor FC is connected between the signal wiring pair. By this read operation, data H / L and H / L of data 1/0 and 1/0 are output (or input) from the data output terminals A3 / A2 and A1 / A0 to the respective signal wiring pairs. As a result, a downward polarization state is generated in the two ferroelectric capacitors FC. That is, step S2 is a step of generating the polarization state of the ferroelectric capacitor.

  In step S3, for example, the nonvolatile memory and the latch circuit FF are brought into a power-down state, and the voltages of the two signal wiring pairs are once set to 0 V, but the polarization state of the ferroelectric capacitor is maintained.

  After power-on in step S4, in step S5, the control unit reads data A [3: 0] = 0110 at address # 01 with the switch SW turned on. With this read operation, the signals at the data output terminals A2 and A1 rise. In this read operation, the read data A [3: 2] = 01 is a signal opposite to the data A [3: 2] = 10 in the polarization generation step of step S2. Therefore, in the signal wiring connected to the data output terminal A2, since the signal rises while inverting the polarization state of the ferroelectric capacitor FC, the rise of the signal is delayed. As a result, the signal latched by the latch circuit FF at timing t1 is AL [3: 0] = 0010, and A2 is different from A [3: 0] = 0110 output from the data output terminal. However, in the case of a replicated product, the delay time is shortened depending on the characteristics of the ferroelectric capacitor, and there is a possibility that AL [3: 0] = 0010 is not obtained at the timing t1 as in the regular product.

  Next, in step S6, the control unit reads data A [3: 0] = 0110 at address # 01 again with the switch SW turned on. With this read operation, the signals at the data output terminals A2 and A1 rise. In this read operation, the same data as the read data A [3: 0] = 0110 in the immediately preceding step S5 is read. Therefore, since the signal wiring connected to the data output terminal A2 is not accompanied by polarization inversion, the rise of the signal is not delayed. As a result, the signal latched by the latch circuit FF at timing t1 is AL [3: 0] = 0110, which is the same as A [3: 0] = 0110 output from the data output terminal. However, in the case of a replica product, the delay time becomes long even with a rising signal without polarization inversion depending on the characteristics of the ferroelectric capacitor, and AL [3: 0] = 0110 may not be reached like the regular product at timing t1. There is sex.

  In the case of a replicated product, it is very unlikely that the characteristics of the ferroelectric capacitor FC will be the same as those of a regular product, so the data AL [3: 0 latched in the latch circuit FF by the read operation in steps S5 and S6 ] Both do not match the case of the genuine product, so that the duplicate product can be judged.

  Finally, in step S7, the control unit turns off the switch SW and disconnects the ferroelectric capacitor FC from the signal wiring. As a result, during normal operation, the signal wiring signal is not delayed by the ferroelectric capacitor.

  In the example of FIG. 5 described above, a pair of signal wirings connected to the data output terminals A [3: 2] and their ferroelectric capacitors FC are used to determine a replica. Then, the polarization state generation is performed for the pair of signal lines in step S2, the rising characteristic of the signal that reverses the polarization state is determined in step S5, and the polarization state generation is performed in step S5 at the same time. The rise characteristic of the signal that does not invert the polarization state is determined in step S5, and whether the product is a genuine product or a duplicate product is determined based on the determination results in steps S5 and S6.

  However, the data output terminal A [1: 0] can also be judged with higher accuracy by checking that normal data is latched in steps S5 and S6 to determine whether it is a genuine product or a duplicate product. .

  FIG. 7 is a diagram illustrating an example of a system including an LSI having a copy determination circuit and a control unit in the present embodiment. The LSI 9 with a copy determination circuit includes a memory 1 such as a nonvolatile memory, a logic circuit 2 having a predetermined function, and a copy determination circuit 3 connected to the data output terminal A [N: 0] of the memory 1. Have. The logic circuit 2 accumulates data in the memory 1 and performs a predetermined functional operation. Therefore, the logic circuit 2 is connected via the memory 1, the write data bus I [N: 0], the address bus IA [M: 0], and the clock signal line CLK. Further, the read data bus A [N: 0] of the memory 1 is connected to the logic circuit 2 via the duplicate product determination circuit 3. That is, the read data bus A [N: 0] of the memory 1 is connected to the duplicate product determination circuit 3, and the duplicate product judgment circuit 3 and the logic circuit 2 are latched by the latch circuit in the duplicate product judgment circuit 3. They are connected via the AL [N: 0] bus. Further, a control signal Sw for controlling the switch in the duplicate product determination circuit 3 is output from the logic circuit 2.

  On the other hand, the host computer 10 includes an LSI 9 with a copy determination circuit, a write data bus I [N: 0], an address bus IA [M: 0], a clock signal line CLK, and a latch data bus AL [N: 0. ] And connected. Then, the host computer 10 performs the steps S1 to S7 described with reference to FIGS. 5 and 6 as a control unit, and the LSI 9 is properly set based on whether or not the latch data AL [N: 0] matches the expected value. Judge whether it is a product or a copy.

  The memory 1 may be an external memory provided outside the LSI 9. However, the data output terminal of the memory is connected to the signal wiring of the duplicate determination circuit 3. Further, the latch data AL [N: 0] bus of the copy determination circuit 3 may be connected to the host computer 10 without going through the logic circuit 2.

  In this way, the host computer 10 in the system on which the LSI 9 is mounted inputs a predetermined data signal to the duplicate determination circuit 3 and based on the latch signal of the rising signal at a timing corresponding to the characteristics of the ferroelectric capacitor. , It can be determined whether the LSI 9 is a genuine product or a duplicate product.

  FIG. 8 is a configuration diagram of the duplicate product determination circuit 3. In this example, (N + 1) / 2 signal wiring pairs are connected to the duplicate product determination circuit unit 4 for the N + 1 signal wirings of the read data bus A [N: 0]. Further, the clock CLK and the switch control signal Sw are input to the respective duplicate product determination circuit units 4.

  FIG. 8 shows a circuit example of the duplicate product determination circuit unit 4. This circuit is equivalent to the duplicate product determination circuit shown in FIG. That is, the ferroelectric capacitor FC is provided between the signal wiring pair X and Y via the switch SW, and the switch SW is ON / OFF controlled by the control signal Sw. A signal input to the pair of signal lines X and Y is latched by the latch circuit FF at the edge timing of the clock CLK, and a latch signal is output to the latch signal terminals XL and YL.

  In this way, by increasing the number of duplicate product determination circuit units 4, it is possible to determine whether each unit is a regular product or a duplicate product, thereby improving the judgment accuracy.

  FIGS. 9 and 10 are diagrams showing a determination operation (authentication operation) by the host computer 10 as to whether the LSI 9 is a genuine product or a duplicate product. FIG. 11 is a timing chart thereof. The steps S1 to S6 shown in these drawings correspond to the steps S1 to S6 shown in FIGS. 9, 10, and 11 are examples in the case where the LSI 9 is a regular product.

  As shown in FIG. 9, the host computer 10 is connected to the LSI 9 with a copy determination circuit, and controls writing and reading from the host computer 10 to a memory in the LSI 9 or a memory external to the LSI 9. In advance, the host computer 10 turns on the switch SW of the copy determination circuit in the LSI 9.

  First, in steps S1a and S1b, the host computer 10 writes data Data [3: 0] = 1010, 0110 to addresses # 00 and # 01. The former data is data for generating a polarization state in the ferroelectric capacitor, and the latter data is data for authentication. The latter data is also data for generating a polarization state.

  These two writing controls are performed by the write keys 1 and 2 in the host computer 10, for example. The right side of FIG. 9 shows the address Address and data Data [3: 0] on the host side, and the address Address and data Data [3: 0] of the memory in the LSI 9 device.

  Next, in step S2, the host computer 10 reads data Data [3: 0] = 1010 at address # 00. As a result, a polarization state is generated in the ferroelectric capacitor in the direction of the electric field corresponding to the data. On the right side of FIG. 9, the polarization directions between A3-A2 and A1-A0 of the signal wiring A [3: 0] in the replica judgment circuit are indicated by arrows.

  In step S3, the host computer 10 turns off the LSI 9. However, the polarization state of the ferroelectric capacitor is maintained.

  Turning to FIG. 10, the host computer 10 powers on the LSI 9 in step S4. Even in this state, the polarization state of the ferroelectric capacitor does not change.

  In step S5, the host computer 10 reads data Data [3: 0] = 0110 at address # 01. By this read operation, a signal of data Data [3: 0] = 0110 is input to the signal wiring A [3: 0] in the replica judgment circuit, and in particular, between the signal wirings A3 and A2, the polarization generation step S2 and The reverse signal is applied to the signal line A2, and the signal rises while inverting the polarization state. Therefore, the rising edge of the signal is delayed, and the latch data AL [3: 0] latched at the timing t1 is AL [3: 0] = 0010 unlike the read data Data [3: 0] = 0110. That is, the latch data AL [2] = 0 of the signal wiring A2 is different from the read data Data [2] = 1.

  Further, the polarization state of the ferroelectric capacitor is generated by the read operation in step S5. That is, the polarization directions are the A2 to A3 direction and the A1 to A0 direction.

  Thereafter, in step S6, the host computer 10 reads data Data [3: 0] = 0110 at address # 01 again. As a result of this read operation, the signal of data Data [3: 0] = 0110 is again input to the signal wiring A [3: 0] in the replica judgment circuit, and the polarization state is not inverted. Therefore, the rise of the signal is not delayed, and the latch data AL [3: 0] latched at the timing t1 is the same as the read data Data [3: 0] = 0110, and AL [3: 0] = 0110 Become.

  Finally, in step S6a, the host computer 10 determines (or authenticates) whether the LSI is a genuine product or a duplicate product based on the latch data AL [3: 0] in steps S5 and S6.

  As described above, in the case of the regular product, the delay amount of the signal that rises without polarization reversal and the delay amount of the signal that rises while reversing the polarization match the latch timing t1, so that the signal that undergoes polarization reversal is a signal. When input to the wiring, the latch data of the signal wiring of the rising signal is different from the input data, but when the signal that does not reverse polarization is input to the signal wiring, the latch data of the signal wiring of the rising signal is input Same as data.

  FIG. 12 is a circuit diagram of the duplicate product determination circuit unit in the case of a duplicate product. FIG. 9 is a circuit diagram in the case of a copy of the copy determination circuit unit 4 shown in FIG. 8. As is clear from comparison with FIG. 8, the ferroelectric capacitor is not formed in the duplicated product, or the ferroelectric capacitor having the same characteristics as the regular product is not formed.

  FIG. 13 is a diagram showing an operation (authentication operation) for determining whether the host computer 10 is a genuine product or a duplicate product. FIG. 14 is a timing chart thereof. Steps S4 ′, S5 ′, and S6a ′ shown in these drawings correspond to steps S4, S5, and S6a shown in FIGS. FIGS. 13 and 14 are examples in which the LSI 9 is a duplicate product. It is assumed that this replica does not have a ferroelectric capacitor, or the amount of charge required for polarization inversion is smaller than that of a regular product, and the signal rise delay is small.

  Steps S1 to S3 are the same as those in FIG. In step S4 ′, the host computer 10 powers on the LSI.

  Next, in step S5 ′, the host computer 10 reads data Data [3: 0] = 0110 at address # 01. As a result, an L / H level signal is input to the signal wiring A3 / A2. This data Data [3: 2] = 01 is a signal opposite to the data Data [3: 2] = 10 in which the polarization state is generated in the ferroelectric capacitor in the polarization generation step S2. However, since the replica product has either no ferroelectric capacitor or a small amount of charge necessary for polarization inversion, the signal rising delay amount of the signal wiring A2 is small. Therefore, the latch data AL [3: 0] latched at the timing t1 is AL [3: 0] = 0110, which is the same as the read data Data [3: 0] = 0110. Thus, the host computer 10 can determine that the LSI 9 is not a regular product but a duplicate product.

  Therefore, the host computer 10 determines that the LSI 9 is a duplicated product and executes necessary control by the authentication operation in step S6a ′. For example, the operation of a predetermined function using the LSI 9 is stopped.

  Note that, as described above, even in the case of a replica, if the delay of the rise of the signal due to the polarization inversion of the ferroelectric capacitor is large, the latch data will be the same as the regular product, AL [3: 0] = 0010, Judgment may not be possible. However, in that case, the rise delay of the signal not accompanied by polarization inversion is also delayed, and in the read operation of address # 01 in the next step S6, the latch data at timing t1 is AL [3: 0] = 0010. Unlike regular products, it can be judged as a duplicate product.

  On the other hand, both the rise of the signal due to the polarization inversion of the ferroelectric capacitor and the rise of the signal not accompanied by the polarization inversion are small in the replica product, and the latch data in the steps S5 and S6 are both AL [3: 0 ] = 0110, which is the same as the read data, and can be determined as a duplicate in step S5 ′ as shown in FIG.

  In this way, by setting the latch timing t1 between the large delay of the rise of the signal with polarization inversion and the small delay of the rise of the signal without polarization inversion, which depend on the characteristics of the ferroelectric capacitor. Therefore, it is possible to detect a duplicate product that does not have a ferroelectric capacitor having the same characteristics as a regular product.

[Second Embodiment]
In the second embodiment, by utilizing the fact that the rise delay of the signal accompanied by polarization inversion depends on the characteristics of the ferroelectric capacitor, the latch timing is set before and after the rise delay, and two polarizations are performed. A signal accompanied by inversion is input to a pair of signal lines in the replica judgment circuit and latched at different latch timings. In the case of a duplicate product, there is no delay amount between two different latch timings, so that the duplicate product can be detected.

  FIG. 15 is a diagram illustrating a duplicated product detection operation in the second embodiment. FIG. 16 is a flowchart of the duplicate detection operation in the second embodiment. As shown in FIG. 15, the duplicate product determination circuit includes a pair of signal wires A and B, a switch, a ferroelectric capacitor, a switch provided therebetween, and a latch circuit FF. The steps so far are the same as those in FIG.

  A selector SELT for selecting either the clock CLK1 with the earlier timing or the clock CLK2 with the later timing is provided as the clock CLK supplied to the latch circuit FF. The high-speed clock CLK1 is, for example, a clock during normal operation, and the low-speed clock CLK2 is a clock for determining a duplicate product (authentication). It is assumed that the signal wiring pair A, B is connected to the data output terminal of the memory as in the first embodiment.

  With the switch SW turned on in advance, in step S12, A = H level and B = L level are read, H and L level signals are input to the signal wiring pairs A and B, and the ferroelectric capacitors are input. Create a polarization state. Next, in step S13, L and H level signals are input to the signal wiring pair A and B at the rising edge t0 of the clock CLK1, and latched at the next rising edge t1. Since the L and H level signals are input to the signal wiring pair A and B, the signal of the signal wiring B rises while inverting the polarization state. This rise is delayed corresponding to the amount of charge charged to the ferroelectric capacitor. However, since latching is performed at the rising edge t1 of the high-speed clock CLK1, the L level before the signal of the signal wiring B rises is latched, and the latch data AL and BL become L and L levels.

  Next, in step S14, the same operation as in step S12 is performed. That is, the H and L level signals are input to the signal wiring pair A and B, and the polarization state is generated in the ferroelectric capacitor. In step S15, L and H level signals are input to the signal wiring pair A and B at the rising edge t0 of the low-speed clock CLK2, and latched at the next rising edge t1. Also in this case, as in step S13, the signal of the signal wiring B rises while inverting the polarization state. This rise is delayed corresponding to the amount of charge charged to the ferroelectric capacitor. However, since latching is performed at the rising edge t1 of the low-speed clock CLK2, the H level after the signal on the signal line B rises is latched, and the latch data AL and BL become L and H levels.

  In step S16, it is determined that the product is a genuine product based on the latch data AL, BL = L, L and L, H output in steps S13, S15. In step S17, the switch SW is turned off and the normal operation state is restored.

  If it is a replica, the delay of the signal that rises while inverting the polarization state does not enter between the rising edge t1 of the high-speed clock CLK1 and the rising edge t1 of the low-speed clock CLK2, and shifts in either direction. Therefore, a duplicate product can be detected from the latch data.

  FIG. 17 is a diagram illustrating an example of a system including an LSI having a duplicate product determination circuit and a control unit according to the second embodiment. A difference from the configuration shown in FIG. 7 is a clock selection circuit 11 provided in the LSI 9 with a copy product determination circuit. The clock selection circuit 11 selects either the high-speed clock CLK1 used in normal operation or the authentication low-speed clock CLK2 generated in the clock selection circuit 11 and outputs the clock CLK. The clock selection circuit 11 selects one of the clocks based on the selector signal SEL supplied from the logic circuit 2. Other configurations are the same as those in FIG.

  FIG. 18 is a circuit diagram of the clock selection circuit 11. FIG. 18 shows three examples. The clock selection circuit shown in FIG. 18 (1) has a high-speed clock CLK1, a frequency divider composed of a flip-flop FF and an inverter INV that divides the frequency by 1/2, and a high-speed clock CLK1 divided by a select signal SEL. And a selector SELT that selects one of the low-speed clocks CLK2 and outputs the clock CLK.

  The clock selection circuit shown in FIG. 18B has a selector SELT and a delay gate DEL. The delay gate DEL outputs a delayed clock CLK2 by delaying the high-speed clock CLK1 for a predetermined time. Then, the selector SELT selects either the clock CLK1 or CLK2 based on the select signal SEL and outputs it as the clock CLK.

  In the clock selection circuit of FIG. 18 (3), the high-speed clock CLK1 is branched, an inverted signal is generated by the inverter INV, and a signal is applied to the ferroelectric capacitor FC. Therefore, the clock CLK2 in which the rising edge of the clock CLK1 is delayed by the polarization inversion of the ferroelectric capacitor FC is generated. Then, the selector SELT selects either the clock CLK1 or CLK2 based on the select signal SEL and outputs it as the clock CLK.

  Any one of the clock selection circuits described above is provided in the LSI 9 of FIG.

  19 and 20 are diagrams showing a determination operation (authentication operation) by the host computer 10 as to whether the LSI 9 is a regular product or a duplicate product. FIG. 21 is a timing chart thereof. Steps S12 to S15 shown in these drawings correspond to steps S12 to S15 shown in FIGS. 19, 20, and 21 are examples in the case where the LSI 9 is a regular product.

  As shown in FIG. 19, the host computer 10 is connected to the LSI 9 with a copy determination circuit, and controls writing and reading from the host computer 10 to a memory in the LSI 9 or a memory external to the LSI 9. In advance, the host computer 10 turns on the switch SW of the copy determination circuit in the LSI 9.

  First, in steps S11a and S11b, the host computer 10 writes data Data [3: 0] = 1010, 0110 to addresses # 00 and # 01. The former data is data for generating a polarization state in the ferroelectric capacitor, and the latter data is data for authentication.

  Next, in step S12, the host computer 10 reads data Data [3: 0] = 1010 at address # 00. As a result, a polarization state is generated in the ferroelectric capacitor in the direction of the electric field corresponding to the data. On the right side of FIG. 19, the directions of polarization between A3-A2 and A1-A0 of the signal wiring A [3: 0] in the replica judgment circuit are indicated by arrows.

  In step S13, the host computer 10 reads data Data [3: 0] = 0110 at address # 01. By this read operation, a signal of data Data [3: 0] = 0110 is input to the signal wiring A [3: 0] in the replica judgment circuit, and in particular, the signal wiring A3, A2 is opposite to the process S12. The signal rises while the signal wiring A2 inverts the polarization state. Therefore, the rise of the signal is delayed.

  In step S13, the high-speed clock CLK1 is supplied as the clock CLK of the latch circuit, and the signal wiring signal is latched at an early timing t1. Unlike the read data Data [3: 0] = 0110, the latch data AL [3: 0] is AL [3: 0] = 0010. That is, the latch data AL [2] = 0 of the signal wiring A2 is different from the read data Data [2] = 1.

  Turning to FIG. 20, in steps S14 and S15, data having the same address as in steps S12 and S13 is read. However, the clock CLK2 for latching in step S15 is selected as the clock CLK2 having a low speed or a slow rising edge. For this reason, the rise of the signal on the signal wiring A2 is delayed, but the latching clock CLK = CLK2 is slower than CLK1, so the latch data AL [3: 0] becomes AL [3: 0] = 0110. That is, the latch data AL [2] = 1 of the signal wiring A2 is equal to the read data Data [2] = 1.

  As shown in FIG. 21, the time from the data input timing t0 to the latch timing t1 in the step S13 is shorter than the time from the timing t0 to the latch timing t1 in the step S15. Timing t1 is earlier than the delay time of the rising signal accompanied by polarization inversion, and timing t1 in step S15 is later. Therefore, in the case of a regular product, the above-mentioned latch data can be obtained, but in the case of a duplicate product with different characteristics of the ferroelectric capacitor, latch data different from the above is obtained, and the duplicate product is discriminated. be able to.

  FIG. 22 is a diagram showing a determination operation (authentication operation) by the host computer 10 as to whether the LSI 9 is a genuine product or a duplicate product. FIG. 23 is a timing chart thereof. Steps S12 ′ and S13 ′ shown in these drawings correspond to steps S12 and S13 shown in FIG. 19 and FIG. FIGS. 22 and 23 show an example in which the LSI 9 is a replica that has a small rise delay of a signal accompanying polarization inversion.

  In steps S11a ′ and S11b ′, the host computer 10 writes data Data [3: 0] = 1010, 0110 to addresses # 00, # 01. Next, in step S12 ′, the host computer 10 reads data Data [3: 0] = 1010 at address # 00 from the memory, and inputs a read data signal to the signal wiring pair of the duplicate product determination circuit. Thereby, the polarization state of the ferroelectric capacitor connected between the signal wiring pair is formed.

  In step S13 ′, the host computer 10 reads the data Data [3: 0] = 0110 at address # 01 from the memory, and inputs a read data signal to the signal wiring pair of the duplicate determination circuit. As a result, the signal of the signal wiring A [2] rises while inverting the polarization state. Since the rise of this signal is a replica, there is no delay, for example, and the data latched at the latch timing t1 is AL [3: 0] = 0110. That is, the latch data AL [2] of the signal wiring A [2] is also set to 1. As a result, the host computer 10 determines that it is not a regular product but a duplicate product.

[Third Embodiment]
FIG. 24 is a circuit diagram of the duplicate product determination circuit unit according to the third embodiment. FIG. 9 is a circuit diagram corresponding to FIG. 8 of the first embodiment. In the duplicate product determination circuit unit 4 of FIG. 24, four signal wirings A [3: 0] are input, and four latch data are output AL [3: 0].

  The specific configuration of the duplicate product determination circuit unit 4 includes a switch SW, a ferroelectric capacitor FC, and a switch SW between four signal wirings connected to the input terminal W-Z. That is, the ferroelectric capacitors FC are respectively provided between the four pairs of input terminals W / X, X / Y, Y / Z, and Z / W. Therefore, compared with the case where two ferroelectric capacitors FC are provided for four signal wirings as in the first and second embodiments, the number of determination bits is smaller in the third embodiment. As a result, the determination accuracy can be increased.

FIG. 25 is a timing chart illustrating a determination operation by the duplicate product determination circuit according to the third embodiment. FIG. 25 shows a case of a regular product and a case of a duplicate product. The determination operation by the duplicate product determination circuit includes steps S21 to S25 as follows.
S21 (not shown): The host computer writes polarization generation data Data [3: 0] = 1010 to address # 00 in the memory.
S22 (not shown): The host computer writes authentication data Data [3: 0] = 1101 to address # 01 in the memory.
S23: The host computer reads the data Data [3: 0] = 1010 at address # 00 from the memory and inputs it to the signal wiring in the duplicate product determination circuit to generate polarization states in the four ferroelectric capacitors .
S24: The host computer reads the data Data [3: 0] = 1101 at address # 01 from the memory and inputs it to the signal wiring in the duplicate product determination circuit. As a result, the latch data AL [3: 0] is acquired.
S25: The host computer reads the data Data [3: 0] = 1101 at address # 01 again from the memory, and inputs it to the signal wiring in the duplicate product determination circuit. As a result, the latch data AL [3: 0] is acquired.
Based on the latch data in steps S24 and S25, it is determined whether the product is a genuine product or a duplicate product.

  In the case of a regular product, four polarization states are generated in step S23, and are indicated by thick white arrows in FIG. In step S24, when the host computer reads the data Data [3: 0] = 1101 at address # 01 from the memory and inputs it to the signal wiring in the replica judgment circuit, the signal wiring between A2 / A1, A1 / A signal for inverting the polarization state is input between A0. As a result, polarization inversion is performed as indicated by the black arrows, and the signal wirings A2 and A0 become rising signals with polarization inversion, and latch data AL [3: 0] = 1000 is obtained due to the delay characteristics, and the signal wiring A2 , A0 latch data AL [2], AL [0] are different from the read data. Further, in the step S24, the polarization states of the four ferroelectric capacitors are brought into a state corresponding to the read data Data [3: 0] = 1101.

  Further, in step S25, when the host computer reads the data Data [3: 0] = 1101 at address # 01 again from the memory and inputs it to the signal wiring in the replica judgment circuit, the polarization state is present between any of the signal wirings. A signal for inverting is not input. Therefore, the latch data AL [3: 0] = 1101, which is the same as the read data Data [3: 0] = 1101.

  It is determined from the latch data in steps S24 and S25 that the product is a genuine product.

  In the case of a replicated product, a data signal with polarization inversion is input in the above step S24, but there is no ferroelectric capacitor between the wiring signals, or the signal rise characteristics even with polarization inversion There is no delay. As a result, the latch data is AL [3: 0] = 1101, which is the same as the read data. In step S25, the latch data is AL [3: 0] = 1101, which is the same as the read data.

  Therefore, it is determined from the latch data in steps S24 and S25 that the product is a duplicate.

  In the above determination operation, the data for authentication written to the address # 01 can be set to Data [3: 0] = 0101. In this case, in step S24, data signals that cause polarization inversion in the four ferroelectric capacitors are input to the four signal wirings. Therefore, the latch data is AL [3: 0] = 0000, and the latch data AL [2] and AL [0] are different from the read data. Therefore, the determination by 2 bits can be performed as in the above-described determination operation.

  FIG. 26 is a timing chart when steps S21 to S24 are performed in the example of the first embodiment. In this case, only the latch data AL [0] is used for determination unlike the read data. However, if the data at address # 00 is set to 1010 and the data at address # 01 is set to 0101, the latch data AL [2] and AL [0] are different from the read data and can be used for determination.

  In the replica judgment circuit according to the third embodiment, as in the judgment operation of the second embodiment, for example, data 1010 is read to form a polarization state in the ferroelectric capacitor, and then data 0101 is read. The rising signal is latched at the edge of the high-speed clock while inverting all ferroelectric capacitors, and the first data 1010 is read again to form the polarization state, and then the data 0101 is read to invert the ferroelectric capacitors. However, the rising signal may be latched at the edge of the low-speed clock. However, in this case, since the rising signal rises while inverting the two ferroelectric capacitors, the delay amount becomes larger.

[Fourth Embodiment]
FIG. 27 is a diagram illustrating an example of data written in the memory used for the duplicate product determination operation according to the fourth embodiment. In the fourth embodiment, random data is written to each of a plurality of addresses in the memory. In the example of FIG. 27, 8-bit write data A [7: 0] is shown for each 4-bit address (16 addresses). Polarization data is written to address # 0000, and authentication data is written to addresses # 0001-1111.

  The 8-bit data output terminal of the memory is connected to the eight signal wirings of the replica judgment circuit, and the ferroelectric capacitors are provided in the four signal wiring pairs of the eight signal wirings. .

In the copy product determination operation of FIG. 28A, the host computer performs the following operation.
S31: Write the data shown in FIG. 27 into the memory. The data at address # 0000 is data that causes 10101010 and all the ferroelectric capacitors to be polarized, but the data at other addresses is at random.
S32: Read the polarization data at address # 0000 from the memory, and generate the polarization state in the ferroelectric capacitor in the replica judgment circuit.
S33: Read authentication data at address # 0001 and obtain latch data AL [7: 0].
S34: The authentication data at the same address is read again to acquire the latch data AL [7: 0].
S35: Increment the address by one.
The above steps S33, S34, S35 are repeated up to address # 1111.

  FIG. 28 is a diagram showing the latch data AL in step S33 at each address when the duplicate product determination operation in the fourth embodiment is performed. FIG. 28 (1) shows the latch data AL in step S33 when the operations for the addresses # 0000 to # 1111 are performed. Since the latch data AL [7: 0] in step S34 is not accompanied by polarization inversion, it is all the same as the read data A [7: 0] shown in FIG.

  In the figure, when read data accompanied by polarization inversion is supplied, the case where the latch data becomes 0 instead of 1 due to the delay due to the ferroelectric capacitor is surrounded by a thick frame. For example, if address # 0000 is read after address # 0000 is formed and then address # 0001 is read, the ferroelectric capacitor of the signal line pair for data A [1: 0] is inverted in polarization as shown in FIG. The Therefore, the rise of the signal by data A [0] is delayed. Therefore, the latch data AL [0] = 0. In the read data at address # 0010, there is no polarization inversion of the ferroelectric capacitor, and all the latch data AL is the same as the read data A. When the address # 0011 is read, the read data A [5: 4], A [3: 2], A [1: 0] are inverted from the data obtained when the ferroelectric capacitor was previously polarized. Since it is data, polarization inversion occurs. As a result, the latch data AL [4], A [2], A [1] are different from the read data.

  According to this determination operation, when all the latch data different from the read data indicated by the thick frame in FIG. 28 (1) match, it is determined as a genuine product, and when even one of them does not match, it is determined as a duplicate product. . The number of bits that can be used for authentication increases and the determination accuracy increases.

  In the determination operation of FIG. 28 (2), after writing in the above steps S31 and S32, after reading the data of address # 0001 in step S33, the address is incremented and the data is changed to # 1111. This is a leading example. The latch data AL [7: 0] at address # 1111 is different from the latch data in FIG. That is, the latch data in step S34 differs depending on whether or not the polarization state by the previous read data is inverted.

  In this way, the data to be latched can be made different by writing data in advance to a large number of addresses and setting the addresses of the read operation in an arbitrary order. Therefore, the order of addresses in this read operation also has the function of an authentication key, and the accuracy of detecting duplicates can be increased by the write data and the order of addresses in read.

[Fifth Embodiment]
FIG. 29 is a diagram illustrating an LSI with a copy determination circuit and a host computer according to the fifth embodiment. This LSI 9 with a copy determination circuit has a logic circuit 2 and a memory 1 and is connected to a host computer 10 to exhibit a predetermined function. The LSI 9 is provided with a duplicate determination circuit 3 and is directly connected to the host computer 10. That is, the host computer 10 inputs the data A [N: 0] to the signal wiring pair of the duplicate determination circuit 3 and the signal wiring pair latched in response to the clock CLK at a predetermined timing from the input. Latch data AL [N: 0] is acquired from the duplicate product determination circuit 3. By controlling the data A [N: 0] and the clock CLK, the replica inversion (authentication) operation similar to that in the first to fourth embodiments can be performed.

  In the case of the fifth embodiment, a ferroelectric capacitor having a characteristic different from that of the regular product is formed in the duplicated product judgment circuit 3 of the duplicated LSI, or no ferroelectric capacitor is formed. The computer 10 can determine whether the product is a genuine product or a copy product by directly performing the determination operation described in the above-described embodiment on the copy product determination circuit 3.

  As described above, according to the present embodiment, the duplicate product determination circuit is built in the LSI to be determined, and the polarization formation data signal and the authentication data signal are provided to each signal wiring of the copy product determination circuit. By inputting and analyzing the latch data at a predetermined timing, it is possible to determine whether the LSI is a genuine product or a duplicate product. This is because it is not easy to reproduce the ferroelectric capacitor from the photographic drawing of the LSI.

  The above embodiment is summarized as follows.

(Appendix 1)
A duplicate product judgment circuit built in an integrated circuit device to be judged,
A pair of wires to which signals are input;
A ferroelectric capacitor provided between the wiring pair;
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to the wiring pair, and the ferroelectric capacitor has a polarization state corresponding to the first signal. After that, a second signal having a potential opposite to that of the first signal is input to the wire pair, and whether the signal is a genuine product based on the signal of the wire pair at a predetermined timing after the input. A duplicate product determination circuit for determining whether or not the product is a duplicate product.

(Appendix 2)
In Appendix 1,
After the polarization state is formed by the first signal, the signal of the wiring pair at a predetermined timing after the second signal is input, and then the second signal is input again after that. A duplicate product determination circuit for determining whether the product is a genuine product or a duplicate product based on the signal of the wiring pair at the predetermined timing.

(Appendix 3)
In Appendix 2,
The predetermined timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and longer than the switching delay time of the signal of the wiring pair that does not invert the polarization state. Product judgment circuit.

(Appendix 4)
In Appendix 1,
After the polarization state is formed by the first signal, whether the product is a genuine product or a duplicate product is determined based on the signal of the wiring pair at the first and second timings after the second signal is input. Is a duplicate determination circuit.

(Appendix 5)
In Appendix 4,
The first timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and the second timing is a replica judgment circuit longer than the switching delay time. .

(Appendix 6)
A duplicate product judgment circuit built in an integrated circuit device to be judged,
A plurality of wiring pairs to which signals are input;
A plurality of ferroelectric capacitors respectively provided between the plurality of sets of wiring pairs;
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to each of the plurality of wiring pairs, and the first signal is input to the plurality of ferroelectric capacitors. Then, a second signal having a potential opposite to that of the first signal is input to the first wiring pair of the plurality of wiring pairs, and the second wiring pair A third signal having the same potential as the first signal is input to the first signal and the second signal based on the signals of the first and second wiring pairs at a predetermined timing after the input. A duplicate determination circuit in which the determination is made.

(Appendix 7)
In Appendix 6,
The predetermined timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and longer than the switching delay time of the signal of the wiring pair that does not invert the polarization state. Product judgment circuit.

(Appendix 8)
A logic circuit having a predetermined function;
A memory having a data output terminal;
A replica judgment circuit having a wiring pair connected to a data output terminal of the memory and to which a data output signal is input, and a ferroelectric capacitor provided between the wiring pair;
Corresponding to the first data read from the memory, a first signal having a second wiring potential higher than the first wiring potential is input to the wiring pair and is input to the ferroelectric capacitor. A second signal having a potential opposite to that of the first signal corresponding to second data opposite to the first data read out from the memory. Is input to the wiring pair, and an integrated circuit device is determined based on a signal of the wiring pair at a predetermined timing after the input.

(Appendix 9)
In Appendix 8,
Third data including at least the first data and a plurality of fourth data including the second data are written to a plurality of addresses in the memory,
After the third data is read from the memory, the plurality of fourth data is read sequentially in an arbitrary address order, and a signal corresponding to the plurality of fourth data is read at the predetermined timing. An integrated circuit device that determines whether the product is a genuine product or a duplicate product based on the signal of the wiring pair.

(Appendix 10)
A replica judgment circuit built in an integrated circuit device to be judged, comprising a pair of wirings to which signals are input and a ferroelectric capacitor provided between the pair of wirings. A method for determining a replica of an integrated circuit device, comprising:
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to the wiring pair, and the ferroelectric capacitor has a polarization state corresponding to the first signal. A polarization state forming step to be formed;
After the polarization forming step, a second signal having a potential opposite to that of the first signal is input to the wire pair, and a normal signal is generated based on the signal of the wire pair at a predetermined timing after the input. And a determination step of determining whether the product is a copy or a copy.

(Appendix 11)
In Appendix 10,
In the determination step, the signal of the wiring pair at a predetermined timing after inputting the second signal, and then the wiring pair at the predetermined timing after inputting the second signal again. A duplicate product judgment method that judges whether the product is a genuine product or a duplicate product based on the signal.

(Appendix 12)
In Appendix 11,
The predetermined timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and longer than the switching delay time of the signal of the wiring pair that does not invert the polarization state. Product judgment method.

(Appendix 13)
In Appendix 10,
In the determination step, a copy product determination method is performed in which it is determined whether the product is a genuine product or a copy product based on the signal of the wiring pair at each of the first and second timings after the second signal is input. .

(Appendix 14)
In Appendix 13,
The first timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and the second timing is longer than the switching delay time. .

A, B: Signal wiring pair
FC: Ferroelectric capacitor
FF: Latch circuit
AL: Latch signal
CLK: Timing clock

Claims (11)

A duplicate product judgment circuit built in an integrated circuit device to be judged,
A pair of wires to which signals are input;
A ferroelectric capacitor provided between the wiring pair;
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to the wiring pair, and the ferroelectric capacitor has a polarization state corresponding to the first signal. After that, a second signal having a potential opposite to that of the first signal is input to the wire pair, and whether the signal is a genuine product based on the signal of the wire pair at a predetermined timing after the input. A duplicate product determination circuit for determining whether or not the product is a duplicate product. In claim 1,
After the polarization state is formed by the first signal, the signal of the wiring pair at a predetermined timing after the second signal is input, and then the second signal is input again after that. A duplicate product determination circuit for determining whether the product is a genuine product or a duplicate product based on the signal of the wiring pair at the predetermined timing. In claim 2,
The predetermined timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and longer than the switching delay time of the signal of the wiring pair that does not invert the polarization state. Product judgment circuit. In claim 1,
After the polarization state is formed by the first signal, whether the product is a genuine product or a duplicate product is determined based on the signal of the wiring pair at the first and second timings after the second signal is input. Is a duplicate determination circuit. In claim 4,
The first timing is shorter than the switching delay time of the signal of the wiring pair that inverts the polarization state of the ferroelectric capacitor, and the second timing is a replica judgment circuit longer than the switching delay time. . A duplicate product judgment circuit built in an integrated circuit device to be judged,
A plurality of wiring pairs to which signals are input;
A plurality of ferroelectric capacitors respectively provided between the plurality of sets of wiring pairs;
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to each of the plurality of wiring pairs, and the first signal is input to the plurality of ferroelectric capacitors. Then, a second signal having a potential opposite to that of the first signal is input to the first wiring pair of the plurality of wiring pairs, and the second wiring pair A third signal having the same potential as the first signal is input to the first signal and the second signal based on the signals of the first and second wiring pairs at a predetermined timing after the input. A duplicate determination circuit in which the determination is made. A logic circuit having a predetermined function;
A memory having a data output terminal;
A replica judgment circuit having a wiring pair connected to a data output terminal of the memory and to which a data output signal is input, and a ferroelectric capacitor provided between the wiring pair;
Corresponding to the first data read from the memory, a first signal having a second wiring potential higher than the first wiring potential is input to the wiring pair and is input to the ferroelectric capacitor. A second signal having a potential opposite to that of the first signal corresponding to second data opposite to the first data read out from the memory. Is input to the wiring pair, and an integrated circuit device is determined based on a signal of the wiring pair at a predetermined timing after the input. In claim 7 ,
Third data including at least the first data and a plurality of fourth data including the second data are written to a plurality of addresses in the memory,
After the third data is read from the memory, the plurality of fourth data is read sequentially in an arbitrary address order, and a signal corresponding to the plurality of fourth data is read at the predetermined timing. An integrated circuit device that determines whether the product is a genuine product or a duplicate product based on the signal of the wiring pair. A replica judgment circuit built in an integrated circuit device to be judged, comprising a pair of wirings to which signals are input and a ferroelectric capacitor provided between the pair of wirings. A method for determining a replica of an integrated circuit device, comprising:
A first signal having a second wiring potential higher than the first wiring potential of the wiring pair is input to the wiring pair, and the ferroelectric capacitor has a polarization state corresponding to the first signal. A polarization state forming step to be formed;
After the polarization forming step, a second signal having a potential opposite to that of the first signal is input to the wire pair, and a normal signal is generated based on the signal of the wire pair at a predetermined timing after the input. And a determination step of determining whether the product is a copy or a copy. In claim 9,
In the determination step, the signal of the wiring pair at a predetermined timing after inputting the second signal, and then the wiring pair at the predetermined timing after inputting the second signal again. A duplicate product judgment method that judges whether the product is a genuine product or a duplicate product based on the signal. In claim 9,
In the determination step, a copy product determination method is performed in which it is determined whether the product is a genuine product or a copy product based on the signal of the wiring pair at each of the first and second timings after the second signal is input. .