JP5926529B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an image pickup device and an image pickup apparatus using the image pickup device, and more specifically, an image pickup device in which each pixel has a plurality of photoelectric conversion units and reads signals from each pixel through a plurality of readout systems. The present invention relates to an imaging apparatus.

  There has been proposed a solid-state imaging device that includes a pixel provided with a plurality of photoelectric conversion units per unit pixel in a part of a pixel region. Such a pixel has been used for focus adjustment in a phase difference detection system. Moreover, since the image captured for each arrangement of the photoelectric conversion units such as the left group and the right group in the unit pixel is an image signal having different viewpoints, application to a stereoscopic image capturing apparatus or the like is also expected.

  On the other hand, it has become common for CMOS solid-state imaging devices to output image signals in parallel from a plurality of output terminals for the purpose of high-speed reading. Particularly, in order to increase the arrangement space of the column output circuit and simplify the wiring structure with the horizontal scanning circuit and the horizontal signal line, it is connected to output terminals arranged above and below the pixel region every other column. It was composed. The necessity of such an arrangement is understood when recalling that the number of output terminals is typically an even number, most simply 2.

  For example, Patent Document 1 discloses an imaging device in which an imaging pixel having a photoelectric conversion unit and a focus detection pixel having a pair of first and second photoelectric conversion units are two-dimensionally arranged. Has been. This image sensor is a first focus detection signal obtained by adding the outputs of the first photoelectric conversion units of the first focus detection pixel and the second focus detection pixel adjacent to each other among the plurality of focus detection pixels. An output unit for outputting from the pixel is provided. The output unit outputs a signal obtained by adding the outputs of the second photoelectric conversion units from the second focus detection pixel.

  By this addition, it becomes possible to read out the image signal from the focus detection pixels in the same readout sequence as the image pickup element that is configured by all of the image pickup pixels even though the focus detection pixels are arranged. It is possible to prevent complication of operation control of the element.

  On the other hand, Patent Document 2 discloses a CMOS solid-state imaging device having a double-line readout configuration, which is arranged in a two-dimensional matrix and has a plurality of pixels that photoelectrically convert a subject optical image to generate a charge signal. The CMOS solid-state imaging device includes a plurality of column output circuits that perform predetermined processing on a charge signal read from a pixel, and a plurality of output terminals that output charge signals that have been subjected to predetermined processing by the column output circuit And have. In addition, a plurality of column output circuit selection units for selecting a column output circuit to which the charge signal read from the pixel is sent are provided. The column output circuit selection unit outputs, from one output terminal, a charge signal generated by a specific pixel arranged in a checkered pattern among pixels, and outputs a charge signal generated by another pixel from another output terminal. The column output circuit is selected as follows.

  In this CMOS solid-state imaging device, in order to output a large number of pixels in parallel from a plurality of horizontal signal lines, column output circuits and horizontal scanning circuits are provided above and below the pixel region, and the column output circuit is provided every other column. Was connected. Conventionally, in the Bayer color filter array, the G signal existing in the R row and the G signal existing in the B row receive noise from different column output circuits or horizontal scanning circuits. On the other hand, in Patent Document 2, the column output circuit selection unit can use the same column output circuit and horizontal scanning circuit.

JP 2008-103885 A JP 2007-74630 A

  However, Patent Document 1 is intended to use the first photoelectric conversion unit and the second photoelectric conversion unit as a focus detection pixel by adding the first photoelectric conversion unit and the second photoelectric conversion unit, and the first photoelectric conversion unit and the second photoelectric conversion unit. And could not be added. In addition, only an addition method for transferring the charge to the same charge-voltage converter (also referred to as a floating diffusion layer or a floating diffusion) between the first photoelectric converters has been disclosed. Further, in view of the drawing, the same floating diffusion has a larger area than the floating diffusion in the imaging pixel, so that the capacity is increased, the charge conversion coefficient of the focus detection pixel is lowered, and the S / N ratio may be lowered. is there.

  In addition, the column output circuit selection unit of Patent Document 2 selects a specific pixel arranged exclusively in a checkered pattern so that it can be output from one output terminal, and the effect in other cases is not suggested. Furthermore, there is no suggestion of the possibility of adding signals output from one output terminal.

  The present invention has been made in view of the above-described problems. In an image pickup device in which each pixel has a plurality of photoelectric conversion units and reads signals from each pixel through a plurality of readout systems, addition reading in units of pixels is performed. And it aims at enabling it to perform the independent reading for every photoelectric conversion part appropriately.

In order to achieve the above object, an image pickup device of the present invention includes a plurality of photoelectric conversion units and a plurality of conversion units that convert electric charges converted by the plurality of photoelectric conversion units into voltage signals and output the voltage signals. A signal line commonly connected to any of the plurality of conversion means included in each of a plurality of unit pixels arranged in a column and a plurality of unit pixels arranged in a column, and the plurality of conversion units. A plurality of the first and second read-out means for independently transferring the voltage signals output from the plurality of conversion means in a first direction via the plurality of signal lines; A plurality of second reading means for transferring the voltage signal transferred by the first reading means in a second direction; a coupling means for coupling the plurality of signal lines for each column; and the coupling means The plurality of And a control means for controlling whether or not to combine Route, and characterized in that said plurality of signal lines, for each column, and connected to one of said plurality of second reading means To do.

  According to the present invention, each pixel has a plurality of photoelectric conversion units, and in an imaging device that reads signals from each pixel through a plurality of readout systems, addition readout in units of pixels and independent readout for each photoelectric conversion unit are performed. Can be done appropriately.

1 is a block diagram illustrating an example of the overall configuration of an imaging apparatus according to an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram illustrating an example of a configuration of the solid-state imaging element according to the first embodiment. FIG. 3 is an equivalent circuit diagram illustrating an example of a configuration of a unit pixel according to the first embodiment. 6 is a timing chart illustrating a method for driving the solid-state imaging element according to the first embodiment. The equivalent circuit diagram showing an example of the composition of the solid-state image sensing device concerning a 2nd embodiment. The equivalent circuit diagram showing an example of the composition of the unit pixel concerning a 2nd embodiment. The equivalent circuit diagram showing an example of the composition of the solid-state image sensing device concerning a 3rd embodiment. The equivalent circuit diagram showing an example of the composition of the unit pixel concerning a 3rd embodiment. 9 is a timing chart illustrating a method for driving a solid-state imaging device according to a third embodiment. The equivalent circuit diagram showing an example of the composition of the solid-state image sensing device concerning a 4th embodiment. The equivalent circuit diagram showing an example of the composition of the unit pixel concerning a 4th embodiment. FIG. 10 is an equivalent circuit diagram illustrating an example of a configuration of a solid-state imaging element according to a fifth embodiment. 10 is a timing chart illustrating a method for driving a solid-state imaging device according to a fifth embodiment. The equivalent circuit diagram showing an example of the composition of the solid-state image sensing device concerning a 6th embodiment.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

  First, the overall configuration of an imaging apparatus according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating an example of the overall configuration of an imaging apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a photographing optical system such as a lens including a diaphragm and a mechanical shutter. The solid-state imaging device 2 photoelectrically converts the subject image formed by the photographing optical system 1 and takes it out as an electrical signal. Since most of the features of the configuration of the present invention are in the solid-state imaging device 2, it will be described in detail later.

  A correlated double sampling (CDS) circuit 3 samples an analog signal output from the solid-state imaging device 2, and an A / D converter 4 converts the sampled analog signal into a digital signal. The digitized image signal is stored in the image memory 8 and subjected to various signal processing such as white balance correction and gamma correction by the signal processing circuit 7. The image signal subjected to the signal processing is recorded on the recording medium 10 via the recording circuit 9. On the other hand, the image signal can also be directly displayed on the display device 12 such as a liquid crystal display through the display circuit 11. The display device 12 can also perform live view display for continuously displaying a screen to be imaged from now on, and playback display of recorded moving images.

  The timing generation circuit 5 drives an imaging system such as the imaging optical system 1 and the solid-state imaging device 2 via the drive circuit 6. Further, the CDS circuit 3 and the A / D converter 4 are driven and controlled in synchronization with the drive of the image pickup system and thus with the output signal of the solid-state image pickup device 2. Since this embodiment is characterized by the driving method by the timing generation circuit 5, it will be described in detail later.

  The system control unit 13 controls the entire imaging apparatus with a program temporarily stored in a volatile memory 14 such as a RAM. Reference numeral 15 denotes a non-volatile memory such as a ROM storing a program and various data to be transferred when the processing is executed.

<First Embodiment>
Next, the configuration of the solid-state imaging device 2 that is a feature of the present invention will be described in detail. FIG. 2 is an equivalent circuit diagram illustrating an example of the configuration of the solid-state imaging device 2 according to the first embodiment. The solid-state imaging device 2 has a pixel region 20 where a subject is to be imaged by the photographing optical system 1. In the pixel region 20, unit pixels including a plurality of photoelectric conversion units are arranged in a matrix form at equal intervals vertically and horizontally. Here, the configuration of the unit pixel will be described.

  FIG. 3 is an equivalent circuit diagram for explaining an example of the configuration of the unit pixel of the solid-state imaging device 2. In the following description, (n, m) represents a component in a unit pixel existing in the nth row and the mth column in the pixel region 20. Further, L and R mean a component existing on the left side and a component existing on the right side in the drawing, respectively. However, in the case of explaining the configuration regardless of the arrangement position and the left and right positions of the configuration, at least one of (n, m) and L and R may be omitted.

  Reference numeral 200 denotes a microlens including a unit pixel within the diameter. 201L (n, m) and 201R (n, m) are photoelectric conversion units, and are configured by, for example, photodiodes. The photoelectric conversion unit includes an N-type semiconductor region, and also functions as a charge storage unit. Signal charges generated in the photoelectric conversion units 201L (n, m) and 201R (n, m) are transferred to the floating diffusion unit 202L (n, m) via the transfer transistors 203L (n, m) and 203R (n, m), respectively. m) and 202R (n, m). The floating diffusion unit 202 operates as a charge voltage conversion unit. The transfer transistors 203L (n, m) and 203R (n, m) are on / off controlled by a control line Tx (n), and are turned on by a high signal and turned off by a low signal. Since the control line Tx (n) is commonly connected to a plurality of unit pixels arranged in the horizontal direction (row direction), the transfer transistors 203L (n, m) and 203R (n, m) are connected to each row (n ) Is turned on / off every time.

  The charge-voltage converters 202L (n, m) and 202R (n, m) include an N-type semiconductor region, and also function as a charge storage unit, similar to the photoelectric converter 201. Further, the reset voltage is reset to the power supply voltage VDD at a cycle of a timing chart described later with reference to FIG. 4 via reset transistors 204L (n, m) and 204R (n, m) controlled by the control line Rx (n). can do. By applying a high signal to the control line Rx (n), the reset transistors 204L (n, m) and 204R (n, m) are turned on and reset is performed. After this reset, the reset transistors 204L (n, m) and 204R (n, m) are turned off and are in an electrically floating (floating) state. Therefore, the potential drops below the power supply voltage VDD by an amount corresponding to the signal charge transferred from the photoelectric conversion units 201L (n, m) and 201R (n, m). The rough mechanism of the unit pixel is to output an analog electric signal by reading this as a signal. The potential corresponding to the signal charge is a potential obtained by dividing the signal charge amount by the capacitance of the charge voltage conversion units 202L (n, m) and 202R (n, m).

  The charge-voltage converters 202L (n, m) and 202R (n, m) are also connected to the gates of the amplification transistors 205L (n, m) and 205R (n, m). Then, a constant current source (not shown) connected to vertical signal lines VLm and VRm, which will be described later, by turning on the selection transistors 206L (n, m) and 206R (n, m) controlled by the control line Sx (n). ) And the source follower circuit. Thereby, the potential change from the power supply voltage is transmitted. The vertical signal lines VLm and VRm are commonly connected to the photoelectric conversion units 201L (n, m) and 201R (n, m) of unit pixels arranged in the vertical direction (column direction, first direction). Yes.

  In the example shown in FIG. 2, in order to make the explanation easy to understand, a case where unit pixels having the above-described configuration are arranged in 4 × 8 columns vertically and horizontally in the pixel region 20 at equal intervals is shown. However, in an actual imaging apparatus, unit pixels of about several million to tens of millions of pixels are arranged.

  In FIG. 2, vertical signal lines VLm and VRm are connected to vertical signal lines different from each other in a plurality of photoelectric conversion units 201L (n, m) and 201R (n, m) of unit pixels arranged in eight columns. As shown, 16 wires are wired. As described above, a plurality of photoelectric conversion units 201L (n, m) and 201R (n, m) are connected to each vertical signal line VLm and VRm for each column.

  Capacitors CSLm, CNLm, CSRm, and CNRm constituting a column output circuit (first reading means) are arranged at the subsequent stage of each of the vertical signal lines VLm and VRm. These capacitors CSLm, CNLm, CSRm, and CNRm realize a function as a memory for one row in which the potentials of the vertical signal lines VLm and VRm are written. A capacitor indicated by CS indicates a memory for holding a potential (image signal) after signal charge transfer, and a capacitor indicated by CN indicates a memory for holding a potential (noise signal) before signal charge transfer. Yes. Further, a parallel control line of transistors for writing potentials to 16 capacitors CSLm and CSRm is called PS, and a parallel control line of transistors for writing potentials to 16 capacitors CNLm and CNRm is called PN.

  In the first embodiment, the column output circuit further includes a noise signal addition averaging transistor ANm controlled by the control line ADD1 (control means) for each combination of the vertical signal lines VLm and VRm. (Joining means). Further, an addition averaging transistor ASm for image signals controlled by the control line ADD1 (control means) is provided for each combination of the vertical signal lines VLm and VRm (coupling means). With this configuration, the noise signal addition averaging transistor ANm and the image signal addition averaging transistor ASm can add and average the noise signal and the image signal for each unit pixel.

  The vertical scanning circuit 21 sends a row address so that the transfer transistor 203, the reset transistor 204, and the selection transistor 206 shown in FIG. 3 are sequentially turned on in the vertical direction at a timing shown in a timing chart described later.

  The horizontal scanning circuits 22U and 22D are arranged in the horizontal direction (row direction, second direction) to output the image signal and noise signal accumulated in the capacitors CSLm, CSNm, CSRm, CNRm to the respective output terminals 23U or 23D. Functions to scan sequentially. The output terminals 23U and 23D have a differential circuit configuration that subtracts the noise signal from the image signal and outputs it, and an S-N signal from which noise has been removed can be obtained. The signal lines connected to the output terminals 23U and 23D may be referred to as horizontal signal lines (second reading means).

  INVU and INVD are all inverting elements that invert the input value, and MSm, MNm, and Mm are all AND elements that output the product of the two input values.

  In such a configuration including a plurality of signal output systems, by distributing the signal output system for each unit pixel, not only the S-N signal is read out independently and in parallel from each photoelectric conversion unit 201 but also added for each unit pixel. It becomes possible to read out the averaged SN signals in parallel.

  FIG. 4 is an example of a timing chart for driving the solid-state imaging device 2 according to the first embodiment. Specifically, the addition averaged voltage signals of the plurality of photoelectric conversion units 201 included in the unit pixel are output. It is a timing chart for. The timing chart as shown in FIG. 4 is realized by the timing generation circuit 5. Hereinafter, a specific operation of the solid-state imaging device 2 will be described according to this timing chart.

  Here, first, it is assumed that the addition averaging control signal ADD1 is fixed to high. FIG. 4 shows the values of the respective control lines with respect to time after the vertical scanning circuit 21 selects the n-th row at a time, as indicated by the horizontal synchronizing signal. Therefore, when the operation shown in FIG. 4 is completed, the vertical scanning circuit 21 selects the (n + 1) th row and repeats the operation of FIG. Such repetition continues until there are no more selectable vertical addresses.

  At time t1 in FIG. 4, the control line Sx (n) of the selection transistors 206L (n, m) and 206R (n, m) of the selected row (nth row) rises with the rise of the horizontal synchronization signal. Thus, all the selected unit pixels in the nth row are connected to the vertical signal lines VLm and VLn.

  At time t2 in FIG. 4, the control lines Rx (n) of the reset transistors 204L (n, m) and 204R (n, m) in the nth row rise, and the charge / voltage conversion unit 202L (n, m) in the nth row. And 202R (n, m) are all reset to the power supply VDD. In this way, the potentials of the charge-voltage converters 202L (n, m) and 202R (n, m) are approximately VDD. This potential state hardly changes at time t3 when the control line Rx (n) falls and the reset transistors 204L (n, m) and 204R (n, m) are turned off. In other words, at time t3, the reset transistors 204L (n, m) and 204R (n, m) are turned off, so that the charge-voltage converters 202L (n, m) and 202R (n, m) are both floating ( Floating) state. It should be noted that the horizontal synchronization signal has fallen before the time t2, but this is not limited because the high period only needs to be maintained high enough as information held by the synchronization signal. .

  At time t4, in order to read the detailed potentials of the charge-voltage converters 202L (n, m) and 202R (n, m) in such a floating state to the memory for one row including the capacitors CNRm, The control line PN is activated. At this time, since ADD1 is fixed high, the addition averaging transistor ANm in FIG. 3 is in the on state, and therefore the potential obtained by adding and averaging the potential of VLm and the potential of VRm is read out to the capacitor CNRm. Here, since the averaged potential is read out, half of the capacitors CNLm and CNRm arranged in the column output circuit is not necessary, so in the first embodiment, the potential averaged only in the capacitor CNRm. Is read out.

  The capacitor CNLm is blocked by the functions of the inverting elements INVU and INVD that invert the ADD1 of FIG. 3 and the AND elements MNm and MSm. That is, the inverting elements INVU and INVD output low because the addition averaging control signal ADD1 is fixed high. Of the transistors controlled by the control line PN, the AND elements MNm are inserted only in the paths corresponding to the capacitors CNLm. Since the first input of these AND elements MNm is a low signal output from the inverting elements INVU and INVD, even if the PN is high from time t4 to t5, the output of the AND element MNm is low. Therefore, no potential is read out to the capacitor CNLm in which the AND element MNm is inserted in the path. Of course, instead of the capacitor CNLm, it is possible to read out the potential only to the capacitor CNLm by inserting an AND element in the path to the capacitor CNRm.

  Thereafter, PN falls at time t5, and at time t6, the control lines Tx (n) of the transfer transistors 203L (n, m) and 203R (n, m) rise. As a result, the signal charges photoelectrically converted and accumulated by the photoelectric conversion units 201L (n, m) and 201R (n, m) are stored in the charge-voltage conversion units 202L (n, m) and 202R (n, m). Transferred. Then, the control line Tx (n) falls after waiting for a time t7 sufficient for signal charge transfer.

  Next, at time t8, the control line PS is activated to read out a detailed potential obtained by adding the potential corresponding to the signal charge to the floating (floating) potential to the memory for one row including the capacitors CSRm. Also at this time, as described above at time t4, the addition average potential is read to the capacitor CSRm, and nothing is read to the capacitor CSLm by the functions of the inverting elements INVU and INVD and the AND element MSm.

  At time t9, PS falls, and at time t10, Sx (n) also falls, and the charge voltage conversion units 202L (n, m) and 202R (n, m) in the n-th row and the vertical signal lines VLm and VRm The connection of is terminated.

  Although a drive signal is not shown in FIG. 4, horizontal scanning is performed in which the potential read into the memory for one row is sequentially scanned in the horizontal direction using the time period from time t10 to t11. Note that the addition average potential is read out only to the capacitors CSRm and CNRm, and the potential reading transistors of the capacitors CSLm and CNLm are stopped by the function of the AND element Mm. Since the stopping mechanism is the same as that described in the inverting elements MSm and MNm, the description thereof is omitted.

  Note that the timing chart of FIG. 4 used for the explanation is an example for specifically explaining the addition averaging operation in the solid-state imaging device 2 having the configuration shown in the equivalent circuit of FIG. 2 that occurs from time t4 to t9. However, various modifications are conceivable.

  Further, in the timing chart of FIG. 4, if the addition averaging control signal is turned off, it is independent from the photoelectric conversion units 201L (n, m) and 201R (n, m) included in the unit pixel without performing addition averaging. An electrical signal can be output. For example, a control method such as outputting an electric signal independently in the stereoscopic image shooting mode and outputting an addition average voltage signal in the live view mode can be considered.

  As described above, according to the first embodiment, in a CMOS solid-state imaging device having a unit pixel including two photoelectric conversion units and having a plurality of output systems, signal readout independent from the two photoelectric conversion units. And reading out the averaged signal can be made compatible easily.

  In the first embodiment, the case where two photoelectric conversion units are arranged for each unit pixel has been described. However, the present invention is not limited to this, and three or more photoelectric conversion units are arranged for each unit pixel. It may be a thing. In such a case as well, a signal from each photoelectric conversion unit of each unit pixel may be configured to be read from any of a plurality of output systems for each unit pixel.

<Second Embodiment>
In the second embodiment, as an example, a case where each unit pixel includes four photoelectric conversion units will be described.

  FIG. 5 is an equivalent circuit diagram illustrating an example of the configuration of the solid-state imaging device 2 in which each unit pixel includes four photoelectric conversion units. The solid-state imaging device 2 has a pixel region 20 as in the first embodiment, and unit pixels including four photoelectric conversion units are arranged vertically and horizontally in 2 rows × 4 columns at equal intervals. As shown, in an actual imaging device, unit pixels of about several million to tens of millions of pixels are arranged.

  FIG. 6 is an equivalent circuit diagram for explaining an example of the configuration of the unit pixel of the solid-state imaging device 2. In the following description, the four symbols LL, LC, RC, and RR mean components that are related to four photoelectric conversion units that exist in order, counting from the leftmost side to the rightmost side in the drawing. However, in the following description, in order to simplify the description, description of (n, m) and at least one of LL, LC, RC, and RR may be omitted.

  Reference numeral 200 denotes a microlens including a unit pixel within the diameter, as in the first embodiment of FIG. 201LL (n, m), 201LC (n, m), 201RC (n, m), and 201RR (n, m) are photoelectric conversion units. The signal charges generated in the photoelectric conversion unit 201 (n, m) are transmitted through the respective transfer transistors 203LL (n, m), 203LC (n, m), 203RC (n, m), and 203RR (n, m). The charge-voltage converter 202LL (n, m), 202LC (n, m), 202RC (n, m) and 202RR (n, m) are transferred. The transfer transistor 203 (n, m) (switching means) is controlled by the control line Tx (n) (control means) as in the first embodiment. Since the control line Tx (n) is commonly connected to a plurality of unit pixels arranged in the horizontal direction (row direction), the four transfer transistors 203 (n, m) are turned on / off for each row (n). Controlled off.

  Furthermore, the first embodiment is provided via reset transistors 204LL (n, m), 204LC (n, m), 204RC (n, m), and 204RR (n, m) controlled by the control line Rx (n). The four charge voltage converters 202 (n, m) can be reset to the power supply voltage VDD in the same timing chart cycle as in FIG. The four charge voltage conversion units 202 (n, m) are connected to the gates of the amplification transistors 205LL (n, m), 205LC (n, m), 205RC (n, m) and 205RR (n, m), respectively. Has been. A constant current source (not shown) and a source follower circuit connected to the vertical signal lines VLLm, VLCm, VRCm, and VRRm are configured by turning on the selection transistor controlled by the control line Sx (n). The vertical signal lines VLLm, VLCm, VRCm, and VRRm are a plurality of unit pixel photoelectric conversion units 201LL (n, m), 201LC (n, m), 201RC (n, m), and the like arranged in the vertical direction (column direction). 201RR (n, m) is commonly connected to each.

  FIG. 5 shows a case where unit pixels in which the four photoelectric conversion units 201 having the configuration shown in FIG. 6 are arranged in the horizontal direction are arranged in 2 rows × 4 columns at equal intervals vertically and horizontally as described above. ing.

  In FIG. 5, vertical signal lines VLLm, VLCm, VRCm, and VRRm are four photoelectric conversion units 201LL (n, m), 201LC (n, m), 201RC (n, m) of unit pixels arranged in four columns. 16 RRs (201, RR (n, m)) are wired so as to be connected to different vertical signal lines. Then, capacitors CSLLm, CNLLm, CSLCm, CNLCm, CSRCm, CNRCm, CSRRm, and CNRRm that constitute the column output circuit are arranged at the subsequent stage of the vertical signal lines VLLm, VLCm, VRCm, and VRRm. Thus, a function as a memory for one row for writing the potential of each vertical signal line is realized.

  The column output circuit further includes four vertical signal lines including three addition averaging transistors ANm1 to ANm1 for noise signals and three addition averaging transistors ASm1 to ASm1 for image signals, which are controlled by a control line ADD1. For each combination. With this configuration, the noise signal addition averaging transistors ANm1 to ANm1 and the image signal addition averaging transistors ASm1 to ASm1 can average the noise signal and the image signal for each unit pixel. it can.

  As in FIG. 2, 21 is a vertical scanning circuit, and 22U and 22D are horizontal scanning circuits. The output terminals 23U and 23D have a differential circuit configuration that subtracts and outputs the potential after signal charge transfer and the potential before signal charge transfer.

  The column output circuits in the second embodiment are also arranged in parallel with the horizontal signal lines above and below the pixel region 20 of the solid-state imaging device 2 corresponding to the output terminals 23U and 23D. These two column output circuit groups are distributed up or down for each unit pixel as understood by tracing back the vertical signal line. With such a configuration, it becomes easy to output the addition average voltage signal of the four photoelectric conversion units 201 included in the unit pixel. Although not explained in the timing chart, the specific operation of addition averaging by an appropriate combination of the inverting elements INVU and INVD and the AND elements MSm1 to 3, MNm1 to 3 and Mm1 to 3 is also performed in the first embodiment. It is equivalent to the form.

<Third Embodiment>
In the second embodiment described above, the plurality of photoelectric conversion units included in the unit pixel are arranged in the horizontal direction, and the number thereof is four. However, the arrangement direction of the photoelectric conversion units in the unit pixel is not limited to horizontal only. In the third embodiment, a case where 2 × 2 four photoelectric conversion units are arranged vertically and horizontally in each unit pixel will be described. Thus, the present invention is generalized to an aspect in a solid-state imaging device in which each unit pixel includes a plurality of photoelectric conversion units.

  FIG. 7 is an equivalent circuit diagram showing an example of the configuration of the solid-state imaging device 2 including such unit pixels. The solid-state imaging device 2 has a pixel region 20 as in the first and second embodiments, and unit pixels in which 2 × 2 four photoelectric conversion units are arranged vertically and horizontally are arranged vertically and horizontally. In this example, 2 rows × 4 columns are arranged at equal intervals. In an actual imaging device, unit pixels of about several million to tens of millions of pixels are arranged.

  FIG. 8 is an equivalent circuit diagram for explaining an example of the configuration of the unit pixel of the solid-state imaging device 2. In the following description, the four symbols LU, LD, RU, and RD mean that they are constituent elements related to four photoelectric conversion units existing in order, counting as upper left, lower left, upper right, and lower right on the drawing. To do. However, in the following description, in order to simplify the description, description of (n, m) and at least one of LU, LD, RU, and RD may be omitted.

  Reference numeral 200 denotes a microlens that includes a unit pixel within the diameter, as in the first and second embodiments. 201LU (n, m), 201LD (n, m), 201RU (n, m), and 201RC (n, m) are photoelectric conversion units. Of the signal charges generated in the photoelectric conversion unit 201 (n, m), the photoelectric conversion units 201LU (n, m) and 201LD (n, m) have their transfer transistors 203LU (n, m) and 203LD (n, m, m) and transferred to the charge-voltage converter 202L (n, m). The photoelectric converters 201RU (n, m) and 201RD (n, m) are connected to the charge / voltage converters 202R (n, m) via the transfer transistors 203RU (n, m) and 203RD (n, m), respectively. ). The transfer transistors 203LU (n, m) and 203RU (n, m) are controlled by the control line Tx1 (n), and the transfer transistors LD (n, m) and 203RD (n, m) are controlled by the control line Tx2 (n ). Since the control lines Tx1 (n) and Tx2 (n) are commonly connected to a plurality of unit pixels arranged in the horizontal direction (row direction), the four transfer transistors 203 (n, m) are connected to each row (n ) Is turned on / off every time.

  Further, it is reset to the power supply voltage VDD at a cycle of a timing chart described later with reference to FIG. 9 via reset transistors 204L (n, m) and 204R (n, m) controlled by the control line Rx (n). be able to.

  The charge-voltage converters 202L (n, m) and 202R (n, m) are also connected to the gates of the amplification transistors 205L (n, m) and 205R (n, m). The constant transistors (not shown) connected to the respective vertical signal lines VLm and VRm by the ON operation of the selection transistors 206L (n, m) and 206R (n, m) controlled by the control line Sx (n). ) And the source follower circuit. The vertical signal lines VLm and VRm are connected in common to the charge-voltage converters 202L (n, m) and 202R (n, m) of unit pixels arranged in the vertical direction (column direction).

  In the example shown in FIG. 7, as described above, unit pixels in which 2 × 2 pieces of four photoelectric conversion units as shown in FIG. 8 are arranged vertically and horizontally are arranged in 2 rows × 4 columns at equal intervals vertically and horizontally. The case of arrangement is shown.

  In FIG. 7, vertical signal lines VLm and VRm are connected to different vertical signal lines from a plurality of charge voltage conversion units 202L (n, m) and 202R (n, m) of unit pixels arranged in four columns. As shown in FIG. As described above, a plurality of charge voltage conversion units 202L (n, m) and 202R (n, m) are connected to the vertical signal lines VLm and VRm for each column, respectively.

  Capacitors CSLm, CNLm, CSRm, and CNRm constituting a column output circuit are arranged at the subsequent stage of each of the vertical signal lines VLm and VRm, and function as a memory for one row in which the potentials of the vertical signal lines VLm and VRm are written. Is realized.

  In the third embodiment, the column output circuit further includes a noise signal addition averaging transistor ANm and an image signal addition averaging transistor ASm controlled by the control line ADD1, and the vertical signal lines VLm and VRm. For each combination. With this configuration, the noise signal addition averaging transistor ANm and the image signal addition averaging transistor ASm can add and average the noise signal and the image signal for each unit pixel.

  As in the first and second embodiments described above, 21 is a vertical scanning circuit, and 22U and 22D are horizontal scanning circuits. The output terminals 23U and 23D have a differential circuit configuration that subtracts the noise signal from the image signal and outputs it, and an S-N signal from which noise has been removed can be obtained.

  The column output circuits in the third embodiment are also arranged in parallel with the horizontal signal lines above and below the pixel region 20 of the solid-state imaging device 2 corresponding to the output terminals 23U and 23D. These two column output circuits are distributed up or down for each unit pixel as understood by tracing back the vertical signal lines VLm and VRm. With such a configuration and a timing chart described later with reference to FIG. 9, it becomes easy to output the addition average voltage signal of the four photoelectric conversion units 201 included in the unit pixel.

  FIG. 9 is an example of a timing chart for driving the solid-state imaging device 2 according to the third embodiment, and more specifically, for outputting the addition average voltage signal of the photoelectric conversion unit 201 included in the unit pixel. It is a timing chart. Hereinafter, a specific operation of the solid-state imaging device 2 will be described according to this timing chart.

  Here, first, it is assumed that the addition averaging control signal ADD1 is fixed to high. FIG. 4 shows the values of the respective control lines with respect to time after the vertical scanning circuit 21 selects the n-th row at a time, as indicated by the horizontal synchronizing signal. Therefore, when the operation shown in FIG. 9 is completed, the vertical scanning circuit 21 selects the (n + 1) th row and repeats the operation of FIG. Such repetition continues until there are no more selectable vertical addresses.

  The difference from FIG. 4 is that at time t6, the control lines Tx1 (n) of the transfer transistors 203LU (n, m) and 203RU (n, m) and the transfer transistors 203LD (n, m) and 203RD (n, m) ) And the control line Tx2 (n). As a result, photoelectric conversion is performed by the photoelectric conversion units 201LU (n, m) and 201LD (n, m), and all the accumulated signal charges are added together and transferred to the charge-voltage conversion unit 202L (n, m). . On the other hand, photoelectric conversion is performed by the photoelectric conversion units 201RU (n, m) and 201RD (n, m), and all the accumulated signal charges are added and transferred to the charge / voltage conversion unit 202R (n, m). Since other operations are the same as those described with reference to FIG. 4, the description thereof is omitted here.

  The timing chart of FIG. 9 used for the description is an example for specifically explaining the addition averaging operation in the solid-state imaging device 2 having the configuration shown in the equivalent circuit of FIG. 7 that occurs from time t4 to t9. However, various modifications are conceivable.

  Further, in the timing chart of FIG. 9, if the addition averaging control signal is turned off and driving is performed so that Tx1 (n) and Tx2 (n) are sequentially scanned in the vertical direction instead of simultaneously, addition averaging is performed. It is possible to output an electric signal independently without the need.

  As described above, according to the third embodiment, in a CMOS solid-state imaging device having a unit pixel including a plurality of photoelectric conversion units and having a plurality of output systems, signal readout independent from the plurality of photoelectric conversion units. And reading out the averaged signal can be made compatible easily.

<Fourth Embodiment>
In the fourth embodiment, another configuration example for realizing addition averaging is shown. FIG. 10 is an equivalent circuit diagram showing an example of the configuration of the solid-state imaging device 2 in the fourth embodiment, and FIG. 11 is an example of an equivalent circuit diagram for explaining the configuration of unit pixels of the solid-state imaging device 2. is there. 10 and 11 are shown using the same reference numerals for the same elements as those in FIGS. 2 and 3, respectively, and only the differences from FIGS. 2 and 3 will be described in detail below.

  The difference is that, in FIG. 10, the addition averaging control line ADD1 controls each pixel. In FIG. 11, the addition averaging control line ADD1 (control means) includes an addition averaging transistor 207 (n as a switch that can connect the charge-voltage converters 202 (n, m) and 202R (n, m). , M) (connected to the coupling means).

  Similar to the timing chart shown in FIG. 4, if the value of the addition averaging control line ADD1 is driven while being fixed to high, the capacitance of the charge voltage conversion unit is basically the charge voltage conversion units 202L (n, m) and 202R ( n, m) and the parallel addition capacity. More specifically, the wiring capacitance and parasitic capacitance to the connection terminals of various transistors connected to the charge voltage conversion units 202L (n, m) and 202R (n, m), the wiring capacitance of the transistor 207 (n, m), etc. The added capacity. However, in any case, it is assumed that the capacity is sufficient to store the added signal charge. On the other hand, since the value of the addition averaging control line ADD1 is fixed to high, the charge / voltage conversion units 202L (n, m) and 202R (n, m) are transferred by the transfer transistors 203L (n, m) and 203R (n, m). The signal charges of the left and right photoelectric conversion units read out in (2) are added. Therefore, the potential read out to the vertical signal line VRm is substantially equal to the addition average voltage signal.

  The column output circuits in the fourth embodiment are also arranged in parallel with the horizontal signal lines above and below the pixel region 20 of the solid-state imaging device 2 corresponding to the output terminals 23U and 23D. These two column output circuits are distributed up or down for each unit pixel as understood by tracing back the vertical signal lines VLm and VRm. With such a configuration, it becomes easy to output the addition average voltage signal of the photoelectric conversion units 201L (n, m) and 201R (n, m) included in the unit pixel. Although not described in the timing chart, the specific operation of addition averaging by an appropriate combination of the inverting elements INVU and INVD and the AND elements MSm and MNm is the same as that in the first embodiment.

  Note that the number of photoelectric conversion units included in a unit pixel is not limited to two even when a transistor to which the charge-voltage conversion unit can be connected is included. This can be understood in view of the second and third embodiments described above.

<Fifth Embodiment>
In the first to third embodiments, the main configuration of the column output circuit is a memory for one row including the addition averaging control line ADD1. In the fourth embodiment, the charge voltage conversion units corresponding to the plurality of photoelectric conversion units included in the unit pixel are connected for averaging, so that the charge voltage conversion units that are considered as a single unit are connected. Capacity increases. Therefore, the conversion coefficient when obtaining the potential corresponding to the addition averaged signal charge is small, and it is difficult to obtain the S / N increase effect in a dark subject in which dark part noise is a problem. Along with the recent reduction in pixel size and higher sensitivity due to an increase in the number of pixels, further noise reduction technology is required. In a CMOS solid-state imaging device, it is an effective measure to reduce noise generated in the process of potential transmission.

  In the fifth embodiment, therefore, noise generated in the process of potential transmission is reduced by providing a column amplifier circuit (amplifying means) that performs voltage amplification before the averaging. Thus, the column output circuit according to the present invention is generalized to an aspect including a column amplifier circuit.

  FIG. 12 is an equivalent circuit diagram illustrating an example of the configuration of the solid-state imaging device 2 according to the fifth embodiment. 12, common reference numerals are used for elements common to FIG. 2, and only differences from FIG. 2 will be described in detail below.

  The difference is that for each of the 16 vertical signal lines VLm and VRm, a column amplifier circuit composed of the amplifier elements AMPLm and AMPRm and the peripheral elements CLm, CRm, CfLm, CfRm, MLm, and MRm This is provided above and below the solid-state imaging device 2. VREF is a reference voltage for the amplification elements AMPLm and AMPRm. Here, among the peripheral elements, MLm is a clamp transistor for performing clamp control by short-circuiting the input / output of the amplifier elements AMPLm and AMPRm, and a clamp control line PC is connected to the gate thereof. The clamp timing will be described later with reference to the timing chart of FIG. The amplification factor in this column amplifier circuit is expressed by CLm / CfLm and CRm / CfRm.

  The column output circuits in the fifth embodiment are also arranged in parallel with the horizontal signal lines above and below the pixel region 20 of the solid-state imaging device 2 corresponding to the output terminals 23U and 23D. These two column output circuits are distributed up or down for each unit pixel as understood by tracing back the vertical signal lines VLm and VRm. The specific operation of addition averaging by an appropriate combination of the inverting elements INVU and INVD and the AND elements Mm, MSm, and MNm is the same as that in the first embodiment.

  Even when the column amplifier circuit is included as in the fifth embodiment, the number of photoelectric conversion units included in the unit pixel is not limited to two.

  FIG. 13 is an example of a timing chart for driving the solid-state imaging device 2 in the fifth embodiment. Specifically, the addition averaged voltage signals of the plurality of photoelectric conversion units 201 included in the unit pixel are output. It is a timing chart for.

  The difference from FIG. 4 is that the clamp control line PC of the amplifying element is raised from time t2 ′ while the reset transistor control line Rx is high, and time t3 ′ before the potential write control line PN of the noise signal rises. It is a point to fall by. By this operation, it is possible to calibrate the variation of the column amplifier circuit before amplifying the potential of the noise signal and the potential of the image signal. Since other operations are the same as those described with reference to FIG. 4, the description thereof is omitted here.

  As described above, the column output circuit in the fifth embodiment also corresponds to the output terminals 23U and 23D, and is above and below the pixel region 20 of the solid-state imaging device 2 and parallel to the horizontal signal lines. Arranged. These two column output circuits are distributed up or down for each unit pixel as understood by tracing back the vertical signal lines VLm and VRm. This is useful when averaging a plurality of photoelectric conversion units for each unit pixel, but there is also an application in which a plurality of photoelectric conversion units are processed and recorded as a plurality of images for each unit. Here, for example, a certain group is a group that divides a plurality of photoelectric conversion units into a group located on the left and a group located on the right. If these are individually processed and recorded as a left group image and a right group image, a two-viewpoint stereoscopic image is obtained, which is useful.

<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described. FIG. 14 is an equivalent circuit diagram showing an example of the configuration of the solid-state imaging device 2 according to the sixth embodiment. FIG. 14 shows the same elements as those of FIG. 12 by using common reference numerals, and only the differences from the fifth embodiment will be described in detail below.

  The difference is that among the 16 vertical signal lines VLm and VRm, a total of 8 vertical signal lines VLm with an odd number m and an even vertical signal line VRm with an even number m are above or below the pixel region 20. The column output circuit selection unit is configured so that the arranged column output circuits can be selected. As a specific configuration for that purpose, only the eight vertical signal lines are provided with column output circuit selection transistors MUm and MDm. The gate is connected to the column output circuit selection control line LR or inverting elements INVU and INVD for outputting an inverted signal thereof.

  In the drive timing chart shown in FIG. 13, if the addition averaging control line ADD1 is fixed to low and the column output circuit selection control line LR is fixed to high, the potential of the vertical signal lines VLm for every other column of m is odd. The data is read out to the column output circuit arranged on the lower side of the solid-state imaging device 2. And it is output from the output terminal 23D. On the other hand, the potential of the vertical signal line VRm where m is an even number is read out to the column output circuit arranged on the upper side of the solid-state imaging device 2, and is output from the output terminal 23U. For vertical signal lines that do not include the column output circuit selection transistors MUm and MDm, the vertical signal line VLm is output from the output terminal 23D, and the vertical signal line VRm is output from the output terminal 23U. As a result, the output terminal 23D outputs images from all the left group photoelectric conversion units, and the output terminal 23U outputs all images from the right group photoelectric conversion units.

  As described above, if the left or right group of images can be associated with each output terminal, the configuration can be simplified when the image memory 8 is secured or when the signal processing circuit 7 performs signal processing. it can.

  On the other hand, as shown in the drive timing chart of FIG. 13, if the averaging control line ADD1 is fixed high and the column output circuit selection control line LR is fixed low, then m is an odd number of vertical signal lines every other column. The potential of VLm is read out to the column output circuit arranged on the upper side of the solid-state imaging device 2. Thereby, the potential of the vertical signal line VRm of the same unit pixel is averaged and output from the output terminal 23U. Similarly, the potential of the vertical signal line VRm having an even number m is read out to the column output circuit arranged below the solid-state imaging device 2, and is added and averaged with the potential of the vertical signal line VLm of the same unit pixel to be output. Output from terminal 23D. As a result, the output terminal 23D outputs an even-numbered image obtained by averaging for each unit pixel, and the output terminal 23U outputs an odd-numbered image obtained by averaging for each unit pixel. This point is the same as the result of the fifth embodiment.

  As described above, according to the sixth embodiment, by further adding the column output circuit selection unit, the addition averaged image for each unit pixel and the left group and right group images that are not based on the addition averaging are obtained. It is possible to selectively switch and output. The former is an image suitable for live view display such as frame alignment, and the latter can be used for stereoscopic image capturing.

  The preferred embodiments have been described above, but the present invention is not limited to these embodiments and can be applied. Various modifications and changes can be made within the scope of the gist.

  For example, in the first to sixth embodiments described above, a signal from an even-numbered unit pixel is read out to a column output circuit arranged below the pixel region 20 and a signal from an odd-numbered unit pixel is read out. In the above description, the configuration is read out by the column output circuit arranged above the pixel region 20. However, the vertical signal lines of the unit pixels in the left area of the pixel area 20 are read out to the column output circuit arranged below the pixel area 20, and the vertical signal lines of the unit pixels in the right area are arranged below the pixel area 20. The data may be read out to the column output circuit. Of course, the combination of upper, lower, left and right may be changed as appropriate. Further, the pixel area 20 may be read by dividing it into upper and lower areas.

  Further, the number of column output circuits may be three or more. In any case, the signal from each photoelectric conversion unit of each unit pixel may be configured to be read from any of a plurality of output systems for each unit pixel.

Claims (7)

A pixel region in which unit pixels each including a plurality of photoelectric conversion units and a plurality of conversion units that convert electric charges converted by the plurality of photoelectric conversion units into voltage signals and output the matrix signals are arranged in a matrix;
A plurality of signal lines commonly connected to any of the plurality of conversion means included in each of the plurality of unit pixels arranged in each column so as to be connected to each of the plurality of conversion means; A first readout means for independently transferring the voltage signal output from the means in a first direction via the plurality of signal lines;
A plurality of second reading means for transferring the voltage signal transferred by the first reading means in a second direction ;
Coupling means for coupling the plurality of signal lines for each column;
Control means for controlling whether or not the plurality of signal lines are coupled by the coupling means ,
An image pickup device, wherein the plurality of signal lines are connected to any one of the plurality of second reading means for each column. Wherein when coupling the plurality of signal lines by the coupling means, the image pickup according to claim 1, characterized in that for each of the unit pixels is controlled so as to couple the plurality of converting means element. A pixel region in which unit pixels each including a plurality of photoelectric conversion units and a plurality of conversion units that convert electric charges converted by the plurality of photoelectric conversion units into voltage signals and output the matrix signals are arranged in a matrix;
A plurality of signal lines commonly connected to any of the plurality of conversion means included in each of the plurality of unit pixels arranged in each column so as to be connected to each of the plurality of conversion means; A first readout means for independently transferring the voltage signal output from the means in a first direction via the plurality of signal lines;
A plurality of second reading means for transferring the voltage signal transferred by the first reading means in a second direction;
Coupling means for coupling the plurality of conversion means for each unit pixel;
Control means for controlling whether or not to combine the plurality of converting means by the combining means ,
It said plurality of signal lines, for each column, wherein the to that an imaging device that has been connected to one of said plurality of second reading means. A pixel region in which unit pixels each including a plurality of photoelectric conversion units and a plurality of conversion units that convert electric charges converted by the plurality of photoelectric conversion units into voltage signals and output the matrix signals are arranged in a matrix;
A plurality of signal lines commonly connected to any of the plurality of conversion means included in each of the plurality of unit pixels arranged in each column so as to be connected to each of the plurality of conversion means; A first readout means for independently transferring the voltage signal output from the means in a first direction via the plurality of signal lines;
A plurality of second reading means for transferring the voltage signal transferred by the first reading means in a second direction;
Switching means for switching whether the charges converted by the plurality of photoelectric conversion units are transferred to the plurality of conversion units by each photoelectric conversion unit or to the plurality of conversion units by a plurality of photoelectric conversion units; ,
Control means for controlling the switching by the switching means ,
It said plurality of signal lines, for each column, wherein the to that an imaging device that has been connected to one of said plurality of second reading means. Imaging device according to any one of claims 1 to 4, further comprising an amplifying means provided in each of the plurality of signal lines. A pixel region in which unit pixels each including a plurality of photoelectric conversion units and two conversion units that convert electric charges converted by the plurality of photoelectric conversion units into voltage signals and output the matrix signals are arranged in a matrix;
A plurality of signal lines commonly connected to one of the two conversion means included in each of the plurality of unit pixels arranged in each column so as to be connected to each of the two conversion means; A first readout means for independently transferring the voltage signal output from the means in a first direction via the plurality of signal lines;
Two second reading means for transferring the voltage signal transferred by the first reading means in a second direction;
A signal line connected to one conversion unit of unit pixels arranged every other column and a signal line connected to the other conversion unit of unit pixels arranged in the other columns are connected to the two second Selecting means for selecting which of the reading means to connect,
An image pickup device, wherein signal lines not selected by the selection unit are connected to the two second readout units different from each other in every other column. The imaging device according to any one of claims 1 to 6 ,
Processing means for processing the voltage signal read from the second reading means into an image signal;
An image pickup apparatus comprising: storage means for storing an image signal processed by the processing means.