JP5909945B2 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate having a SON (silicon on nothing) structure and a method for manufacturing a semiconductor device such as a pressure sensor using the semiconductor substrate.

  Conventionally, there is a semiconductor device such as a pressure sensor formed using a silicon substrate having a SON structure. A method for manufacturing the silicon substrate 500 having the SON structure will be described.

13 to 15 are main part manufacturing process diagrams showing a conventional method for manufacturing a silicon substrate having a SON structure in the order of processes. (A) is a top view, (b) is sectional drawing.
As shown in FIG. 13, a thermal oxide film is formed on a silicon substrate 51, and this thermal oxide film is patterned with a resist mask 53 to form a thermal oxide film mask 52 for forming holes. In the figure, 54a is a through hole of the thermal oxide film mask 52 for forming the hole 61 in the silicon substrate 1, 55a is a through hole of the resist mask 53 for forming the through hole 54a, and 56 is a through hole of the resist mask 53. Is a group.

  Next, as shown in FIG. 14, anisotropic dry etching is performed using a thermal oxide film mask 52 to form a hole group 62 composed of a plurality of holes 61 having the same dimensions. For example, the diameter D7 of the hole 61 is about 0.6 μm, the hole interval W7 is about 0.6 μm, and the hole depth T7 is about 5 μm. As shown in FIG. 16, the center point 61a of the hole 61 is arranged at the lattice point 71a of the square lattice 71, and the interval W8 between the lattice points 71a is 1.2 μm.

  Next, as shown in FIG. 15, after the thermal oxide film mask 52 is removed by wet etching, the silicon substrate 51 is annealed at 1150 ° C. in a hydrogen atmosphere, for example. By performing the annealing process, due to the migration effect, the upper portion of the hole 61 is gradually closed to become a large flat plate-like cavity 63, and the silicon substrate 500 having the SON structure is completed.

  In FIG. 15, when the flat cavity 63 is formed by a single hole 61, the step S of the step portion 65 (see FIG. 15) decreases as the hole diameter D7 decreases and the hole interval W7 increases. .

  The method of forming this SON structure is a method using the surface migration of silicon. By performing a high-temperature heat treatment (annealing treatment) on the silicon substrate 51 in a hydrogen atmosphere or high vacuum, the surface diffusion of silicon atoms is achieved. This utilizes the fact that the surface is flattened at the atomic level.

A stepped portion 65 is formed at the boundary (edge portion 64) between the portion where the flat cavity 63 is formed and the portion where the cavity 63 is not formed, and the step where the cavity 63 is formed becomes low.
In Patent Document 1, a plurality of grooves are two-dimensionally formed on the surface of a silicon substrate, and then the silicon substrate is subjected to a heat treatment to change the plurality of grooves into one flat cavity, thereby increasing costs. In addition, it is disclosed that an SOI structure can be formed without degrading reliability.

  Patent Document 2 describes a method for manufacturing a silicon carbide single crystal substrate having a cavity inside. A step of forming a cavity in the silicon carbide single crystal substrate; and a first surface of the silicon carbide single crystal substrate facing the space in the cavity, the silicon carbide single crystal facing the first surface across the cavity. By a manufacturing method including a step of sublimating silicon carbide from the first surface and crystallizing the sublimated silicon carbide on the second surface at a higher temperature than the second surface of the crystal substrate. It is disclosed that a method for producing a high-quality silicon carbide single crystal substrate can be provided.

JP 2001-144276 A JP 2003-95797 A

  As shown in FIG. 15B, when the slope 66 of the stepped portion 65 formed in the edge portion 64 is steep, a semiconductor device such as a pressure sensor is manufactured using the silicon substrate 500 having this SON structure. At this time, in the patterning step, as shown in FIG. 17, the resist 67 is accumulated in the stepped portion 65, and the thickness Q of the resist 67 is increased, thereby causing a resist mask defect (patterning defect or the like). Further, as shown in FIG. 18, when the wiring 68 is formed in the steep stepped portion 65, the disconnection 69 is easily caused, and the reliability of the semiconductor device is lowered. Furthermore, when the stepped portion 65 is steep, a crystal defect 70 is likely to occur at this location as shown in FIG. 19 due to thermal stress applied during the manufacturing process. The presence of the crystal defects 70 adversely affects the characteristics of the semiconductor device and lowers the reliability. These cause the same inconvenience when an epitaxial layer (not shown) is formed on the silicon substrate 51 including the SON structure (cavity 63) and a semiconductor device such as a pressure sensor is manufactured.

  In the above-mentioned Patent Document 1, as a specific method for reducing the influence of the step, “a wide pattern is provided for the pattern of the portion corresponding to the step. Before forming the flat cavity, The area other than the cavity formation area is dug down to the extent that it is lowered in advance, or only the cavity formation area is lifted up after the flat cavity has been formed, or the entire surface is polished by CMP to the surface. Can be flattened. " However, these methods increase the number of masks and increase the manufacturing cost.

  In Patent Document 2, it is described that a cavity is formed in a silicon carbide single crystal substrate, and the quality of the single crystal is improved by sublimation and crystallization of silicon carbide inside the silicon carbide single crystal substrate. However, the step portion formed on the substrate surface (edge portion) on the cavity is not described.

  An object of the present invention is to provide a method for manufacturing a semiconductor substrate having a SON structure that can solve the above-described problems and can gently tilt the step portion formed at the edge portion, and a method for manufacturing a semiconductor device using the semiconductor substrate. Is to provide.

In order to achieve the above object, according to the first aspect of the present invention, in the method for manufacturing a semiconductor substrate having a SON structure, a first hole comprising a plurality of first holes on the surface of the semiconductor substrate. forming for forming a second hole group consisting arranged the first second hole plurality have is shallow than the diameter small interval size Ku depth hole so as to surround the first hole group and the hole group at the same time Then, heat treatment is performed at a high temperature exceeding 1100 ° C. in a hydrogen atmosphere or a vacuum atmosphere to close the upper portions of the first hole of the first hole group and the second hole of the second hole group, thereby forming one flat cavity. And forming the second hole group, so that the slope of the stepped portion formed on the surface near the end of the flat plate-shaped cavity is made gentle. Semiconductor substrate The manufacturing method is as follows.

According to the invention of claim 2, wherein the appended claims, claims in the invention described in claim 1, wherein the second is arranged so as to surround the hole group, the second distance smaller diameter than the hole is widely look including the step of forming a third hole group depth comprises a plurality of third holes shallow simultaneously with the second hole group, in the step of forming the one flat of the cavity, by the heat treatment, the first The upper portions of the first hole, the second hole, and the third hole may be closed to form one flat cavity .

  According to a third aspect of the present invention, in the first and second aspects of the invention, the first hole is formed at each lattice point of a lattice in which the lattice points are arranged in a square or equilateral triangle. A center point, a center point of the second hole, and a center point of the third hole may be arranged, respectively.

  According to the invention described in claim 4, in the invention described in claim 1, the plurality of first lattice points are arranged in a square shape, and each center of the first hole is located at each first lattice point. It is preferable that a point is arranged, the second lattice point is connected to the first lattice point located on the outermost periphery, the second lattice point is an equilateral triangle, and the second hole is disposed at each second lattice point.

According to the invention described in claim 5 of the claims , in any one of claims 1 to 4, the flat plate-like cavity is thinner at the outer peripheral portion than at the central portion. .
According to the invention described in claim 6, the semiconductor device manufactured using the semiconductor substrate having the SON structure manufactured by the manufacturing method according to any one of claims 1 to 5. In the manufacturing method, a step of applying a resist to the surface of the semiconductor substrate and forming a resist mask by photolithography, and using the resist mask, an electric circuit is formed on the surface layer including the upper part of the SON structure of the semiconductor substrate Forming a diffusion layer and an electric wiring connecting the diffusion layers.

  For this reason, the hole diameter dimension for arranging the trench holes in the semiconductor substrate is set such that the hole diameter on the side (edge portion) near the portion where the SON structure is not formed is reduced and the interval is increased. Thereby, since the hole diameter near the edge portion is small, the depth is formed shallower, the deformation due to annealing proceeds slightly earlier than the central portion, and the flatness of the semiconductor substrate surface where the holes are closed also proceeds. As a result, the amount by which the surface of the semiconductor substrate is lowered is reduced, and the slope of the stepped portion becomes gentle.

  According to the present invention, by decreasing the diameter of the hole in the edge portion and widening the interval, the slope of the step portion at the edge portion of the semiconductor substrate surface having the SON structure in which the plate-like cavity is formed becomes gentle.

As described above, since the slope of the stepped portion becomes gentle, when a semiconductor device such as a pressure sensor is formed on this semiconductor substrate, resist mask defects can be prevented and the manufacturing cost can be reduced.
In addition, disconnection of the wiring formed in the step portion can be prevented, and the reliability of the semiconductor device can be improved.

  Furthermore, stress applied to the semiconductor substrate in the vicinity of the stepped portion is relieved, and generation of crystal defects can be prevented, so that a favorable semiconductor substrate and semiconductor device can be provided.

It is a partial manufacturing process diagram of the semiconductor substrate having the SON structure of the first embodiment of the present invention. FIG. 2 is a partial manufacturing process diagram of the semiconductor substrate having the SON structure according to the first embodiment of the invention, following FIG. 1; FIG. 3 is a partial manufacturing process diagram of the semiconductor substrate having the SON structure according to the first embodiment of the invention, following FIG. 2; It is a figure of the square lattice which arrange | positions a hole. It is a figure of the grating | lattice which arrange | positions the center point of a hole, (a) is an equilateral triangle figure, (b) is a figure which mixed the square lattice and the equilateral triangle lattice. It is a top view at the time of arrange | positioning a small 3rd hole group in the outer periphery of a 2nd hole group. It is principal part manufacturing process sectional drawing of the semiconductor device manufactured using the semiconductor substrate which has SON structure of 2nd Example of this invention. FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device manufactured using the semiconductor substrate having the SON structure of the second embodiment of the invention, following FIG. 7. FIG. 9 is a cross-sectional view of the essential part manufacturing process of the semiconductor device manufactured using the semiconductor substrate having the SON structure of the second embodiment of the invention, following FIG. 8; FIG. 10 is a cross-sectional view showing the main part manufacturing process of the semiconductor device manufactured using the semiconductor substrate having the SON structure according to the second embodiment of the invention, following FIG. 9; FIG. 11 is a principal part manufacturing process cross-sectional view of the semiconductor device manufactured using the semiconductor substrate having the SON structure of the second embodiment of the invention, following FIG. 10; FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device manufactured using the semiconductor substrate having the SON structure of the second embodiment of the invention, following FIG. 11. It is a principal part manufacturing-process figure about the manufacturing method of the silicon substrate which has the conventional SON structure. FIG. 14 is a manufacturing process diagram of principal parts of a method for manufacturing a silicon substrate having a conventional SON structure, following FIG. 13; FIG. 15 is a main part manufacturing step view of the method for manufacturing the silicon substrate having a conventional SON structure, following FIG. 14; It is the figure which has arrange | positioned the center point of the hole 61 in the square lattice. It is the figure where the resist accumulated in the level | step-difference part and the thickness of the resist became thick. It is the figure which the wiring formed in the level | step-difference part disconnected. It is the figure which the crystal defect generate | occur | produced in the level | step-difference part.

Embodiments will be described in the following examples.
<Example 1>
1 to 3 are main part manufacturing process diagrams showing a method of manufacturing a semiconductor substrate having a SON structure according to the first embodiment of the present invention in the order of processes. (A) is a top view, (b) is sectional drawing. Here, the silicon substrate 100 having the SON structure will be described as an example. These drawings are schematic views.

  As shown in FIG. 1, a thermal oxide film is formed on a single crystal silicon substrate 1, and a patterned resist mask 3 is formed thereon. Subsequently, by using this resist mask 3, the thermal oxide film 2 is formed by patterning the thermal oxide film by anisotropic etching such as RIE (Reactive Ion Etching). The first through hole 4a in the figure is a through hole of the thermal oxide film mask 2 for forming a large first hole in the silicon substrate 1. The second through hole 4 b is a through hole of the thermal oxide film mask 2 that forms a small second hole in the silicon substrate 1. The third through hole 5a is a through hole of the resist mask 3 for forming the first through hole 4a. The fourth through hole 5b is a through hole of the resist mask 3 that forms the second through hole 4b. The first through hole group 6 is a through hole of the resist mask 3, and the second through hole group 7 is a through hole group of the resist mask 3 that surrounds the outer periphery of the first through hole group 6.

  Next, as shown in FIG. 2, after the resist mask 3 is carbonized and peeled off, two kinds of holes 11, 11 are formed on the surface of the silicon substrate 1 by anisotropic etching, for example, RIE, using the thermal oxide film mask 2. 12 is formed. The large first hole 11 is arranged in the center, and its diameter D1 is 0.6 μm, the interval W1 is 0.6 μm, and the depth T1 is about 5 μm. The small second holes 12 are arranged on the outer periphery so as to surround the first hole group 13, and the diameter D2 thereof is 0.5 μm, the interval W2 is 0.7 μm, and the depth T2 is about 4 μm. The interval W3 between the first hole 11 and the second hole 12 is 0.65 μm. A group of the first holes 11 is a first hole group 13, and a group of the second holes 12 is a second hole group 14. A second hole group 14 is disposed so as to surround the first hole group 13. The second hole group 14 includes second holes 12 arranged in about 2 to 5 rows (2 rows in the figure). As shown in FIG. 4, the center point 11 a of the first hole 11 and the center point 12 a of the second hole 12 are arranged at each lattice point 15 a of the same square lattice 15. The interval W4 between the lattice points 15a is 1.2 μm here. Further, since the first hole 11 and the second hole 12 are formed simultaneously, the depth T2 of the second hole 12 having a small diameter is shallower than the depth T1 of the first hole 11 having a large diameter. Further, here, a thermal oxide film is used as a mask material for forming the holes 11 and 12, but in the anisotropic etching for forming the holes, a thermal oxide film can be used as long as the material has a high selection ratio with silicon. It is not limited to.

  Next, as shown in FIG. 3, after removing the thermal oxide film mask 2, in a non-oxidizing atmosphere under reduced pressure, for example, in a 100% hydrogen atmosphere having a heat treatment temperature of 1150 ° C. and an atmospheric pressure of 10 Torr (1330 Pa). Perform high temperature annealing. By performing the high temperature annealing, the upper openings of the holes 11 and 12 are closed, and one large flat plate-like cavity 16 is formed inside the silicon substrate 1 to complete the silicon substrate 100 having the SON structure. When the heat treatment temperature is lower than 1100 ° C., migration hardly occurs, so 1100 ° C. or higher is preferable. The pressure is 10 Torr (1330 Pa), but it may be higher. Moreover, it may be performed in a vacuum atmosphere.

  A stepped portion 18 is formed on the semiconductor surface (edge portion 17) near the outer peripheral portion of the flat plate-like cavity 16, and the slope 19 of the stepped portion 18 becomes gentle by forming the second hole group 14. .

  As described above, the diameter D2 of the second hole 12 disposed in the edge portion 17 is made smaller than the diameter D1 of the first hole 11, and the interval W2 between the second holes 12 is made wider than the interval W1 between the first holes 11. The slope 19 of the step portion 18 formed in the edge portion 17 becomes gentle. Here, the slope 19 is the slope (X / Y).

  As described above, since the slope 19 of the stepped portion 18 becomes gentle, crystal defects formed in this portion are reduced, and the characteristic failure of a semiconductor device such as a pressure sensor using this silicon substrate is reduced. Improves.

In addition, resist pooling at the stepped portion 18 is prevented, and defects in the resist mask 3 are reduced.
Next, a lattice for arranging the center points of holes different from those shown in FIG. 2 will be described.

  FIG. 5 is a diagram of a grid for arranging the center points of holes. FIG. 5A is a diagram in which the grid points 21a are arranged in an equilateral triangle grid 23, and FIG. 5B is a center point 11a of the first hole. Is a square lattice 22, and a lattice point 23 a at which the center point 12 a of the second hole 12 is disposed is an equilateral triangular lattice 23. The intervals between the lattice points 21a, 22a, and 23a are the same. The diameters D1 and D2 and the intervals W1 and W2 of the first hole 11 and the second hole 12 are the same as in the above case. In this case, the same effect as described above can be obtained.

FIG. 6 is a plan view when the third hole group 25 is arranged so as to surround the outer periphery of the second hole group 14. The diameter D3 of the third hole 24 is smaller than the diameter D2 of the second hole 12. In this case, the slope 19 of the stepped portion 18 is preferable because it becomes more gentle than in the case of FIG. Also in this case, the lattice point spacing is the same as in FIG. Furthermore, although not shown in the drawing, a fourth hole group composed of fourth holes that are smaller than the third holes and wide in intervals may be formed so as to surround the outer periphery of the third hole group 25.
<Example 2>
7 to 12 are cross-sectional views showing a main part manufacturing process showing a manufacturing method of a semiconductor device manufactured using a semiconductor substrate having a SON structure according to the second embodiment of the present invention in the order of steps. Here, a manufacturing method of the pressure sensor 200 manufactured using the silicon substrate 100 having the SON structure will be described. The SON structure is used as a pressure sensor diaphragm.

  First, as shown in FIG. 7, a silicon substrate 100 having a SON structure manufactured by the manufacturing method of the present invention is prepared. The thickness of the flat cavity 16 is about several μm. In order to simplify the explanation, the cavity 16 is narrowed at the outer peripheral portion as indicated by the oblique line 16a, but here, the cross-sectional shape of the flat cavity 16 is indicated by a rectangle.

Next, as shown in FIG. 8, an epitaxial layer 31 having a thickness P of about 8 μm is formed on the silicon substrate 1.
Next, as shown in FIG. 9, a resist is applied on the epitaxial layer 31, and a resist mask 32 for forming a bridge resistance, an electric circuit, etc. of the pressure sensor is formed by photolithography.

  Next, as shown in FIG. 10, using this resist mask 32, each diffusion layer 33 for forming a bridge resistance, an electric circuit, etc. of the pressure sensor is formed, and the resist mask 32 is removed.

  Next, as shown in FIG. 11, a detection hole 34 reaching the cavity 16 of the SON structure from the back surface of the silicon substrate 1 is formed. The detection hole 34 is necessary for introducing a gas or a liquid for detecting / measuring pressure to the diaphragm.

Next, as shown in FIG. 12, a wiring for connecting the respective diffusion layers 33 is formed, and the pressure sensor 200 is completed by covering the case 35.
Since the slope 19 of the step portion 18 on the surface near the SON structure becomes gentle, a defect in the resist mask 3 can be prevented and the manufacturing cost can be reduced.

  Moreover, disconnection of the wiring formed in the step part 18 can be prevented. Furthermore, the stress applied to the silicon substrate 1 near the stepped portion 18 can be reduced, and the generation of crystal defects can be suppressed. As a result, the characteristic failure of the semiconductor device can be prevented and the reliability can be improved.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Thermal oxide film mask 3 Resist mask 4a 1st through-hole 4b 2nd through-hole 5a 3rd through-hole 5b 4th through-hole 6 1st through-hole group 7 2nd through-hole group 11 1st hole 11a, 12a 24a center point 12 2nd hole 13 1st hole group 14 2nd hole group 15, 21, 22 square lattice 15a, 21a, 22a, 23a lattice point 16 flat plate-like cavity 16a oblique line 17 edge portion 18 step portion 19 slope 23 Equilateral triangular lattice 24 Third hole 25 Third hole group 31 Epitaxial layer 32 Resist mask 33 Diffusion layer 34 Detection hole 35 Case 100 Silicon substrate having SON structure 200 Pressure sensor D1 Diameter of first hole D2 Diameter of second hole W1 First 1 hole interval W2 2nd hole interval W3 1st hole and 2nd hole interval T1 1st hole depth T2 2nd hole depth

Claims (6)

In a method for manufacturing a semiconductor substrate having a SON structure,
The first hole group and the first is arranged so as to surround the hole group the first second hole plurality have is shallow than the diameter small interval size Ku depth hole comprising a plurality of first holes in the surface of the semiconductor substrate Forming a second hole group consisting of:
Heat-treating in a non-oxidizing atmosphere under reduced pressure to close each upper portion of the first hole of the first hole group and the second hole of the second hole group to form one flat cavity. A method for manufacturing a semiconductor substrate, comprising: Wherein disposed second to surround the hole group, to form a third hole group consisting of the second third hole plurality have than the diameter small interval size Ku depth shallow hole simultaneously with the second hole group the process only contains,
In the step of forming the one flat cavity, the upper portion of each of the first hole, the second hole, and the third hole is closed by the heat treatment to form one flat cavity. A method for manufacturing a semiconductor substrate according to claim 1.   A center point of the first hole, a center point of the second hole, and a center point of the third hole are arranged at each lattice point of a lattice in which the lattice points are arranged in a square or equilateral triangle, respectively. The manufacturing method of the semiconductor substrate of Claim 1 or 2.   A plurality of first grid points are arranged in a square shape, each center point of the first hole is arranged at each first grid point, and the second grid point connected to the first grid point located on the outermost periphery is the second grid point. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the lattice points are arranged in an equilateral triangle, and the second holes are disposed at the second lattice points. 5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the flat cavity has a thinner outer peripheral portion than a central portion. In the manufacturing method of the semiconductor device manufactured using the semiconductor substrate which has the SON structure manufactured with the manufacturing method according to any one of claims 1 to 5 ,
Forming an epitaxial layer on the semiconductor substrate having the SON structure;
Applying a resist on the epitaxial layer and forming a resist mask by photolithography;
Using the resist mask, forming each diffusion layer constituting an electric circuit on the surface layer of the epitaxial layer and an electric wiring connecting the diffusion layer;
A method for manufacturing a semiconductor device, comprising: