JP5904375B2 - Power supply control device - Google Patents

Power supply control device Download PDF

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Publication number
JP5904375B2
JP5904375B2 JP2013120499A JP2013120499A JP5904375B2 JP 5904375 B2 JP5904375 B2 JP 5904375B2 JP 2013120499 A JP2013120499 A JP 2013120499A JP 2013120499 A JP2013120499 A JP 2013120499A JP 5904375 B2 JP5904375 B2 JP 5904375B2
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abnormality
mosfets
semiconductor power
power supply
control device
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JP2014239132A (en
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佑樹 杉沢
佑樹 杉沢
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Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
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Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
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Priority to JP2013120499A priority Critical patent/JP5904375B2/en
Priority to PCT/JP2014/063669 priority patent/WO2014196376A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/04—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
    • H02H3/044—Checking correct functioning of protective arrangements, e.g. by simulating a fault

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)

Description

本発明は、電力供給制御装置に関する。   The present invention relates to a power supply control device.

従来、電源から負荷に至る経路上に半導体パワー素子を配し、この半導体パワー素子のオンオフを制御することで、電源から負荷に供給される電力を制御する電力供給制御装置が知られている。   2. Description of the Related Art Conventionally, a power supply control device that controls power supplied from a power supply to a load by arranging a semiconductor power element on a path from the power supply to the load and controlling on / off of the semiconductor power element is known.

ここで、半導体パワー素子が故障すると、この半導体パワー素子は、通常、高い抵抗を生じさせて通電可能な状態とされる。
そのため、たとえ、半導体パワー素子がオフ状態に制御されていたとしても、通電してしまい、その抵抗値の高さ故に、異常発熱が生じうる。半導体パワー素子が異常発熱すると、発煙、発火等の不具合が生じることが懸念される。 Here, when the semiconductor power element fails, this semiconductor power element is normally brought into a state where it can be energized by generating a high resistance.
For this reason, even if the semiconductor power element is controlled to be in an OFF state, it is energized and abnormal heat generation may occur due to its high resistance value. If the semiconductor power element generates abnormal heat, there is a concern that problems such as smoke and fire may occur.

特許文献１は、半導体パワー素子としてのＭＯＳＦＥＴがベース上に傾斜して保持された回路基板に半田付けされて実装されている。ＭＯＳＦＥＴの異常発熱で半田が溶解すると、ＭＯＳＦＥＴが自重でストッパ部材の位置まで脱落し、ＭＯＳＦＥＴがオープンな状態となり、異常発熱による不具合が防止されるようになっている。   In Patent Document 1, a MOSFET as a semiconductor power element is mounted by being soldered to a circuit board held on an inclination on a base. When the solder is melted due to the abnormal heat generation of the MOSFET, the MOSFET falls off to the position of the stopper member by its own weight, and the MOSFET is opened, so that the trouble due to the abnormal heat generation is prevented.

特開２００１−６０７５０号公報JP 2001-60750 A

ところで、上記特許文献１の構成では、半導体パワー素子の異常発熱による不具合を防止するために、回路基板を傾斜させる必要があるため、装置の構成が複雑になるという問題がある。   By the way, in the structure of the said patent document 1, since it is necessary to incline a circuit board in order to prevent the malfunction by abnormal heat generation of a semiconductor power element, there exists a problem that the structure of an apparatus becomes complicated.

本発明は上記のような事情に基づいて完成されたものであって、簡素な構成で、半導体パワー素子の異常発熱による不具合を防止することが可能な電力供給制御装置を提供することを目的とする。   The present invention has been completed based on the above-described circumstances, and an object thereof is to provide a power supply control device capable of preventing a malfunction due to abnormal heat generation of a semiconductor power element with a simple configuration. To do.

本発明は、電源から負荷へ供給される電力を制御する電力供給制御装置であって、前記電源から前記負荷に至る経路に並列に配される複数の半導体パワー素子と、前記半導体パワー素子のオンオフを制御する制御部と、前記半導体パワー素子の異常を検出する異常検出部と、を備え、前記制御部は、前記複数の半導体パワー素子をオン状態とする駆動信号を出力していないことにより当該複数の半導体パワー素子の全てがオフ状態のときに前記異常検出部が前記半導体パワー素子の異常を検出すると、前記異常が生じていない前記半導体パワー素子が前記オン状態となるように制御する。


The present invention is a power supply control device that controls power supplied from a power supply to a load, and includes a plurality of semiconductor power elements arranged in parallel in a path from the power supply to the load, and on / off of the semiconductor power elements A control unit that controls the semiconductor power element, and an abnormality detection unit that detects an abnormality of the semiconductor power element, and the control unit does not output a drive signal for turning on the plurality of semiconductor power elements. when all of the plurality of semiconductor power elements the abnormality detecting unit in the off state when detecting an abnormality of the power semiconductor device, wherein the abnormality occurs non the semiconductor power element is controlled to be the oN state.


本構成によれば、半導体パワー素子がオフ状態のときに異常検出部が半導体パワー素子の異常を検出すると、異常が生じていない半導体パワー素子がオン状態となるように制御される。これにより、異常が生じた半導体パワー素子が大きいオン抵抗を伴って通電可能となると、異常が生じていないため比較的オン抵抗が小さい半導体パワー素子側の通電電流が大きくなるように分流する。   According to this configuration, when the abnormality detection unit detects an abnormality in the semiconductor power element when the semiconductor power element is in the off state, the semiconductor power element in which no abnormality has occurred is controlled to be in the on state. As a result, when the semiconductor power element in which an abnormality has occurred can be energized with a large on-resistance, since no abnormality has occurred, the current is divided so that the energizing current on the semiconductor power element side having a relatively small on-resistance becomes large.

これにより、装置の構成を大きく変更しなくても、異常が発生した半導体パワー素子の通電電流が抑制されることで当該半導体パワー素子の発熱が抑制されるため、簡素な構成で、半導体パワー素子の異常発熱による不具合を防止することができる。   As a result, even if the configuration of the apparatus is not largely changed, the conduction current of the semiconductor power element in which an abnormality has occurred is suppressed, so that heat generation of the semiconductor power element is suppressed. It is possible to prevent problems caused by abnormal heat generation.

上記構成の実施態様として以下の構成を有すれば好ましい。
・前記異常検出部が前記半導体パワー素子の異常を検出すると、前記制御部は、全ての前記半導体パワー素子がオン状態となるように制御する。
このようにすれば、複数の半導体パワー素子のうちのいずれの半導体パワー素子に異常が発生したかを検出しなくても、異常発熱による不具合を防止することができるため、より一層、半導体パワー素子の異常発熱による不具合を防止するための構成を簡素化することが可能になる。 It is preferable to have the following configuration as an embodiment of the above configuration.
When the abnormality detection unit detects an abnormality in the semiconductor power element, the control unit controls all the semiconductor power elements to be in an on state.
In this way, since it is possible to prevent a malfunction due to abnormal heat generation without detecting which one of the plurality of semiconductor power elements is abnormal, it is possible to further improve the semiconductor power element. It is possible to simplify the configuration for preventing problems caused by abnormal heat generation.

・前記異常検出部は、前記複数の半導体パワー素子の少なくとも１個の半導体パワー素子の異常によって生じる電圧の変化を検出する。
少なくとも１個の半導体パワー素子が異常により高い抵抗を伴ってオン状態となると、回路の電圧に変動が生じるため、この電圧の変動を検出することで、少なくとも１個の半導体パワー素子に異常が生じていることを検出することができる。 The abnormality detection unit detects a change in voltage caused by an abnormality in at least one semiconductor power element of the plurality of semiconductor power elements.
When at least one semiconductor power element is turned on with an abnormally high resistance, the circuit voltage fluctuates. By detecting this voltage fluctuation, at least one semiconductor power element is abnormal. Can be detected.

・前記半導体パワー素子に異常が生じたことを外部に報知する報知手段を備える。
異常が生じていない半導体パワー素子をオン状態とする場合、本来オフ状態であるため通電されていないはずの負荷への不要な通電が行われている可能性がある。本構成によれば、報知手段の報知により半導体パワー素子の異常を認識することが可能になるとともに、異常を認識したユーザが適切な処置をすることで負荷への不要な通電を抑制することが可能になるとともに、さらなる異常状態が発生する前に電力供給制御装置の交換や修理が可能になり、異常発熱の発生を防止することができる。 A notification means for notifying the outside that an abnormality has occurred in the semiconductor power element is provided.
When turning on a semiconductor power element in which no abnormality has occurred, there is a possibility that unnecessary energization is applied to a load that should not have been energized because it is originally in an off state. According to this configuration, it is possible to recognize the abnormality of the semiconductor power element by the notification of the notification means, and it is possible to suppress unnecessary energization to the load by the user who has recognized the abnormality taking appropriate measures. In addition, the power supply control device can be replaced or repaired before a further abnormal state occurs, thereby preventing abnormal heat generation.

本発明によれば、簡素な構成で、半導体パワー素子の異常発熱による不具合を防止することが可能となる。   According to the present invention, it is possible to prevent problems due to abnormal heat generation of a semiconductor power element with a simple configuration.

実施形態１の電源と負荷との間に配された電力供給制御装置の電気的構成を示す図The figure which shows the electric constitution of the electric power supply control apparatus distribute | arranged between the power supply and load of Embodiment 1. 実施形態２の電源と負荷との間に配された電力供給制御装置の電気的構成を示す図The figure which shows the electric constitution of the electric power supply control apparatus distribute | arranged between the power supply and load of Embodiment 2. FIG.

＜実施形態１＞
以下、実施形態１について、図１を参照して説明する。
電力供給制御装置１０は、図１に示すように、自動車等の車両の電源Ｂ（バッテリ）から車両のランプ、モータ、ヒータなどの負荷Ｌに至る経路（導電路）に設けられて負荷Ｌに供給される電力の制御を行うものである。
電源Ｂの＋側は、車両の図示しないインバータ、及び、電力供給制御装置１０の入力部１８に接続され、電力供給制御装置１０の出力部１９は、負荷Ｌに接続されている。 <Embodiment 1>
The first embodiment will be described below with reference to FIG.
As shown in FIG. 1, the power supply control device 10 is provided in a path (conductive path) from a power source B (battery) of a vehicle such as an automobile to a load L such as a lamp, motor, and heater of the vehicle. It controls the power supplied.
The + side of the power supply B is connected to an inverter (not shown) of the vehicle and the input unit 18 of the power supply control device 10, and the output unit 19 of the power supply control device 10 is connected to the load L.

電力供給制御装置１０は、導電路がプリント配線された回路基板に電子部品が実装されて構成されており、複数（本実施形態では３個）のＭＯＳＦＥＴ１２Ａ〜１２Ｃ（「半導体パワー素子」の一例）と、複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃのオンオフを制御する制御回路１３とを備えている。
この電力供給制御装置１０はＩＰＤ（Intelligent Power Device）として一体的に構成されている。なお、電力供給制御装置１０の全体でＩＰＤを構成するものに限らず、少なくともＭＯＳＦＥＴ１２Ａ〜１２Ｃを含む回路でＩＰＤを構成してもよい。 The power supply control device 10 is configured by mounting electronic components on a circuit board on which conductive paths are printed and wired, and a plurality (three in this embodiment) of MOSFETs 12A to 12C (an example of “semiconductor power element”). And a control circuit 13 for controlling on / off of the plurality of MOSFETs 12A to 12C.
The power supply control device 10 is integrally configured as an IPD (Intelligent Power Device). Note that the IPD is not limited to the entire power supply control device 10 and may be configured by a circuit including at least the MOSFETs 12A to 12C.

複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃは、パッケージされた一つのチップ１１内に収容されており、共に同一構成のＮ型のＭＯＳＦＥＴ１２Ａ〜１２Ｃ（パワーＭＯＳＦＥＴ）である。
複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃは、電力供給制御装置１０の入力部１８と出力部１９との間の経路（導電路）に並列に配され、互いのドレイン同士が接続されて同電位とされるとともに、互いのソース同士が接続されて同電位とされている。
これにより、電源Ｂ側からの電流が複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃに分流して共通の負荷Ｌに供給される。なお、本実施形態では、複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃは、同一平面上でわずかに間隔を空けて分離されており、複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃの各ソースは、チップ１１の外部に配された導電路の接続部１７で接続されている。この接続部１７は、ＩＰＤの内部に配するものに限らず、ＩＰＤの外部に設けてもよい。 The plurality of MOSFETs 12A to 12C are accommodated in one packaged chip 11, and are N-type MOSFETs 12A to 12C (power MOSFETs) having the same configuration.
The plurality of MOSFETs 12 </ b> A to 12 </ b> C are arranged in parallel in a path (conductive path) between the input unit 18 and the output unit 19 of the power supply control device 10, and their drains are connected to have the same potential, The sources are connected to each other and have the same potential.
As a result, the current from the power source B side is shunted to the plurality of MOSFETs 12A to 12C and supplied to the common load L. In the present embodiment, the plurality of MOSFETs 12 </ b> A to 12 </ b> C are separated on the same plane with a slight space therebetween, and each source of the plurality of MOSFETs 12 </ b> A to 12 </ b> C is a conductive path arranged outside the chip 11. They are connected by a connection unit 17. The connecting portion 17 is not limited to being provided inside the IPD, and may be provided outside the IPD.

各ＭＯＳＦＥＴ１２Ａ〜１２Ｃは、一個少ない個数のＭＯＳＦＥＴ（例えば２個のＭＯＳＦＥＴ１２Ｂ，１２Ｃ）で負荷Ｌへ供給したとしても異常が生じない電流容量を備えたものが用いられている。
ここで、ＭＯＳＦＥＴは、通常、最大使用温度（限界温度）まで余裕を持たせた温度で使用するように設計されているため（ディレーティング）、通常並列にＭＯＳＦＥＴ１２Ａ〜１２Ｃを有するチップ１について、ＭＯＳＦＥＴ１２Ｂ，１２Ｃのみをオン状態としたとしても最大使用温度以下で使用することが可能である。したがって、通常のチップ１１の構成を大きく変更しなくてもＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常発熱による不具合を防止できるようになっている。 Each of the MOSFETs 12A to 12C is provided with a current capacity that does not cause an abnormality even if the MOSFET 12A to 12C is supplied to the load L by a small number of MOSFETs (for example, two MOSFETs 12B and 12C).
Here, since the MOSFET is normally designed to be used at a temperature with a margin up to the maximum use temperature (limit temperature) (derating), the MOSFET 12B is usually used for the chip 1 having the MOSFETs 12A to 12C in parallel. , Even if only 12C is turned on, it can be used below the maximum operating temperature. Therefore, problems due to abnormal heat generation of the MOSFETs 12A to 12C can be prevented without greatly changing the configuration of the normal chip 11.

また、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常発生時には、外部にダイアグ信号ＳＤが報知されるようになっているため、少ない個数のＭＯＳＦＥＴ１２Ｂ，１２Ｃでの長期間の使用が抑制されるように構成されている。
なお、各ＭＯＳＦＥＴ１２Ａ〜１２Ｃの電流容量は、ＭＯＳＦＥＴが一個少ない場合に限らず、複数個少ないＭＯＳＦＥＴで負荷Ｌへ供給したとしても故障等の異常が生じない電流容量に設定することも可能である。 In addition, when an abnormality occurs in the MOSFETs 12A to 12C, the diagnosis signal SD is notified to the outside, so that long-term use with a small number of MOSFETs 12B and 12C is suppressed.
The current capacity of each of the MOSFETs 12A to 12C is not limited to the case where the number of MOSFETs is small, but can be set to a current capacity that does not cause an abnormality such as a failure even when a plurality of MOSFETs are supplied to the load L.

制御回路１３は、各ＭＯＳＦＥＴ１２Ａ〜１２Ｃのオンオフを制御するＩＣ(Integrated Circuit)からなる制御部１４と、制御部１４からの駆動信号を受けて各ＭＯＳＦＥＴ１２Ａ〜１２Ｃをオンオフするドライブ回路１５Ａ〜１５Ｃと、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常を検出し、検出結果に応じた異常検出信号ＳＡを制御部１４に出力する異常検出部１６とを備える。   The control circuit 13 includes a control unit 14 composed of an IC (Integrated Circuit) for controlling on / off of the MOSFETs 12A to 12C, drive circuits 15A to 15C for receiving on / off signals from the control unit 14 and turning on / off the MOSFETs 12A to 12C. An abnormality detection unit 16 that detects abnormality of the MOSFETs 12A to 12C and outputs an abnormality detection signal SA corresponding to the detection result to the control unit 14 is provided.

ドライブ回路１５Ａ〜１５Ｃは、各ＭＯＳＦＥＴ１２Ａ〜１２Ｃに対応して設けられており、制御部１４からＭＯＳＦＥＴ１２Ａ〜１２Ｃをオン状態とする駆動信号を受けると、対応するＭＯＳＦＥＴ１２Ａ〜１２Ｃのゲートに電圧を印加して各ＭＯＳＦＥＴ１２Ａ〜１２Ｃのドレイン−ソース間を通電させる。   The drive circuits 15A to 15C are provided corresponding to the MOSFETs 12A to 12C. When a drive signal for turning on the MOSFETs 12A to 12C is received from the control unit 14, a voltage is applied to the gates of the corresponding MOSFETs 12A to 12C. Then, the drain-source of each of the MOSFETs 12A to 12C is energized.

異常検出部１６は、ＭＯＳＦＥＴ１２Ａ〜１２Ｃに故障等の異常が生じていることを検出するものである。
具体的には、ＭＯＳＦＥＴ１２Ａ〜１２Ｃのソースと負荷Ｌとの間の電位とアース電位との電位差を検出しており、所定時間における電位差の変動が所定以上となったときに、ＭＯＳＦＥＴ１２Ａ〜１２Ｃに異常が発生しているとして、異常が発生したことを示す異常検出信号ＳＡを制御部１４に出力する。制御部１４は、異常検出信号ＳＡを受けると、外部に異常が発生していることを示すダイアグ信号ＳＤを出力する。よって、制御部１４は、外部に異常を報知する報知手段を備えている。 The abnormality detection unit 16 detects that an abnormality such as a failure has occurred in the MOSFETs 12A to 12C.
Specifically, the potential difference between the potential between the source of the MOSFETs 12A to 12C and the load L and the ground potential is detected, and the MOSFET 12A to 12C is abnormal when the variation of the potential difference over a predetermined time becomes equal to or greater than a predetermined value. As a result, an abnormality detection signal SA indicating that an abnormality has occurred is output to the control unit 14. Upon receiving the abnormality detection signal SA, the control unit 14 outputs a diagnosis signal SD indicating that an abnormality has occurred outside. Therefore, the control part 14 is provided with the alerting | reporting means which alert | reports abnormality outside.

なお、異常検出部１６によるＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常検出方法は、これに限られない。例えば、各ＭＯＳＦＥＴ１２Ａ〜１２Ｃの各ゲートの電位を検出し、ゲートの電位が所定以上変動した場合に対応するＭＯＳＦＥＴ１２Ａ〜１２Ｃに異常が発生したと判断するようにしてもよい。   In addition, the abnormality detection method of MOSFET12A-12C by the abnormality detection part 16 is not restricted to this. For example, the potentials of the gates of the MOSFETs 12A to 12C may be detected, and it may be determined that an abnormality has occurred in the corresponding MOSFETs 12A to 12C when the gate potential fluctuates more than a predetermined value.

本実施形態の電力供給制御装置１０の動作を説明する。
外部のスイッチ等から負荷Ｌをオンオフするための信号Ｓを制御部１４が受けると、信号Ｓに応じてＭＯＳＦＥＴ１２Ａ〜１２Ｃのオンオフを制御する（複数をまとめてオンオフする）。 The operation of the power supply control device 10 of this embodiment will be described.
When the control unit 14 receives a signal S for turning on and off the load L from an external switch or the like, the MOSFETs 12A to 12C are controlled to be turned on and off according to the signal S (a plurality are turned on and off collectively).

ここで、全てのＭＯＳＦＥＴ１２Ａ〜１２Ｃがオフした状態にあるときにＭＯＳＦＥＴ１２Ａ〜１２Ｃのうちの１つ（例えばＭＯＳＦＥＴ１２Ａ）が故障すると、ＭＯＳＦＥＴ１２Ａが高いオン抵抗を有して短絡した状態となる。このＭＯＳＦＥＴ１２Ａの高いオン抵抗により、ＭＯＳＦＥＴ１２Ａ〜１２Ｃのドレインと負荷Ｌとの間の接続部１７の電圧が変化し、この変化した電圧に応じた電圧信号ＳＶは、異常検出部１６に与えられる。   Here, when one of the MOSFETs 12A to 12C (for example, the MOSFET 12A) fails when all the MOSFETs 12A to 12C are in an off state, the MOSFET 12A is short-circuited with a high on-resistance. Due to the high on-resistance of the MOSFET 12A, the voltage of the connection portion 17 between the drains of the MOSFETs 12A to 12C and the load L changes, and the voltage signal SV corresponding to the changed voltage is given to the abnormality detection portion 16.

異常検出部１６は、所定時間の電圧変化が少なくとも１個のＭＯＳＦＥＴに異常が生じていると判断できる所定電位差以上である場合には、いずれかのＭＯＳＦＥＴ１２Ａ〜１２Ｃに異常が発生している可能性が高いため、異常が発生したことを示す異常検出信号ＳＡを制御部１４に出力する。
制御部１４は、異常検出信号ＳＡを受けると、全てのＭＯＳＦＥＴ１２Ａ〜１２Ｃをオンするように、全てのドライブ回路１５Ａ〜１５Ｃに駆動信号を出力するとともに、電力供給制御装置１０の外部に、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの少なくとも１個に異常が発生していることを示すダイアグ信号ＳＤを出力する。 The abnormality detection unit 16 may have an abnormality in any of the MOSFETs 12 </ b> A to 12 </ b> C when the voltage change for a predetermined time is equal to or greater than a predetermined potential difference at which it can be determined that an abnormality has occurred in at least one MOSFET. Therefore, an abnormality detection signal SA indicating that an abnormality has occurred is output to the control unit 14.
Upon receiving the abnormality detection signal SA, the control unit 14 outputs drive signals to all the drive circuits 15A to 15C so as to turn on all the MOSFETs 12A to 12C, and the MOSFET 12A to the outside of the power supply control device 10 A diagnosis signal SD indicating that an abnormality has occurred in at least one of 12C is output.

本実施形態によれば、以下の作用・効果を奏する。
ＭＯＳＦＥＴ１２Ａ〜１２Ｃ（半導体パワー素子）がオフ状態のときに異常検出部１６がＭＯＳＦＥＴ１２Ａ（〜１２Ｃ）の異常を検出すると、異常が生じていないＭＯＳＦＥＴ１２Ａ〜１２Ｃがオン状態となるように制御される。これにより、異常が生じたＭＯＳＦＥＴ１２Ａが大きいオン抵抗を伴って通電可能となると、異常が生じていないため比較的オン抵抗が小さいＭＯＳＦＥＴ１２Ｂ，１２Ｃ側の通電電流が大きくなるように分流する。 According to the present embodiment, the following operations and effects are achieved.
When the abnormality detection unit 16 detects an abnormality of the MOSFET 12A (to 12C) when the MOSFETs 12A to 12C (semiconductor power elements) are in the off state, the MOSFETs 12A to 12C in which no abnormality has occurred are controlled to be in the on state. Thus, when the MOSFET 12A in which an abnormality has occurred can be energized with a large on-resistance, since no abnormality has occurred, the current is shunted so that the energizing current on the MOSFETs 12B and 12C side having a relatively small on-resistance becomes large.

これにより、装置の構成を大きく変更しなくても、異常が発生したＭＯＳＦＥＴ１２Ａ〜１２Ｃの通電電流が抑制されることで当該ＭＯＳＦＥＴ１２Ａ〜１２Ｃの発熱が抑制されるため、簡素な構成で、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常発熱による不具合を防止することができる。   Thereby, even if the configuration of the apparatus is not greatly changed, the energization current of the MOSFETs 12A to 12C in which an abnormality has occurred is suppressed, so that the heat generation of the MOSFETs 12A to 12C is suppressed. It is possible to prevent problems caused by abnormal heat generation.

また、異常検出部１６がＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常を検出すると、制御部１４は、全てのＭＯＳＦＥＴ１２Ａ〜１２Ｃがオン状態となるように制御する。
このようにすれば、複数のＭＯＳＦＥＴ１２Ａ〜１２ＣのうちのいずれのＭＯＳＦＥＴ１２Ａ〜１２Ｃに異常が発生したかを検出しなくても、異常発熱による不具合を防止することができるため、より一層、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常発熱による不具合を防止するための構成を簡素化することが可能になる。 Moreover, if the abnormality detection part 16 detects abnormality of MOSFET12A-12C, the control part 14 will control so that all MOSFET12A-12C will be in an ON state.
In this way, it is possible to prevent problems due to abnormal heat generation without detecting which of the plurality of MOSFETs 12A to 12C is abnormal, so that the MOSFETs 12A to 12C can be further improved. It is possible to simplify the configuration for preventing problems caused by abnormal heat generation.

さらに、異常検出部１６は、複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃの少なくとも１個のＭＯＳＦＥＴ１２Ａ（〜１２Ｃ）の異常によって生じる電圧の変化を検出する。
少なくとも１個のＭＯＳＦＥＴ１２Ａが異常により高い抵抗を伴ってオン状態となると、回路の電圧に変動が生じるため、この電圧の変動を検出することで、少なくとも１個のＭＯＳＦＥＴ１２Ａに異常が生じていることを検出することができる。 Further, the abnormality detection unit 16 detects a change in voltage caused by an abnormality of at least one MOSFET 12A (to 12C) of the plurality of MOSFETs 12A to 12C.
When at least one MOSFET 12A is turned on with an abnormally high resistance, the circuit voltage fluctuates. By detecting this voltage fluctuation, it is confirmed that at least one MOSFET 12A has an abnormality. Can be detected.

また、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常が生じたことを外部に報知する制御部１４（報知手段）を備える。
異常が生じていないＭＯＳＦＥＴ１２Ａ〜１２Ｃをオン状態とする場合、本来オフ状態であるため通電されていないはずの負荷Ｌへの不要な通電が行われている可能性がある。本実施形態によれば、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常を認識することが可能になるとともに、制御部１４の報知により異常を認識したユーザが適切な処置をすることで負荷Ｌへの不要な通電を抑制することが可能になるとともに、さらなる異常状態が発生する前に電力供給制御装置の交換や修理が可能になり、異常発熱の発生を防止することができる。 Moreover, the control part 14 (notification means) which alert | reports to the outside that abnormality in MOSFET12A-12C has arisen is provided.
When the MOSFETs 12 </ b> A to 12 </ b> C in which no abnormality has occurred are turned on, unnecessary energization to the load L that should not have been energized since it is originally in an off state may be performed. According to the present embodiment, it becomes possible to recognize the abnormality of the MOSFETs 12A to 12C, and the user who has recognized the abnormality by the notification of the control unit 14 suppresses unnecessary energization to the load L by taking appropriate measures. In addition, the power supply control device can be replaced or repaired before a further abnormal state occurs, thereby preventing abnormal heat generation.

＜実施形態２＞
実施形態１では、チップ１１の外部で３個のＭＯＳＦＥＴ１２Ａ〜１２Ｃのソースが接続されていたが、実施形態２では、図２に示すように、チップ２０の内部でＭＯＳＦＥＴ１２Ａ〜１２Ｃのソースが接続されるものである。実施形態１と同一の構成については、同一の符号を付して説明を省略する。 <Embodiment 2>
In the first embodiment, the sources of the three MOSFETs 12A to 12C are connected outside the chip 11, but in the second embodiment, the sources of the MOSFETs 12A to 12C are connected inside the chip 20 as shown in FIG. Is. About the same structure as Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.

ＭＯＳＦＥＴ１２Ａ〜１２Ｃと負荷Ｌとの間は、チップ２０の内部又は表面でＭＯＳＦＥＴ１２Ａ〜１２Ｃの内部又は表面の金属配線によってショートされており、ＭＯＳＦＥＴ１２Ａ〜１２Ｃのソース同士が接続された接続部２１の電位が異常検出部１６に出力される。   The MOSFET 12A to 12C and the load L are short-circuited inside or on the surface of the chip 20 by the metal wiring inside or on the surface of the MOSFET 12A to 12C, and the potential of the connection portion 21 where the sources of the MOSFETs 12A to 12C are connected to each other It is output to the abnormality detection unit 16.

＜他の実施形態＞
本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような実施形態も本発明の技術的範囲に含まれ、さらに、下記以外にも要旨を逸脱しない範囲内で種々変更して実施することができる。
（１）上記実施形態では、電力供給制御装置１０には、ＭＯＳＦＥＴが３個備えられていたが、これに限らず、ＭＯＳＦＥＴが２個又は４個以上備えられるものに本発明を適用してもよい。なお、この場合、オン状態とするＭＯＳＦＥＴの個数に応じてＭＯＳＦＥＴの電流容量を設定すればよい。 <Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention, and further, within the scope not departing from the gist of the invention other than the following. Various modifications can be made.
(1) In the above embodiment, the power supply control device 10 includes three MOSFETs. However, the present invention is not limited to this, and the present invention may be applied to a device including two or four or more MOSFETs. Good. In this case, the current capacity of the MOSFET may be set according to the number of MOSFETs to be turned on.

（２）上記実施形態では、異常検出部１６は、複数のＭＯＳＦＥＴ１２Ａ〜１２Ｃの少なくとも１つに異常が発生していることを検出する構成としたが、これに限られず、個別のＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常を検出するようにしてもよい。例えば、各ＭＯＳＦＥＴ１２Ａ〜１２Ｃに個別に対応する複数の異常検出部を設けて、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの異常を検出するようにしてもよい。このように、いずれのＭＯＳＦＥＴに異常が発生しているかを検出できれば、ＭＯＳＦＥＴの異常発生時に、異常が発生していないＭＯＳＦＥＴのみを制御部１４がオン状態に制御することも可能である。 (2) In the above embodiment, the abnormality detection unit 16 is configured to detect that an abnormality has occurred in at least one of the plurality of MOSFETs 12A to 12C. However, the present invention is not limited to this, and the individual MOSFETs 12A to 12C An abnormality may be detected. For example, a plurality of abnormality detection units corresponding individually to the MOSFETs 12A to 12C may be provided to detect abnormality of the MOSFETs 12A to 12C. In this way, if it is possible to detect which MOSFET has an abnormality, it is possible for the control unit 14 to control only the MOSFET in which no abnormality has occurred when the abnormality of the MOSFET has occurred.

（３）複数のドライブ回路１５Ａ〜１５Ｃを設けたが、ＭＯＳＦＥＴ１２Ａ〜１２Ｃの各ゲートを接続し、１つのドライブ回路を駆動させてＭＯＳＦＥＴ１２Ａ〜１２Ｃをオンオフするようにしてもよい。 (3) Although the plurality of drive circuits 15A to 15C are provided, the gates of the MOSFETs 12A to 12C may be connected to drive one drive circuit to turn on and off the MOSFETs 12A to 12C.

１０...電力供給制御装置
１１...チップ
１２Ａ〜１２Ｃ...ＭＯＳＦＥＴ（半導体パワー素子）
１３...制御回路
１４...制御部（制御部，報知手段）
１６...異常検出部
Ｂ...電源
Ｌ...負荷 10 ... Power supply control device 11 ... Chips 12A to 12C ... MOSFET (semiconductor power element)
13 ... Control circuit 14 ... Control unit (control unit, notification means)
16 ... Abnormality detector B ... Power supply L ... Load

Claims (4)

電源から負荷へ供給される電力を制御する電力供給制御装置であって、
前記電源から前記負荷に至る経路に並列に配される複数の半導体パワー素子と、
前記半導体パワー素子のオンオフを制御する制御部と、
前記半導体パワー素子の異常を検出する異常検出部と、を備え、
前記制御部は、前記複数の半導体パワー素子をオン状態とする駆動信号を出力していないことにより当該複数の半導体パワー素子の全てがオフ状態のときに前記異常検出部が前記半導体パワー素子の異常を検出すると、前記異常が生じていない前記半導体パワー素子が前記オン状態となるように制御する電力供給制御装置。 A power supply control device for controlling power supplied from a power supply to a load,
A plurality of semiconductor power elements arranged in parallel in a path from the power source to the load;
A controller for controlling on / off of the semiconductor power element;
An abnormality detection unit for detecting an abnormality of the semiconductor power element,
Since the control unit does not output a drive signal for turning on the plurality of semiconductor power elements , the abnormality detection unit detects an abnormality of the semiconductor power element when all of the plurality of semiconductor power elements are off. Upon detection of the abnormality is not occurring said semiconductor power device power supply control device for controlling so that the on state. 前記異常検出部が前記半導体パワー素子の異常を検出すると、前記制御部は、全ての前記半導体パワー素子がオン状態となるように制御する請求項１に記載の電力供給制御装置。 2. The power supply control device according to claim 1, wherein when the abnormality detection unit detects an abnormality of the semiconductor power element, the control unit performs control so that all of the semiconductor power elements are turned on. 前記異常検出部は、前記複数の半導体パワー素子の少なくとも１個の半導体パワー素子の異常によって生じる電圧の変化を検出する請求項２に記載の電力供給制御装置。 The power supply control device according to claim 2, wherein the abnormality detection unit detects a change in voltage caused by an abnormality of at least one semiconductor power element of the plurality of semiconductor power elements. 前記半導体パワー素子の異常が生じたことを外部に報知する報知手段を備える請求項１ないし請求項３のいずれか一項に記載の電力供給制御装置。 The power supply control device according to any one of claims 1 to 3, further comprising a notification unit that notifies the outside that an abnormality has occurred in the semiconductor power element.
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