JP5900272B2 - Access control circuit and access control method - Google Patents

Description

  The present invention relates to an access control circuit and an access control method.

  In recent years, many multiprocessor systems that share resources (macro and memory) among a plurality of processors have been used. In such multiprocessor systems, shared resources are accessed by multiple processors. Therefore, when a shared resource is being used by a certain processor, there is a system having an access control circuit that makes it possible to exclude access from another processor by hardware.

  In such a system, for example, when the processor accesses the shared resource via the bus, the processor acquires the access right of the shared resource by setting the processor identification number in the address signal line of the bus. Therefore, when an access right for the same shared resource is requested by another processor until the access right is released, an access request and an error response are output to the bus each time.

  Alternatively, for example, the system has access permission information on the shared resource, and controls access from each processor to the shared resource based on the access permission information. In this case, for example, the access right acquisition / release processing is performed by the processor by updating the access permission information based on a dedicated instruction from the processor.

  Such a system is described in Patent Documents 1 and 2, for example.

JP 2003-280980 A JP 2007-264679 A

  However, in such a system, access by the processor occurs one by one in order to acquire and release the access right of the shared resource. For this reason, access to the shared resource is performed in a series of flows including acquisition of the access right to the shared resource, processing for the shared resource, and release of the access right. As a result, the code amount of the program increases, which causes a deterioration in the performance of the processor and easily causes a failure due to the complication of the program.

  In addition, when an access right is acquired by a certain processor and an access request to a shared resource by another processor occurs, an access request and an error response are output to the bus each time an access request occurs. The bus usage rate will increase and the bus usage efficiency will deteriorate.

  As described above, in a system having an access control circuit for controlling access to a shared resource by a plurality of processors, performance degradation, program complexity, and bus use efficiency are problems.

  An object of the present invention is to provide an access control circuit and an access control method for improving the access control of shared resources.

  A first aspect is an access control circuit that is connected to a plurality of processors and a bus, and that controls shared resources that are accessed by the plurality of processors via the common bus. When the access target address from the first processor is a dummy address indicating a non-use area, the dummy address is converted into a shared resource address of the corresponding shared resource, and is output to the bus. Management means for releasing the access right to the shared resource by the first processor and outputting the access target address to the bus without converting the address when the access target address is not the dummy address; Have.

  According to the first aspect, access control of shared resources can be made efficient.

It is a figure which shows an example of the multiprocessor system which has an access control circuit in this embodiment. It is an example figure of a general program and the program in this embodiment. It is an example figure showing the detailed structure of the access control circuit in the present embodiment. It is a flowchart figure of the access control circuit in the present embodiment. It is a figure explaining the specific example of the address map in this example of an embodiment. It is a figure explaining the subtraction process for address conversion in the example of this embodiment. It is a figure explaining the specific example of the address map in a 2nd embodiment. It is a figure explaining the subtraction process for address conversion in the example of a 2nd embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[Configuration of multiprocessor system]
FIG. 1 is a diagram illustrating an example of a multiprocessor system 100 having an access control circuit according to the present embodiment. The multiprocessor system 100 in FIG. 1 includes, for example, a plurality of processors A10 and B20, an access control circuit 30, a processor A10, and shared resources A51 to C53 (hereinafter, shared resources 51 to 53) accessible from the processor B20. .

  In the present embodiment, the access control circuit 30 and the shared resources 51 to 53 are connected to each other via a common shared bus 40. The processors A10 and B20, which are a plurality of processors, are respectively connected to the corresponding address control unit A31a and address control unit B31b (hereinafter, address control units 31a and 31b) in the access control circuit 30 through dedicated buses. The

[Shared resources]
In this embodiment, the shared resources 51 to 53 indicate, for example, a shared memory that is commonly accessed from a plurality of processors, a circuit macro register, and the like. The shared resources 51 to 53 have a possibility of being simultaneously accessed from a plurality of processors. When the shared resources 51 to 53 are simultaneously accessed from a plurality of processors, for example, the consistency of information stored in the shared memory and information held in the register of the circuit macro is lost. This can lead to system runaway.

  Thus, in general shared resource access control, even when the processor A 10 acquires the access right to the shared resource A 51 while the processor A 10 acquires the access right to the shared resource A 51, even when the access right to the same shared resource A 51 is requested. The acquisition of the access right by the processor B20 is not permitted. Acquisition of the access right by the processor B20 is permitted after the access right to the shared resource A51 of the processor A10 is released.

[Access control circuit]
The access control circuit 30 in FIG. 1 is disposed between the plurality of processors A and B and the shared bus 40, and controls access to the shared resources 51 to 53 from each processor. The access control circuit 30 includes, for example, address control units 31a and 31b corresponding to each processor and an access monitoring unit 32.

  The address control units 31a and 31b have a function of blocking access to the shared resources 51 to 53 as necessary, a function of returning an error response to the processor A10 and the processor B20, an address conversion function when releasing the access right, and the like. Details of the processing will be described later. In addition, the access monitoring unit 32 includes a register that holds, for each shared resource 51 to 53, an ID (hereinafter, CPU-ID) of a processor that is acquiring the access right of the shared resource. The address control units 31a and 31b and the access monitoring unit 32 control access to the shared resources 51 to 53 by comparing the CPU-ID corresponding to the shared resources 51 to 53 with the ID of the access source processor. To do.

[First Embodiment]
The access control circuit 30 according to the present embodiment makes an instruction for releasing the access right to the shared resources 51 to 53 and an instruction for acquiring the access right unnecessary.

[Access control circuit: Release access right]
First, regarding the release of the access right of the shared resources 51 to 53, the access control circuit 30 in the present embodiment, when the access target address from the processors A10 and B20 is a dummy address indicating an unused area, The dummy address is converted into the shared resource address of the corresponding shared resource 51-53 and output to the bus 40, and the access right to the shared resource 51-53 by the processor is released. In addition, when the access target address is not a dummy address, the access control circuit 30 outputs the access target address to the bus 40 without converting the address.

  According to such an access control circuit 30, the processor does not need to separately instruct an access right release process for the shared resources 51 to 53 when ending the access process for the shared resources 51 to 53.

[Access control circuit: Acquisition of access right]
Then, regarding the acquisition of the access right of the shared resources 51 to 53, the access control circuit 30 according to the present embodiment is configured so that the shared resource 51 to 51 when the access target address is not a dummy address and is a shared resource address. When the access right to 53 is acquired by the processor, the access target address is output to the bus 40. In addition, when the access right to the shared resources 51 to 53 is not acquired by any processor, the access control circuit 30 causes the processor to acquire the access right and outputs the access target address to the bus 40. When acquired by the processor, the access target address is not output to the bus 40.

  According to such an access control circuit 30, the processor does not need to separately instruct the access right acquisition process for the shared resources 51 to 53 when starting the access process for the shared resources 51 to 53.

  Here, an example of a program in a system having the access control circuit 30 of the present embodiment will be described in comparison with a general program.

[Sample program for instructing access processing to shared resources]
FIG. 2 is a diagram illustrating an example of a program P2 for instructing access processing to a shared resource in a system having a program P1 for instructing access processing for a general shared resource and the access control circuit 30 according to the present embodiment. It is. The left program P1 in the figure is a specific example of a general program describing the access processing to the shared resource, and the right program P2 is a specific example of a program processed by the processor in the present embodiment. is there.

[General program example]
First, a specific example of the general program P1 will be described. In the general program P1 example, when accessing the shared resources 51 to 53, for example, when writing to the shared memory is performed, the access to the shared resource is performed before and after the command indicating the shared resource access process c2. Instructions indicating right acquisition c1 and release processing c3 are required. For this reason, even if the access process c2 to the shared resource is a trivial process that can be instructed with one instruction, the access right acquisition instruction c1 and the release instruction c3 to the shared resource are always before and after that. Necessary.

  For example, a processing flow when the processor A10 accesses the shared resource A51 when the access right of the shared resource A51 is acquired by the processor B20 will be described. In such a case, after the processor B20 performs the access right release processing of the shared resource A51, the processor A10 acquires the same access right and performs the access processing to the shared resource A51. When the access process by the processor A10 ends, an access right release process is performed, and an access right acquisition process is performed again by the processor B20 as necessary.

  As described above, a large number of instructions for controlling the access right to the shared resource are processed before and after the access processing to the shared resource. As a result, the amount of instructions processed by each processor increases and the performance of the processor decreases. Further, the description of the program P1 becomes complicated, and a failure is induced. Here, an example of a failure that easily occurs will be described.

  For example, in the program P1, when the description c1 of the access right acquisition command is leaked, the shared resource is illegally accessed. As a result, the consistency of shared resources is not guaranteed. This indicates a case where access to the same shared resource by another processor (for example, processor A10) is permitted while the shared resource is being accessed by the processor (for example, processor B20) that is acquiring the access right. Thereby, for example, a situation occurs in which the shared memory is simultaneously updated by a plurality of processors, and the consistency of the shared memory is lost.

  Also, for example, when the description of the access right release instruction is leaked, the access right of the shared resource remains illegally acquired by a certain processor, and acquisition of the access right by another processor fails. As a result, the shared resource cannot be accessed by another processor, and the program processing is not appropriately performed.

[Program example in this embodiment]
On the other hand, in the program P2 in the present embodiment, instructions for acquiring and releasing the access right of the shared resource are not required before and after the instruction c4 indicating the access process to the shared resource. However, in the final access instruction to the shared resource, a dummy address corresponding to the address of the shared resource to be accessed is designated as the access target address. In the program P2, the processor performance is improved by not increasing the amount of instructions processed by the processor. Further, since the description of the program P2 is simple, the above-described failure is avoided.

  Next, the configuration of the access control circuit 30 in the present embodiment will be specifically described.

[Detailed Configuration of Access Control Circuit 30]
FIG. 3 is an example diagram showing a detailed configuration of the access control circuit 30 in the present embodiment. The access control circuit 30 in the present embodiment includes address control units A31a and 31b corresponding to the processors A10 and B20, and an access monitoring unit 32. In FIG. 1, the processor B20 and the address control unit B31b corresponding to the processor B20 are omitted from FIG. 1, but the configuration of the address control unit B31b is the same as that of the address control unit A31a.

  The address control unit A31a in FIG. 3 includes, for example, an access mask / address conversion unit 311, an address decoder 312, and an error response unit 310. The address decoder 312 determines whether access to the shared resource has occurred based on the value s2 to the dedicated address bus and the control value s3 to the dedicated control bus by the corresponding processor A10. If it is determined that access to the shared resource has occurred, the address decoder 312 outputs the processor ID to the access monitoring unit 32 (s4).

  When detecting access to the shared resource, the access mask / address conversion unit 311 compares the CPU-ID (s5) corresponding to the shared resource input from the access monitoring unit 32 with the ID of the connected processor. If they match, and if the CPU-ID is not registered, access instructions s2 and s3 to the shared resource are output to the shared bus 40. On the other hand, if they do not match, the access mask / address conversion unit 311 blocks an access instruction to the shared resource and does not output it to the shared bus 40, but outputs an error notification trigger to the error response unit 310. As a result, the error response unit 310 outputs an error response s1 for access to the corresponding processor.

  When the access mask / address conversion unit 311 detects access to the dummy address, the access mask / address conversion unit 311 determines that the access is the final access corresponding to the shared resource. In this case, the access mask / address conversion unit 311 outputs the actual shared resource address s2 ′ obtained by converting the dummy address to the shared address bus and the control value s3 to the shared control bus, and sends the CPU-ID to the access monitoring unit 32. A clear instruction s6 is output.

  Further, the access monitoring unit 32 of FIG. 3 includes a register unit 321 that holds, for each shared resource, the ID of the processor that is acquiring the access right of the shared resource in a register as a CPU-ID. When access to the shared resource occurs, the access control circuit 30 outputs the access source processor ID (s4) to the access monitoring unit 32.

  The access monitoring unit 32 compares the CPU-ID corresponding to the shared resource of the register unit 321 with the input processor ID (s4), and if different, updates the CPU-ID corresponding to the shared resource. Absent. This indicates a case where the access right of the shared resource has already been acquired by another processor. On the other hand, if the CPU-ID and the input processor ID match, it indicates that the access right has been acquired by the access source processor. For this reason, the access monitoring unit 32 does not update the CPU-ID of the register unit 321. Alternatively, when the CPU-ID is not registered, the access monitoring unit 32 registers the input processor ID as a new CPU-ID to indicate that no access right has been acquired by any processor.

  Next, the flow of processing of the access control circuit 30 will be described based on the flowchart diagram.

[Access to shared resources]
FIG. 4 is a flowchart for explaining the flow of access processing to the shared resource of the access control circuit 30 in the present embodiment. With reference to the flowchart in the figure, for example, the access processing to the shared resource A51 by the processor A10 will be described. However, the same applies to the access processing to another shared resource by the processor B20.

  First, when accesses s2 and s3 from the processor A10 to the shared resource A51 occur (S11), the address control unit A31a is based on the CPU-ID (s5) corresponding to the shared resource A51 input from the access monitoring unit 32. Then, it is determined whether or not the shared resource A51 is accessible (S12).

  When the CPU-ID does not indicate any processor, it indicates that the access right of the shared resource A51 has not been acquired by any processor and is accessible (YES in S12). Therefore, the address control unit A31a outputs the access instructions s2 and s3 of the processor A10 to the shared bus 40, and the access monitoring unit 32 updates the CPU-ID corresponding to the shared resource A51 to the ID of the processor A10 (S13). ). Thereby, it is registered that the shared resource A51 is being used by the processor A10. That is, the access right of the shared resource A51 is acquired by the processor A10.

  Further, when the CPU-ID is the same as the ID of the processor A10, it indicates that the access right of the shared resource A51 has already been acquired by the processor A10 and is accessible to the shared resource A51 (YES in S12). . Therefore, the address control unit A31a outputs the access instructions s2 and s3 of the processor A10 to the shared bus 40. At this time, the access monitoring unit 32 maintains the CPU-ID corresponding to the shared resource A51 as the ID of the processor A10 (S13). Then, an instruction to access the shared resource A51 from the processor A10 is output to the shared bus 40 (S15).

  On the other hand, when the CPU-ID is an ID of another processor (for example, processor B20), it indicates that the access right of the shared resource A51 is being accessed by another processor (processor B20) (NO in S12). In this case, the address control unit A31a does not notify the shared bus 40 of the access instruction from the processor A10 (S14), and blocks the access instruction. In addition, the address control unit A31a outputs an error response s1 to the processor A10 to notify that the access right of the shared resource A51 is acquired by another processor (S14).

  In the case of the final access to the shared resource A51 (YES in S16), the program describes in advance an access process for a dummy address corresponding to the address to be accessed to be recognized (S17). That is, a dummy address corresponding to the last access target address is described in advance in the program. Thus, only at the time of final access, a dummy address corresponding to the shared resource A51 address to be accessed is described in the program as an access target address.

  When the address control unit A31a detects a dummy address, the address control unit A31a recognizes that it is the final access to the shared resource A51 corresponding to the dummy address. Therefore, the address control unit A31a converts the dummy address into the address of the corresponding shared resource A51 and outputs it to the shared bus 40 (S18). That is, the address control unit A31a converts the dummy address into a real address and outputs it to the shared bus 40 (s2 ′, s3). In addition, the address control unit A31a outputs a clear trigger s6 of the CPU-ID (ID of the processor A10) corresponding to the shared resource A51 to the access monitoring unit 32, and the access monitoring unit 32 outputs the CPU-ID corresponding to the shared resource A51. The ID is cleared (S18). As a result, the access right of the shared resource A51 is released, and the shared resource A51 becomes a non-use state. In this way, the access right to the shared resource A51 of the processor A10 can be released in accordance with the final access without separately requiring an instruction for releasing the access right.

  Next, details of the address conversion process will be described.

[Address conversion processing]
In the present embodiment, the dummy address corresponding to the shared resource is recognized in advance by the address control unit A31a of the access control circuit 30. For this reason, when an access to the dummy address occurs, the address control unit A31a can recognize that it is the final access to the shared resource and convert the address. In the address conversion process according to the present embodiment, a predetermined value is subtracted from the dummy address, whereby the address of the shared resource corresponding to the dummy address is acquired.

  Here, the address of the shared resource and the dummy address in the memory map will be described with reference to the drawings.

[Specific example of address map]
FIG. 5 is a diagram for explaining a specific example of the address map AM1 in the present embodiment. The dummy address is secured in an arbitrary area on the address map AM1 corresponding to the address of each shared resource. The dummy address is an unused address on the memory map AM1. The dummy address does not have to correspond to the physical address. The size of the area range of the dummy address is the same as the area range of the address of the corresponding shared resource.

  The address map AM1 in FIG. 5 is, for example, the address map AM1 of the processor A10. For example, since the processor A10 is a 32-bit processor, it has a 4 GB address space. In the address map AM1 in the figure, a dummy address area da corresponding to the address area ra of the shared resource A51 and a dummy address area db corresponding to the address area rb of the shared resource B52 are represented. The address area and dummy address area of the shared resource C53 are omitted.

  In the example of the address map AM1 in FIG. 5, the address area ra of the shared resource A51 is a 4 KB area of 0x0000 — 1000 to 0x0000 — 2000. The dummy address area da corresponding to the address area ra of the shared resource A51 is a 4 KB area of 0x2000 — 2000 to 0x2000 — 3000. In this way, an address having the same size as the address area ra of the shared resource is set as the dummy address area da. Similarly, a 4 KB dummy address area db of 0xA000 — 3000 to 0xA000 — 4000 is set corresponding to the 4 KB address area rb of 0x7000 — 1000 to 0x7000 — 2000 of the shared resource B52.

  As described above, in the present embodiment, the program is described so as to access the dummy address corresponding to the shared resource address only at the time of final access. For example, when the access is to the address 0x0000_1000 of the shared resource A51 and is the final access, an instruction to access the address 0x2000_2000 is described in the program. Similarly, when the access is to the address 0x7000_1500 of the shared resource B52 and is the final access, an access instruction to the address 0xA000_3500 is described in the program.

  In this way, a dummy address for final access is set in advance on the address map AM1 corresponding to the address of each shared resource. Since the address control unit A31a recognizes in advance the dummy address and the address of the corresponding shared resource, the address of the corresponding shared resource can be easily acquired based on the dummy address. In the present embodiment, the address areas ra and rb of the shared resource corresponding to the dummy address areas da and db are the same size, and therefore the address of the corresponding shared resource is obtained by subtracting a predetermined value from the dummy address. Can be acquired. Next, the specification of the address conversion process in the present embodiment will be described based on the address map AM1 in FIG.

[Address conversion specifications]
FIG. 6 is a diagram for explaining the specification of subtraction processing for address conversion in the present embodiment. In the table H1 in FIG. 6, for the shared resource A51 and the shared resource B52, the shared resource address areas ra and rb, the corresponding dummy address areas da and db, and the arithmetic expression of the subtraction process for performing the address conversion process are represented. ing.

  In the address conversion specification table H1 of FIG. 6, the subtraction formula for the shared resource A51 is “dummy address−0x2000 — 1000”. For example, in the example illustrated in FIG. 5 where the address 0x2000_2000 is accessed as the final access, the corresponding real address 0x0000_1000 is calculated by the arithmetic processing of “0x2000_2000-0x2000_1000”. Similarly, the subtraction formula of the shared resource B52 is “dummy address−0x3000_2000”. For example, in the example in which the address 0xA000_3500 is accessed as the final access illustrated in FIG. 5, the corresponding real address 0x7000_1500 is calculated by the arithmetic processing of “0xA000_3500-0x3000_2000”.

  As described above, since the dummy address and the corresponding shared resource address are recognized in advance, the corresponding shared resource address is easily calculated by a predetermined arithmetic expression. In addition, since the dummy address area and the corresponding shared resource address area have the same size, the real address can be obtained by a simple calculation using a predetermined value of the dummy address.

  In this embodiment, the dummy address area is set to an area having a larger address value on the memory map AM1 (FIG. 5) than the address area of the shared resource. For this reason, the address conversion process is performed by subtracting a predetermined value from the dummy address. However, the dummy address area may be set to any address on the address map AM1. For example, when the dummy address area is set to an area having a smaller address value on the memory map than the shared resource address area, the address conversion process is performed by adding a predetermined value to the dummy address.

  Further, the address conversion process is not limited to the subtraction operation and the addition operation. As long as the address of the shared resource that uniquely corresponds to the dummy address can be acquired, it may be converted by any arithmetic expression. Further, the address conversion process may be performed by referring to a conversion table in which a shared resource corresponding to a dummy address is associated, for example, instead of an arithmetic process.

  As described above, the access control circuit 30 according to the present embodiment, when the access target address from the first processor among the plurality of processors is a dummy address indicating an unused area, The address is converted to the shared resource address of the corresponding shared resource and output to the bus, and the access right to the shared resource by the first processor is released. Further, when the access target address is not a dummy address, the access control circuit 30 outputs the access target address to the bus without converting the address.

  Therefore, the processor does not need to separately instruct the shared resource access right release process when the shared resource access process ends. As a result, the processing efficiency of the processor is improved, and the code amount of instructions processed by the processor is reduced. Further, by simplifying the instruction for instructing the access processing to the shared resource, it is possible to avoid the failure of the program due to the omission of the description of the access right release instruction. As a result, the verification cost, manufacturing, porting cost and the like related to the program are reduced.

  In the access control circuit 30 according to the present embodiment, the dummy address range is the same size as the shared resource address range, and the address conversion of the management means adds or subtracts a predetermined value to the dummy address. To convert to a shared resource address. As a result, the real address can be obtained by a simple addition or subtraction operation using a predetermined value of the dummy address.

  Further, the management means of the access control circuit 30 in the present embodiment further provides an access target when the access right to the shared resource is acquired by the first processor when the access target address is not a dummy address. Output address to bus. In addition, when the access right to the shared resource is not acquired by any of the plurality of processors, the management unit causes the first processor to acquire the access right and outputs the access target address to the bus. When it is acquired by a processor different from the one processor, the access target address is not output to the bus.

  Therefore, the processor does not need to separately instruct the process for acquiring the access right for the shared resource when starting the access process for the shared resource. As a result, the processing efficiency of the processor is improved, and the code amount of instructions processed by the processor is reduced. Further, by simplifying the instruction for instructing the access processing to the shared resource, it is possible to avoid a failure of the program due to omission of description of the access right acquisition instruction. As a result, the verification cost, manufacturing, porting cost and the like related to the program are reduced.

  In implementing the access control circuit 30 in the present embodiment, it is not necessary to change each processor, shared resource, and bus in the existing multiprocessor system. Further, there is no need for a dedicated command for instructing acquisition and release processing of the shared resource access right. Thereby, the access control circuit 30 in the present embodiment can be easily mounted on an existing multiprocessor system.

  Furthermore, the access control circuit 30 in the present embodiment is installed between a plurality of processors and a common bus. As a result, the access related to the access right acquisition / release processing of the shared resource and the error response corresponding to the access right acquisition instruction are not output to the bus. Thereby, for example, when the access right is acquired by another processor, it is avoided that an access right acquisition instruction and an error response are output to the bus each time the access right is requested. Therefore, the bus usage rate is suppressed and the bus usage efficiency is improved.

  Specifically, when the access right to the shared resource A51 is acquired by the processor A10 and the access to the shared resource A51 occurs by the processor B20, every time the access processing from the processor B20 is instructed, It is avoided that instructions and corresponding error responses continue to be output on the bus. This avoids unnecessary data being output to the shared bus and suppresses the bus usage rate.

  In the multiprocessor system 100 in which a shared resource is accessed from a processor via a plurality of shared buses, the performance of each shared bus may be different. In such a case, the data transfer speed corresponds to the speed of the bus with the lowest performance. For example, unlike the present embodiment, when the instruction to acquire the access right of the shared resource is performed via the shared bus, the instruction to acquire the access right of the processor is acquired via the shared bus. It is blocked until the result is notified. For this reason, if there is a low-performance bus among a plurality of shared buses, the block time of the processor becomes long, which causes performance degradation.

  For this reason, it is desirable that only the minimum necessary instructions are output to the shared bus 40. In this embodiment, the access control circuit 30 is installed between a plurality of processors and a common bus, so that the access control to the shared resource by the processor is performed before the output to the shared bus 40. Controlled by the circuit 30. As a result, the output to the shared bus 40 is kept to the minimum necessary, and deterioration of the performance of the entire system is avoided.

[Second Embodiment]
In the first embodiment, the case where the dummy address area corresponding to the address area of the shared resource is set to a different area for each shared resource on the address map is illustrated. On the other hand, in the second embodiment, a case where dummy address areas corresponding to each shared resource are set in an overlapping manner is illustrated. That is, the dummy address areas overlap between a plurality of shared resources. Thereby, the range of the dummy address area can be suppressed to the minimum size, and the address map is effectively used.

[Specific example of address map]
FIG. 7 is a diagram illustrating a specific example of the address map AM2 in the second embodiment. The address map in the figure is an address map of the processor A10, for example, and shows address areas rd to rf of the shared resources D to F and corresponding dummy address areas dd to df, respectively. However, the dummy address areas dd to df are not set in separate areas for each shared resource.

  In the example of the address map AM2 in FIG. 7, the address area rd of the shared resource D is a 1 MB area of 0x0000 — 1000 to 0x0010 — 1000. Therefore, a 1-MB dummy address area dd is set. In the address map shown in the figure, an area of 0xF000 — 0000 to 0xF010 — 0000 is set as a dummy address area dd of the shared resource D.

  Since the address area re of the shared resource E is a 4 KB area of 0x7000 — 0000 to 0x7000 — 1000, a 4 KB dummy address area “de” is set. In the second embodiment, among the dummy address areas dd of the shared resource D, 4 KB address areas 0xF000_0000 to 0xF002_0000 are set as the dummy address area de of the shared resource E. Similarly, as the dummy address area df of the shared resource F, the 128 KB address area 0xF000 — 0000 to 0xF000 — 1000 of the dummy address area dd of the shared resource D is set.

  Thus, in the second embodiment, the dummy address areas corresponding to the shared resources overlap. That is, a shared dummy address area dx is set, and among the shared dummy address areas dx, an area corresponding to the size of the address area of the shared resource is set as a dummy address area. For this reason, the size of the shared dummy address area dx is set to the same size as the size of the address area of the largest shared resource.

  In the example of FIG. 7, the dummy address area de of the shared resource E and the dummy address area df of the shared resource F are overlapped, but the present invention is not limited to this example. For example, the dummy address area df of the shared resource F may be set so as not to overlap with the dummy address area de of the shared resource E in the shared dummy address area dx.

[Address conversion specifications]
FIG. 8 is a diagram for explaining subtraction processing for address conversion in the second embodiment. In the drawing, for shared resources D to F, an address area, a corresponding dummy address area, and an arithmetic expression for subtraction processing for performing address conversion processing are shown.

  In the address conversion specification table H2 of FIG. 8, the subtraction formula for the shared resource E is “dummy address−0x8000 — 0000”. For example, when the processor A10 accesses the address 0xF000_1000 as the final access to the shared resource E, the corresponding real address 0x7000_1000 is calculated by the arithmetic processing of “0xF000_1000-0x8000_0000”. Similarly, when the address 0xF000_1500 is accessed as the final access to the shared resource F, the corresponding real address 0xA000_1500 is calculated by the arithmetic processing of “0xF000_1500-0x5000_0000”.

  As described above, even when the dummy address areas are set in an overlapping manner, the address of the corresponding shared resource is simplified by subtracting the predetermined value from the dummy address in the same manner as in the first embodiment. Is calculated. Although the dummy address area of each shared resource overlaps, the dummy address area and the corresponding shared resource address area are the same size, so the real address can be obtained by a simple calculation using a predetermined value of the dummy address. It becomes possible.

  In this way, when there are a plurality of shared resources, the size of the dummy address area on the memory map can be minimized by sharing the dummy address area corresponding to each shared resource. For example, in the case of a multiprocessor system having 10 4 KB shared resources, the first embodiment requires a total dummy address area size of 40 KB, whereas the second embodiment has 10 It is sufficient to secure a 4 KB dummy address area by sharing the dummy address areas. Therefore, this is effective for a system with a small number of unused address areas on the memory map.

  As described above, according to the access control circuit in the second embodiment, when the shared resource includes the first shared resource and the second shared resource, which are a plurality of shared resources, the first shared resource The range of the first dummy address corresponding to the shared resource address and the range of the second dummy address corresponding to the shared resource address of the second shared resource overlap. Thereby, the range of the dummy address area can be suppressed to the minimum size, and the address map is effectively used. Also, in the second embodiment, as in the first embodiment, the processing efficiency of the processor is improved, the amount of code of instructions processed by the processor is reduced, and the trouble of the program is reduced. Avoided. In addition, the bus use efficiency is improved, and the bus can be easily mounted on an existing multiprocessor system.

  The above embodiment is summarized as follows.

(Appendix 1)
An access control circuit that is connected to a plurality of processors and a bus and controls shared resources accessed by the plurality of processors via the common bus,
When the access target address from the first processor among the plurality of processors is a dummy address indicating an unused area, the dummy address is converted into a shared resource address of the corresponding shared resource, and the address is converted. Output to the bus, release the access right to the shared resource by the first processor, and when the access target address is not the dummy address, the access target address is not converted to the bus An access control circuit comprising management means for outputting.

(Appendix 2)
In Appendix 1,
The range of the dummy address is the same size as the range of the shared resource address,
The access control circuit according to claim 1, wherein the address conversion of the management means converts the address into the shared resource address by adding or subtracting a predetermined value to the dummy address.

(Appendix 3)
In any one of appendices 1 to 2,
The management means further includes:
When the access target address is not the dummy address and the access right to the shared resource is acquired by the first processor, the access target address is output to the bus, and the access right is the plurality of access rights. When the access right is not acquired by any of the processors, the first processor is caused to acquire the access right and the access target address is output to the bus, and the access right is acquired by a processor different from the first processor. And the access control circuit does not output the access target address to the bus.

(Appendix 4)
In any one of appendices 1 to 3,
An access control circuit installed between the plurality of processors and the common bus.

(Appendix 5)
In Appendix 1,
The shared resource includes a first shared resource and a second shared resource,
The first dummy address range corresponding to the shared resource address of the first shared resource overlaps with the second dummy address range corresponding to the shared resource address of the second shared resource. A featured access control circuit.

(Appendix 6)
An access control method for controlling shared resources connected to a plurality of processors and a bus and accessed by the plurality of processors via the common bus,
When the access target address from the first processor among the plurality of processors is a dummy address indicating an unused area, the dummy address is converted into a shared resource address of the corresponding shared resource, and the address is converted. Output to the bus, release the access right to the shared resource by the first processor, and when the access target address is not the dummy address, the access target address is not converted to the bus An access control method comprising: an output management step.

100: Multiprocessor system, 10: Processor A, 20: Processor B, 30: Access control circuit, 40: Shared bus, 51: Shared resource A, 52: Shared resource B, 53: Shared resource C

Claims (5)

An access control circuit that is connected to a plurality of processors and a bus and controls shared resources accessed by the plurality of processors via the common bus,
When the access target address from the first processor among the plurality of processors is a dummy address indicating an unused area, the dummy address is converted into a shared resource address of the corresponding shared resource, and the address is converted. Output to the bus, release the access right to the shared resource by the first processor, and when the access target address is not the dummy address, the access target address is not converted to the bus An access control circuit comprising management means for outputting. In claim 1,
The range of the dummy address is the same size as the range of the shared resource address,
The access control circuit according to claim 1, wherein the address conversion of the management means converts the address into the shared resource address by adding or subtracting a predetermined value to the dummy address. In any one of Claims 1 thru | or 2,
The management means further includes:
When the access target address is not the dummy address and the access right to the shared resource is acquired by the first processor, the access target address is output to the bus, and the access right is the plurality of access rights. When the access right is not acquired by any of the processors, the first processor is caused to acquire the access right and the access target address is output to the bus, and the access right is acquired by a processor different from the first processor. And the access control circuit does not output the access target address to the bus. In any one of Claims 1 thru | or 3,
An access control circuit installed between the plurality of processors and the common bus. An access control method for controlling shared resources connected to a plurality of processors and a bus and accessed by the plurality of processors via the common bus,
When the access target address from the first processor among the plurality of processors is a dummy address indicating an unused area, the dummy address is converted into a shared resource address of the corresponding shared resource, and the address is converted. Output to the bus, release the access right to the shared resource by the first processor, and when the access target address is not the dummy address, the access target address is not converted to the bus An access control method comprising: an output management step.

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