JP5894870B2 - Solar power system - Google Patents

Description

  The present invention relates to a solar power generation system that obtains desired power by converting power generated by a solar panel using a power converter, and in particular, by controlling a converter connected to the solar panel, The present invention relates to a photovoltaic power generation system that detects a maximum point of power of an optical panel and operates a power converter (power conditioner, PCS) at the detected maximum power point.

  A solar power generation system is a system that converts electric power generated by a solar panel into commercial alternating current by a power conditioner and consumes it at home or reversely flows to a commercial system.

  In FIG. 4, the solid line is a graph showing the characteristics of the output voltage Vpv and output current Ipv of the solar panel (hereinafter referred to as “voltage-current characteristics”), and the broken line is the characteristic of the output voltage Vpv and output power Ppv of the solar panel ( It is a graph showing “voltage-power characteristics” below.

  As shown here, the voltage-current characteristic is a non-linear characteristic in which the output current Ipv becomes the short-circuit current Isc when the output voltage Vpv is 0, and the output current Ipv becomes 0 when the output voltage Vpv is the open circuit voltage Voc. is there. The voltage-power characteristic has a characteristic that the output power Ppv becomes the maximum power point Pmax when the output voltage Vpv is Vpmax, and the output current Ipv at the maximum power point Pmax is Ipmax.

  Since the voltage-current characteristics and voltage-power characteristics described here vary depending on the sunshine conditions and temperature conditions, in order to efficiently extract power from the solar panel, the maximum power point Pmax is always searched and the solar panel It is necessary to control the power converter connected to the power source so that the operation point of the solar panel becomes the maximum power point.

  As a method well known as the maximum power tracking control method, there is a hill climbing method. This hill-climbing method minutely changes the input voltage command value of the power converter, and determines whether the generated power of the solar panel increases or decreases according to this change. Then, based on this determination result, the change direction of whether the next voltage command value is to be slightly increased or decreased is determined to repeat the minute change of the command value.

Alternatively, there is a scanning method disclosed in Patent Document 1. This method has a power conversion circuit configured such that an inductor and a switching element are connected in series to two terminals of a solar panel, and when the maximum power point is detected, the switching element is in a first logic state, so-called open state. The process of making the solar panel output terminals open and the switching element operating from this open state to the second logic state, the so-called closed state, to make the solar panel output terminals short-circuited The voltage and current are detected at, and the point at which the power that is the product of these is maximized is detected. At the time of maximum power detection, first, the current command value Iref0 of the input current of the power conversion circuit is set to 0, and the voltage of the solar panel is once set to the open voltage Voc. Next, the command value Vref0 of the input voltage of the power conversion circuit is changed to Vref0 = Voc− (Voc / to) · t (Expression 1)
Change to the value represented by. Vref0 linearly drops from Voc to 0 during time to according to the equation. It is shown that the power conversion circuit performs feedback control using PI control so that the solar panel voltage, which is the input voltage of the power conversion circuit, becomes Vref0, and drives the switching element.

  Since this method can detect the current-voltage characteristic over the entire area of the solar panel, even when a double peak characteristic occurs due to a partial shadow, the maximum power point can be reliably detected and moved.

WO2012 / 025593A1

  The hill-climbing method described above may have a slow response when sunshine changes suddenly. In addition, there is a fear that it is not possible to cope with the double mountain characteristics that occur when a partial shadow occurs in the solar panel.

  Moreover, the scanning method shown by patent document 1 is changing the input voltage command value which is the voltage of a solar panel by the feedback control by PI control at the time of a maximum power point detection. The solar panel has a characteristic that the voltage change (dV / di) with respect to the current change is large in the vicinity of the short circuit current point. Therefore, if the choke coil value is reduced to reduce the volume and cost, the short circuit current point In the vicinity, the voltage of the solar panel greatly fluctuates due to the choke coil ripple current, and the input voltage control system may oscillate and the accurate maximum power point may not be detected.

  In the scanning method, when Iref0 is set to 0 when maximum power is detected, the solar panel shifts to the open circuit voltage Voc point, and the output power from the power conversion circuit becomes zero. Next, as Vref0 is changed, the output power decreases again from zero through the maximum power, and when Vref0 becomes zero, the current reaches the short-circuit current Isc and the output power becomes zero. In this way, when viewed from the grid-connected inverter side, the output power greatly changes when maximum power is detected, which may adversely affect the system such as voltage fluctuations in the system.

  An object of the present invention is to improve the responsiveness of the maximum power point tracking method in a photovoltaic power generation system. In addition, even when a partial shadow is generated on the solar panel, the maximum power point is accurately obtained. Also, the capacity and cost of the choke coil and the input filter capacitor of the power conversion circuit are made as small as possible. In addition, it is intended to stabilize the system by suppressing rapid output fluctuation of the grid interconnection inverter.

In order to solve the above-described problem, in the photovoltaic power generation system according to claim 1, a solar panel, a power detection unit that detects output power of the solar panel, and an on / off operation of a switching element, a power conversion means for outputting the voltage of the power obtained by converting the output voltage, the output of the power detection means is input, and a control means for controlling the switching element, the control means, wherein an open loop While controlling the switching element, the duty ratio for driving the switching element is changed between 0% and a predetermined upper limit value, and the maximum power point of the solar panel is detected in the process.

  ADVANTAGE OF THE INVENTION According to this invention, the responsiveness of the maximum electric power point tracking system in a solar power generation system can be improved. Further, even when a partial shadow is generated on the solar panel, the maximum power point can be accurately obtained. In addition, the capacity and cost of the choke coil and input filter capacitor of the power conversion circuit can be reduced as much as possible. Further, it is possible to stabilize the system by suppressing a rapid output fluctuation of the grid interconnection inverter.

1 is a diagram illustrating a circuit configuration of Embodiment 1. FIG. FIG. 3 is a diagram illustrating a circuit configuration of an input filter according to the first embodiment. FIG. 6 is a waveform of each part showing the operation of the first embodiment. The figure which shows the characteristic of a solar panel. The figure which shows the relationship between the PN voltage of a power conditioner, and Duty maximum value Dmax. 5 shows waveforms at various parts in the detection mode according to the first embodiment. 6 shows waveforms at various parts in the detection mode of Example 2. 6 shows waveforms at various parts in the third embodiment.

  The Example of the solar energy power generation system of this invention is described using FIGS. 1-8.

  The solar power generation system of Example 1 is demonstrated using FIGS. 1-6.

  FIG. 1 is a diagram illustrating a circuit configuration of the photovoltaic power generation system according to the present embodiment. In FIG. 1, 1 is a solar panel, 2 is a power conditioner, 3 is a commercial system, and an input filter 4, a DC-DC converter 7, a grid interconnection inverter 12, and a control circuit are provided inside the power conditioner 2. There are 14. In the DC-DC converter 7, 8 is a choke coil having an inductance value of about 200 to 800 μH, 9 is a power MOSFET, 10 is a boost diode, 11 is a capacitor, 13 is a current sensor, 15a and 15b are voltage dividing resistors, and 24 is a driver. It is. In the control circuit 14, 16 is a time ratio generator, 17 is a mode switch, 18a and 18b are subtractors, 19a and 19b are PI control blocks, 20 is a multiplier, 21a and 21b are AD converters, and 22 is A PWM circuit, 23 is a maximum value determination circuit, and 25 is an input voltage command value (Vref).

  As shown in FIG. 1, both ends of the solar panel 1 are connected to the input side terminals of the input filter 4 inside the power conditioner 2, and the output side terminal of the input filter 4 is the input of the DC-DC converter 7. The output side terminal of the DC-DC converter 7 is connected to the input side terminal of the grid interconnection inverter 12. The output side terminal of the grid interconnection inverter 12 is connected to the commercial system 3 outside the power conditioner 2.

  Here, the inside of the DC-DC converter 7 will be described in detail. The input side terminal of the choke coil 8 is connected to the positive output side terminal of the input filter 4, and the output side terminal of the choke coil 8 is connected to the drain of the power MOSFET 9. Further, the negative output side terminal of the input filter 4 and the source of the power MOSFET 9 are connected. Further, in the DC-DC converter 7, a series body of voltage dividing resistors 15 a and 15 b is connected to both ends of the output side terminal of the input filter 4. The anode of the boost diode 10 is connected to the drain of the power MOSFET 9. A capacitor 11 is connected between the cathode of the boost diode 10 and the source of the power MOSFET 9. Both ends of the capacitor 11 are connected to the grid interconnection inverter 12 outside the DC-DC converter 7.

  Next, the inside of the control circuit 14 will be described in detail. The AD converter 21 a is connected to the midpoint of the voltage dividing resistors 15 a and 15 b inside the DC-DC converter 7, and the AD converter 21 b is connected to the current sensor 13 inside the DC-DC converter 7. The output of the AD converter 21a is Vin and the output of the AD converter 21b is a digital quantity named IL. IL and Vin are input to the multiplier 20, and the output is input to the maximum value determination circuit 23 as Ppv. Vin is also input to the maximum value determination circuit 23 and the positive terminal of the subtractor 18a. The output of the maximum value determination circuit 23 becomes the input voltage command value 25 (Vref) and is input to the minus side terminal of the subtractor 18a. The output of the subtracter 18a is input to the PI control block 19a. The output of the PI control block 19a is input to the plus side terminal of the subtractor 18b. IL is input to the minus terminal of the subtractor 18b. The output of the subtracter 18b is input to the PI control block 19b. The output of the PI control block 19b is connected to the steady mode side of the mode switch 17. A duty ratio generator 16 is connected to the detection mode side of the mode switch 17. The output of the mode switch 17 is input to the PWM circuit 22. Here, the output of the mode switch 17 is a duty ratio when the power MOSFET 9 is switched, and is described as “Duty” below. The output of the PWM circuit 22 is input to a driver 24 inside the DC-DC converter 7. The output of the driver 24 is connected to the gate of the power MOSFET 9.

  FIG. 2 is a diagram showing an example of the inside of the input filter 4 of FIG. In FIG. 2, 5a and 5b are common mode chokes, and 6a, 6b, 6c, 6d, 6e and 6f are filter capacitors. Among the filter capacitors, the capacities of 6a and 6e are about 5 to 10 μF, and 8 μF filter capacitors 6 a and 6 e and 10000 pF filter capacitors 6 b, 6 c, 6 d, and 6 f are exemplified. In FIG. 2, a filter capacitor 6a is connected to both ends of the input side terminal of the input filter 4, and an input side terminal of the common mode choke 5a is connected to both ends of the filter capacitor 6a. The output side terminal of the common mode choke 5a is connected to a series body of filter capacitors 6b and 6c. The midpoint of the filter capacitors 6b and 6c is connected to the frame ground. Both ends of the filter capacitor 6d are connected to both ends of the series body of the filter capacitors 6b and 6c. Both ends of the filter capacitor 6d are connected to the input side terminals of the common mode choke 5b. A filter capacitor 6e is connected between the output side terminals of the common mode choke 5b. Then, both terminals of the filter capacitor 6 e become the converter side terminals and are drawn out of the input filter 4. Here, 8 μF of the filter capacitors 6a and 6e is a capacitor mainly used for removing a switching ripple of 20 to 40 kHz which is a switching frequency, and a film capacitor having a relatively large capacity and excellent frequency characteristics is used. desirable. On the other hand, the filter capacitors 6b, 6c, 6d, and 6f are used to remove noise components of 100 kHz or more that are generated in association with switching, and it is desirable to use ceramic capacitors that are more excellent in high frequency characteristics than film capacitors.

  Next, the circuit operation of the first embodiment will be described with reference to FIG. FIG. 3 is a diagram showing operation waveforms of each part of the circuit of FIG. 1 with the horizontal axis as time, and FIG. 3A shows whether the DC-DC converter 7 is in a steady mode or a detection mode. “DC-DC converter 7 operating state”, FIG. 3B shows a waveform indicating the duty ratio Duty of the duty ratio generator 16 as “Duty”, and FIG. 3C shows the current waveform of the solar panel 1. “Ipv”, FIG. 3D shows the voltage waveform at both ends of the solar panel 1, and FIG. 3E shows the waveform of the power output from the DC-DC converter 7 to the grid interconnection inverter 12. This is “DC-DC converter 7 output power”. Here, the detection mode is a mode for detecting the maximum power point of the solar panel 1, and the steady mode is for operating the power conditioner 2 so that the current at the maximum power point obtained in the detection mode is obtained. It is a mode to make it.

  Next, FIG. 4 is a graph showing the current-voltage characteristics and the current-power characteristics of the solar panel 1 as described above, and shows the range (Vpvmin to Voc) of the voltage Vpv used in the detection mode. It is.

  Next, FIG. 5 is a graph showing the relationship between the maximum value Dmax of the duty ratio Duty output from the duty ratio generator 16 and the PN voltage (Vpn) which is the voltage of the capacitor 11 (Cpn). The parameter is the minimum value Vpvmin of the solar panel voltage Vpv in the detection mode, and shows three examples of 30V, 50V, and 70V.

  Next, FIG. 6 is a graph showing respective time variations of Duty, generated power, Ipv, and Vpv in the detection mode as a specific example of this embodiment.

  Next, the operation of the power conditioner 2 of this embodiment will be described. First, the steady mode will be described. In the steady mode, the mode switch 17 in FIG. 1 is connected to the steady mode side. At this time, the DC-DC converter 7 performs PWM control of the power MOSFET 9 so that the input voltage Vin matches the input voltage command value 25 (Vref). The input voltage command value 25 (Vref) is a value obtained in advance, and how to obtain it will be described later.

  In the DC-DC converter 7, the input voltage Vin is detected by the voltage dividing resistors 15a and 15b, and converted into a digital quantity by the AD converter 21a. Further, the current sensor 13 detects the current flowing through the choke coil 8 (L). Since the current IL flowing through the choke coil 8 (L) pulsates by switching of the power MOSFET 9 described later, the current IL detected by the current sensor 13 is taken into the control circuit 14 through the AD converter 21b and recognized as an average value. . As a method for extracting the average value from the pulsating current IL, there is a method of providing a first-order lag filter for attenuating the switching frequency component of the power MOSFET 9 (S1) in the current sensor 13, or a timing for taking in the AD converter 21b as a PWM cycle. There is a method of always sampling the central value of pulsation in synchronization, and any method may be used as long as the average value can be extracted from the pulsating current IL. Hereinafter, the obtained average current value is described as IL.

  Vin output from the AD converter 21a is compared with the input voltage command value 25 (Vref) by the subtractor 18a, and these voltage errors are input to the PI control block 19a to be proportional-integral calculated. The output signal of the PI control block 19a is a current target value Iref. Next, IL is subtracted from the current target value Iref in the subtractor 18b. This current error is input to the PI control block 19b and subjected to proportional integration calculation. The output of the PI control block 19b is a duty ratio, and this duty is input to the PWM circuit 22 via the mode switch 17 to generate a PWM pulse. This PWM pulse is input to the gate of the power MOSFET 9 (S1) via the driver 24 to drive the power MOSFET 9 (S1). The power MOSFET 9 (S1) is repeatedly turned on and off by switching. This switching frequency is approximately 20 to 100 kHz. When the power MOSFET 9 (S1) is turned on, a closed circuit of the solar panel 1-input filter 4-choke coil 8 (L) -power MOSFET 9 (S1) -input filter 4-solar panel 1 is formed. A current flows from the panel 1 to the choke coil 8 (L). Next, when the power MOSFET 9 (S1) is turned OFF, the solar panel 1-input filter 4-choke coil 8 (L) -boost diode 10 (D1) -capacitor 11 (Cpn) -input filter 4-solar panel 1 circuit The excitation energy stored in the choke coil 8 (L) is released to the capacitor 11 (Cpn).

  When the input voltage Vin is higher than the voltage command value Vref, that is, when the voltage error is positive, the ON width of the drive signal of the power MOSFET 9 increases to increase the excitation energy stored in the choke coil 8 (L), and the input current Works to increase. On the contrary, when the input voltage Vin is lower than the voltage command value Vref, that is, when the voltage error is negative, the ON width of the drive signal of the power MOSFET 9 is reduced to reduce the excitation energy stored in the choke coil 8 (L), Operates to reduce input current. By repeating this operation, the voltage error is controlled to be zero. When the power MOSFET 9 (S1) is turned on, the excitation energy is stored in the choke coil 8 (L) and IL increases. When the power MOSFET 9 (S1) is turned off, the excitation energy stored in the choke coil 8 (L). Is discharged to the capacitor 11 (Cpn) and IL decreases. Here, the control is not limited to making the voltage error zero, but may be controlled to be a value close to zero.

  On the other hand, Vin and IL (average value) converted into digital quantities by the AD converters 21a and 21b are input to the multiplier 20, and the current instantaneous power Ppv is calculated. Ppv and Vin are input to the maximum value determination circuit 23. The maximum value determination circuit 23 searches for the maximum power point by an algorithm using the hill-climbing method, and sequentially changes the input voltage command value 25 (Vref) minutely. This hill-climbing algorithm compares Ppv (z-1) and Vin (z-1), which are the previous sample values, with Ppv and Vin collected this time. The direction in which 25 (Vref) is slightly changed is determined. With this algorithm, in the solar panel 1 having the characteristics as shown in FIG. 4, Vref can be changed so as to operate at a point (Vpmax, Ipmax) at which the power becomes maximum (Pmax).

  At this time, by using the input filter 4 as shown in FIG. 2, the pulsation component of IL mainly due to switching of the power MOSFET 9 (S1) is attenuated. On the other hand, regarding the voltage, the DC component of the voltage Vpv of the solar panel 1 input to the input filter 4 and the output voltage Vin of the input filter 4 are substantially equal, and Vin includes a high-frequency component accompanying switching.

  As a result, DC power of Ipv and Vpv flows from the solar panel 1 to the DC-DC converter 7, and the loss of the DC-DC converter 7 can be subtracted from the DC-DC converter 7 to the grid interconnection inverter 12. Electric power is output. In the grid interconnection inverter 12, the DC power input from the DC-DC converter 7 is converted into a sine wave current synchronized with the voltage phase of the commercial system 3 and output to the commercial system 3.

  Next, the detection mode will be described. In general, the voltage-current characteristic of the solar panel 1 is such that the voltage change (dV / di) is very large with respect to the current change in the vicinity of the short-circuit current point (0, Isc) as shown in FIG. It has become. On the other hand, in the DC-DC converter 7, the power MOSFET 9 is PWM-controlled to perform a switching operation to increase or decrease the current flowing through the choke coil 8 at a frequency of about 20 to 100 kHz, so that the vicinity of the short-circuit current point (0, Isc). In this case, the voltage of the solar panel 1 greatly fluctuates due to the ripple current of the choke coil 8, and Vin of the DC-DC converter 7 may vibrate. At this time, if feedback control is performed so as to make Vin coincide with the command value, there is a possibility that the phase is rotated and Vin oscillates. When Vin oscillates, the accurate voltage-current characteristics of the solar panel 1 and thus the maximum power point cannot be grasped, leading to a decrease in the MPPT efficiency of the power conditioner 2.

  In order to prevent oscillation by the conventional scanning method, it is necessary to suppress oscillation by suppressing the ripple current by setting the value of the choke coil 8 to 1 mH or more. Alternatively, the ripple current can be suppressed by setting the capacitance of the capacitor in the input filter 4 to about 500 to 2000 μF. However, all of these conventional countermeasures increase the volume and cost of the choke coil 8 and the input filter 4, and therefore have problems from the viewpoint of reducing the size and cost of the power conditioner 2.

  Therefore, in the present embodiment, the oscillation in the detection mode is performed while the inductance value of the choke coil 8 is suppressed to about 100 to 800 μH and the capacitor capacity in the input filter 4 is suppressed to about 5 to 30 μF by the following two means. It proposes a method to prevent this.

  In this embodiment, a method is employed in which the duty ratio for sequentially turning on / off the power MOSFET 9 is changed by open loop control without using feedback control in the detection mode. Thereby, even if vibration occurs in Vin, this Vin is detected and Duty is not changed, so that oscillation does not occur.

  In this embodiment, Dmax is determined in advance in the detection mode, and Duty is linearly changed (monotonically increased or monotonously decreased) between 0 and Dmax. When Duty becomes Dmax, the operating point of the solar panel 1 in FIG. 4 becomes (Vpvmin, Ipvmin). Since Vin tends to vibrate due to the ripple current of the choke coil 8 between (Vpvmin, Ipvmax) and the short-circuit current point (0, Isc), generation of vibration can be avoided by not performing characteristic detection in this section. .

  In the present embodiment, the operation is performed as follows reflecting the above idea. That is, when a certain time elapses in the steady mode, the mode transits to the detection mode. The detection mode is started by switching the mode switch 17 in FIG. 1 to the detection mode side. As can be seen from FIG. 1, in the detection mode, the feedback control system used in the steady mode is not used, and the duty ratio generated from the duty ratio generator 16 changes to an open loop control system that drives the power MOSFET 9. To do.

  At this time, the initial value of the duty ratio generator 16 is set to zero. Therefore, when the mode switch 17 is switched to the detection mode, the duty changes from the time ratio in the normal mode to zero. At this time, the operating point of the solar panel 1 moves to the coordinates of (Voc, 0) in FIG. As the duty gradually increases, the ON width of the power MOSFET 9 gradually increases and IL increases. In FIG. 4, this means that the operating point changes from the point (Voc, 0) to (Vpvmin, Ipvmax) via (Vpmax, Ipmax).

The waveform in the detection mode is as shown in FIG. When Duty increases linearly from 0 as shown in FIG. 3B, Ipv increases and Vpv decreases as shown in FIGS. 3C and 3D. At this time, the output power of the DC-DC converter 7 has a waveform as shown in FIG. 3E, and has a characteristic that the power gradually decreases after passing through the maximum power point Pmax. As apparent from FIG. 3B, in this embodiment, Duty rises linearly to a predetermined maximum value Dmax. Dmax is determined by the PN voltage Vpn and the minimum voltage Vpvmin in the detection mode. Dmax = (Vpn−Vpvmin) / Vpn (Equation 2)
Set to a value determined by.

  FIG. 5 is a graph showing Dmax when Vpn is 300 to 420 V and Vpvmin is 30 V, 50 V, and 70 V in Equation 2. In order to avoid vibrations, Vpvmin is preferably set to about 50 V in the case of the solar panel 1 having a rating of about 250 to 350 V. The PN voltage Vpn normally requires about 320 V in order to output AC 200 V to the system side. Since the conversion efficiency of the power conditioner 2 decreases as Vpn increases, it is generally set to about 340V. When the minimum voltage Vpvmin of the solar panel 1 is set to 50V and the VPN is set to 340V, Dmax is approximately 85%. Here, an example in which Dmax is approximately 85% will be described. However, by setting Dmax in the range of 80 to 90%, the same effect as described later can be obtained.

  In the detection mode, open-loop control is performed, but the duty ratio Duty is input to the PWM circuit 22 to generate a PWM pulse. This PWM pulse is input to the gate of the power MOSFET 9 (S1) to drive the power MOSFET 9 (S1). When the power MOSFET 9 (S1) is turned on, excitation energy is stored in the choke coil 8 (L) and IL increases. When the power MOSFET 9 (S1) is turned off, the excitation energy stored in the choke coil 8 (L) is Released to (Cpn) and IL decreases. As the duty increases, the ON time of the power MOSFET 9 increases and the IL increases. Ipv changes from (Voc, 0) to (Vpvmin, Ipvmax) according to the characteristics of the solid line shown in FIG. 4 as IL increases. At this time, IL and Vin are sampled by the AD converters 21a and 21b each time. The sampling period ts is about 25 to 100 μs. By detecting these and calculating Ppv by the multiplier 20, the maximum value determination circuit 23 can grasp Ppv and Vin at that time as a set of (Ppv, Vin). The maximum value determination circuit 23 stores Ppv as the maximum power point Pmax and stores Vin at that time as VinM when Ppv is larger than the previous set among the pairs of (Ppv, Vin) sequentially input.

  As Duty increases, the voltage Vpv gradually decreases from Voc and reaches Vpvmin at Dmax. During this time, since the operating point of Pmax, which is the maximum power point, passes through, the maximum value determination circuit 23 stores (Pmax, VinM) = (Pmax, Vpmax) when Duty = Dmax, which is the end point of the detection mode. Will be.

  Therefore, in the next steady mode, the maximum value determination circuit 23 outputs Vpmax as Vref. In the steady mode, as described above, the mode switch 17 is again connected to the steady side and performs feedback control so that Vin matches Vref. Vref is Vpmax obtained in the detection mode, and becomes an initial value in the steady mode, and operates while searching for a further maximum power point by the above-described hill-climbing method.

  If the time in the steady mode is T, the time is sufficiently longer than the time ts in the detection mode. For example, the detection mode time ts is in the order of 1 to several tens of ms, and the steady mode time T is in the order of several minutes to several tens of minutes.

  In addition, the inductance value of the choke coil 8 used at this time is approximately between 100 and 800H, and can be mounted on a printed circuit board.

Next, FIG. 6 will be described. FIG. 6 shows a power conditioner in which six solar panels 1 having a rating of Voc = 45.2V, Isc = 5.62A, Vpmax = 36.6V, Ipmax = 5.20A and rated at 190 W are connected in series and three in parallel. This is a simulation result assuming the case of connection to No. 2. Vpn = 340V, Vpvmin = 50V, Dmax = 85.3%, and the detection mode time is about 100 ms. Duty rises linearly from the detection mode start point (time zero). Although the time reaches 20% at 20 ms, Voc is 271.2V (= 45.2 × 6),
Vpv = Vpn (1-Duty) (Formula 3)
Therefore, if Duty does not become 20.2% or more, Vpv remains at the open circuit voltage. When the time becomes 20 ms or more and Duty becomes 20.2% or more, Vpv gradually decreases linearly, while the current Ipv increases rapidly. Accordingly, the power Ppv increases in the same manner as the current, and reaches a maximum value of about 3420 W when the duty is 35%. When Duty is 35% or more, the increase in current becomes small and the voltage decreases linearly, so that the power decreases almost linearly. When Duty reaches 85.3%, which is Dmax, Duty becomes constant and voltage Vpv becomes 50V.

  In this embodiment, di / dt in the detection mode does not depend on the inductance value of the choke coil 8, but depends on the increasing rate of the duty to be set, so that the inductance value of the choke coil can be freely selected. Thus, a small, light and low cost solar power generation system can be realized.

  In this way, in this embodiment, the maximum power point of the solar panel can be detected every predetermined time, and the power conditioner 2 can be operated at the detected maximum power point.

  In the present embodiment, as shown in FIG. 3, even in the detection mode, the power of the solar panel 1 is output from the DC-DC converter 7 and output to the commercial system 3 side via the system interconnection inverter 12. For this reason, even if di / dt is made small in order to improve detection accuracy, that is, the rate of increase in current change is slowed down and the detection mode is extended, power loss from the solar panel can be minimized. .

  In the present embodiment, the super-junction type power MOSFET 9 may be used as the power MOSFET 9 and may be replaced with other switching elements such as IGBT and SiC-MOSFET. It is also effective to apply a SiC device to the boost diode 10. The configuration of the DC-DC converter 7 is preferably the step-up converter shown in FIG. 1, but may be other non-insulated converters or isolated converters. In addition, the input filter 4 may have other configurations as long as it has a similar function, that is, a circuit configuration that prevents the current of the switching component from flowing to the solar panel and reduces common mode noise.

  Further, the control circuit 14 may be constituted by an analog circuit having a similar function. Although the PWM circuit 22 is a circuit that performs pulse width modulation control, it can be replaced by pulse frequency modulation control (PFM), pulse density modulation control (PDM), or the like. Further, the PI control blocks 19a and 19b are blocks that perform proportional-integral control, but may be configured by analog circuits such as operational amplifiers as described above, or may be replaced by PID (proportional-integral delay) control or the like.

  In this embodiment, the initial value of the duty ratio generator 16 is set to zero, but this is not restrictive. The reason why the initial value of the time ratio generator 16 is set to zero is that it also means that there is no leakage in sampling when detecting the maximum power point. Therefore, the initial value of the time ratio generator 16 is not limited to zero, but may be a value close to zero.

  Further, the value of the time ratio generator 16 may be changed to zero or a value close to zero by gradually reducing the value of the time ratio generator 16 when transitioning from the steady mode to the detection mode. By gradually reducing the value of the time ratio generator 16, it is possible to prevent a voltage jump due to the parasitic inductance of the cable between the solar panel 1 and the power conditioner 2.

  The timing at which the duty is gradually increased from zero or a value close to zero is constant switching regardless of whether the duty is zero or a value close to zero, even when a certain time has elapsed. It may be when the number of times is counted.

  Further, in this embodiment, the maximum value determination circuit 23 sets Ppv as the maximum power point Pmax when Ppv is larger than before in the set of (Ppv, Vin) sequentially input, and Vin at that time is VinM. However, this is not the case. Since it is sufficient to know the maximum power point Pmax, all the pairs (Ppv, Vin) sequentially input by the maximum value determination circuit 23 are stored, and the largest stored Ppv may be set as the maximum power point Pmax. . In this case, Vin at the maximum power point Pmax is set to VinM, and the subsequent steady mode is as described above for outputting Vpmax as VinM.

  In the present embodiment, the transition is made from the steady mode to the detection mode after a lapse of a fixed time, but this is not restrictive. It is only necessary to provide a timing for transition from the steady mode to the detection mode, and transition may be performed under a predetermined condition such as the number of times of switching.

  Further, in the present embodiment, the transition from the detection mode to the steady mode is made after a certain period of time, but this is not restrictive. The transition from the detection mode to the steady mode may be performed at the stage where the detection mode is completed or the stage where the maximum power point is detected, and the transition may be performed under a predetermined condition such as the number of times of switching.

  In this embodiment, the duty ratio generator 16 determines Duty and Dmax. However, the present invention is not limited to this.

In this embodiment, the increase in duty is started from 0. However, this is not the case, and when switching from the steady mode to the detection mode, the duty becomes zero and Voc is obtained.
Duty = (Vpn−Voc) / Vpn (Formula 4)
In FIG. 6, the duty may be increased stepwise from 0 to about 21%, and then the duty may be increased linearly.

  Next, a second embodiment of the present invention will be described with reference to FIGS. Note that the description of the points in common with the first embodiment will be omitted.

  FIG. 7 is a graph showing respective time variations of Duty, generated power, Ipv, and Vpv in the detection mode as a specific example of the present embodiment.

  FIG. 7 is also similar to FIG. 6 and includes six solar panels 1 rated in the order of 190 W having three characteristics: Voc = 45.2V, Isc = 5.62A, Vpmax = 36.6V, Ipmax = 5.20A. It is a simulation result that assumes a case of parallel connection to the power conditioner 2. Vpn = 340V, Vpvmin = 50V, Dmax = 85.3%, and the detection mode time is about 100 ms.

FIG. 7 differs from FIG. 6 in that the change in Duty in FIG. 6 is linear, whereas in FIG. Specifically, in the duty ratio generator 16 of FIG. 1, the change in Duty is calculated as follows: Duty = 1−exp (−t / τ) (Formula 5)
Determine as. Note that τ is a first-order lag time constant, and is set to 50 ms in this embodiment.

Also in this example,
Vpv = Vpn (1-Duty) (Formula 6)
Therefore, Vpv remains at the open circuit voltage Voc before 11 ms when Duty does not exceed 20%, but after that, the voltage Vpv drops rapidly and the current Ipv rises rapidly. As a result, the power Ppv is about 3420 W, which is the maximum value at about 22 ms, and then gradually decreases. Compared to FIG. 6, it can be seen that the voltage change starts earlier in FIG. 7, the time to reach the maximum power is shorter, and the time from the maximum power point to the Dmax point is longer.

  According to the present embodiment, it is possible to detect the maximum power point in an earlier time by changing the duty with a linear delay function than when the duty is changed linearly in the detection mode. Further, when Vpv is lowered, there is a concern that the change of Vpv with respect to the change of Ipv becomes large due to the characteristics of the solar panel 1, and vibration is generated by the ripple current of the DC-DC converter 7, but in this embodiment, the duty is in this region. The rate of change is suppressed.

  It should be noted that, while monitoring the decrease in power from the maximum power point, the detection mode may be interrupted and shifted to the steady mode, for example, when the power reaches 1/3 or less of the maximum power.

  Next, a third embodiment of the present invention will be described with reference to FIGS. Note that the description of the points in common with the first embodiment will be omitted.

  FIG. 8 shows, as a specific example of this embodiment, a graph in which each time change of Duty, generated power, Ipv, and Vpv in the detection mode, a waveform of the system voltage, and an output current of the grid interconnection inverter 12 are described. FIG.

  As in FIG. 6, FIG. 8 is similar to FIG. It is a simulation result assuming the case where it is set in parallel and connected to the power conditioner 2, and Vpn = 340V, Vpvmin = 50V, and Dmax = 85.3%.

  This embodiment is different from the other embodiments in that the change in Duty is devised to make the time change of Ppv in the detection mode sine half-wave, and the detection mode timing is synchronized with the system voltage phase. It is a point.

  The problem to be solved in the present embodiment is to eliminate the point that the fluctuation of the power output to the system side is large in the detection mode, unlike the steady mode.

In FIG. 8, the system voltage is AC200V / 50Hz. The change in Duty is about 21% at the detection mode start point. This is the measurement of the open circuit voltage Voc just before the transition from the steady mode to the detection mode.
Duty = (Vpn−Voc) / Vpn (Expression 7)
Ask for. As shown in the figure, the duty is increased in the form of a suspended line and is changed to 27% at 2.5 ms, 36% at 5 ms, 49% at 7.5 ms, and 85% at 10 ms. Thereby, when the solar panel 1 is in a state where rated output is possible, Ppv has a shape close to a sine half wave that takes the maximum power point at 10 ms.

  On the other hand, in this embodiment, it is proposed that the detection mode is set to 10 ms and the start point and end point of the detection mode are substantially synchronized with the zero cross point of the system voltage. As a result, the generated power Ppv is the lowest at the zero cross point where the power supply to the system becomes zero, and conversely, the Ppv becomes the largest at a phase of 90 degrees (at 5 ms) when the power supply to the system is the largest. As a result, in the capacitor 11 (Cpn) shown in FIG. 1, the difference between the power flowing from the solar panel 1 side and the power output to the grid-connected inverter 12 side is suppressed smaller than that detected by other patterns. be able to. As a result, fluctuations in the electric power output from the power conditioner 2 to the commercial system 3 before and after the detection mode can be suppressed.

DESCRIPTION OF SYMBOLS 1 Solar panel 2 Power conditioner 3 Commercial system 4 Input filter 5a, 5b Common mode choke 6a, 6b, 6c, 6d, 6e, 6f Filter capacitor 7 DC-DC converter 8 Choke coil 9 Power MOSFET
DESCRIPTION OF SYMBOLS 10 Boost diode 11 Capacitor 12 Grid connection inverter 13 Current sensor 14 Control circuit 15a, 15b Voltage dividing resistor 16 Time ratio generator 17 Mode switch 18a, 18b Subtractor 19a, 19b PI control block 20 Multiplier 21a, 21b AD conversion 22 PWM circuit 23 Maximum value determination circuit 24 Driver 25 Input voltage command value

Claims (5)

Solar panels,
Power detection means for detecting the output power of the solar panel;
Power conversion means for outputting electric power of a voltage obtained by converting the output voltage of the solar panel by an on / off operation of a switching element;
Control means for controlling the switching element while receiving an output of the power detection means;
A solar power generation system comprising:
The control means controls the switching element in an open loop and changes a time ratio for driving the switching element between 0% and a predetermined upper limit value.
A solar power generation system, wherein a maximum power point of the solar panel is detected in the process. In the photovoltaic power generation system according to claim 1,
The predetermined upper limit value is 80 to 90%. The solar power generation system according to claim 1 or 2,
In the process of changing the time ratio for driving the switching element, the time ratio is monotonously increased from 0% to the predetermined upper limit value. The solar power generation system according to claim 1 or 2,
In the process of changing the time ratio for driving the switching element, the time ratio is monotonously decreased from the predetermined upper limit value to 0%.   Solar panels,
  Power detection means for detecting the output power of the solar panel;
  The output voltage of the solar panel is controlled by the on / off operation of the switching element.
  Power conversion means for outputting the power of the converted voltage;
  Control means for controlling the switching element while receiving an output of the power detection means;
A solar power generation system comprising:
  The control means changes a time ratio for driving the switching element,
  While detecting the maximum power point of the solar panel in the process,
  The detection is performed during a half cycle of the system voltage in synchronization with the zero crossing of the system voltage.
Solar power generation system.