JP5892695B2 - Wiring board - Google Patents

Wiring board Download PDF

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JP5892695B2
JP5892695B2 JP2012069282A JP2012069282A JP5892695B2 JP 5892695 B2 JP5892695 B2 JP 5892695B2 JP 2012069282 A JP2012069282 A JP 2012069282A JP 2012069282 A JP2012069282 A JP 2012069282A JP 5892695 B2 JP5892695 B2 JP 5892695B2
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semiconductor element
wiring
element connection
connection pads
insulating substrate
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JP2013201321A (en
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茂治 木村
茂治 木村
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京セラサーキットソリューションズ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、半導体素子等を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a semiconductor element or the like.

従来、半導体素子集積回路素子等の半導体素子を搭載するための配線基板は、図３（ａ）および（ｂ）に示すように、上面中央部に半導体素子Ｓを搭載するための搭載部１１ａを有する絶縁基板１１と、絶縁基板１１の上面に、搭載部１１ａの外周部を互いに隣接して半導体素子Ｓの外周辺に直角な方向に延在するとともに絶縁基板１１の下面に導出する複数の配線導体１２と、絶縁基板１１の上面に被着されており、搭載部１１ａの外周部における配線導体１２の一部を露出させる開口部１３ａを有するとともに、残余の配線導体１２を被覆するソルダーレジスト層１３とを具備している。   Conventionally, as shown in FIGS. 3A and 3B, a wiring substrate for mounting a semiconductor element such as a semiconductor element integrated circuit element has a mounting portion 11a for mounting a semiconductor element S at the center of the upper surface. And a plurality of wirings extending on the upper surface of the insulating substrate 11 in a direction perpendicular to the outer periphery of the semiconductor element S adjacent to each other and extending to the lower surface of the insulating substrate 11 A solder resist layer that is attached to the top surface of the conductor 12 and the insulating substrate 11 and has an opening 13a that exposes a part of the wiring conductor 12 in the outer peripheral portion of the mounting portion 11a and covers the remaining wiring conductor 12 13.

開口部１３ａから露出された配線導体１２の一部は、半導体素子Ｓの外周辺に沿って互いに並設された複数の半導体素子接続パッド１４として機能する。また、絶縁基板１１の下面に露出する配線導体１２は、外部の電気回路基板に接続するための外部接続パッド１５として機能する。そして、半導体素子Ｓの電極Ｔを半導体素子接続パッド１４に半田を介して接続するとともに、外部接続パッド１５を外部の電気回路基板の配線導体に半田を介して接続することにより半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体１２に信号を伝送することにより半導体素子Ｓが作動する。なお、上述のようにして半導体素子Ｓが配線基板２０に搭載される場合、半導体素子Ｓと配線基板２０との間の隙間を封止樹脂により充填しておき水分や異物等が隙間に浸入することを防止することで半導体素子Ｓの作動を安定化させている。   A part of the wiring conductor 12 exposed from the opening 13a functions as a plurality of semiconductor element connection pads 14 arranged in parallel along the outer periphery of the semiconductor element S. Further, the wiring conductor 12 exposed on the lower surface of the insulating substrate 11 functions as an external connection pad 15 for connecting to an external electric circuit substrate. Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 14 via solder, and the external connection pad 15 is connected to the wiring conductor of the external electric circuit board via solder so that the semiconductor element S is externally connected. The semiconductor element S is operated by transmitting a signal to the wiring conductor 12 between the semiconductor element S and the external electric circuit board. When the semiconductor element S is mounted on the wiring board 20 as described above, the gap between the semiconductor element S and the wiring board 20 is filled with sealing resin, and moisture, foreign matter, etc. enter the gap. By preventing this, the operation of the semiconductor element S is stabilized.

ところで、半導体素子Ｓと配線基板２０との間の隙間に封止樹脂を充填する際に、搭載部１１ａにおける半導体素子接続パッド１４よりも内側部分に封止樹脂をあらかじめ山状に被着させておき、それぞれが対応する半導体素子Ｓの電極Ｔと、半導体素子接続パッド１４とが対向するように位置決めされた半導体素子Ｓを、搭載部１１ａの上方から下方へ下降させて電極Ｔと半導体素子接続パッド１４とを接合すると同時に、山状に被着された封止樹脂を半導体素子Ｓと配線基板２０との隙間に押し広げていく方法がとられる場合がある。このように、封止樹脂が搭載部１１ａの中央部から外周部に向けて押し広げられることで半導体素子Ｓと配線基板２０との隙間が充填される。   By the way, when the sealing resin is filled in the gap between the semiconductor element S and the wiring substrate 20, the sealing resin is previously deposited in a mountain shape on the inner side of the mounting portion 11a than the semiconductor element connection pad 14. Each of the semiconductor elements S positioned so that the electrodes T of the corresponding semiconductor elements S and the semiconductor element connection pads 14 face each other is lowered from above the mounting portion 11a to connect the electrodes T and the semiconductor elements. At the same time as bonding the pad 14, there may be a method in which the sealing resin deposited in a mountain shape is pushed out into the gap between the semiconductor element S and the wiring substrate 20. Thus, the gap between the semiconductor element S and the wiring substrate 20 is filled by the sealing resin being spread from the central portion of the mounting portion 11a toward the outer peripheral portion.

ところが、封止樹脂が搭載部１１ａの中央部から外周部に向けて押し広げられる際に、図４に示すように、互いに並設された半導体素子接続パッド１４間のソルダーレジスト層１３の開口縁１６において、封止樹脂が気泡Ｂを巻き込んで滞留させてしまい、半導体素子接続パッド１４と気泡Ｂとが接触状態となる場合があった。このように、半導体素子接続パッド１４と気泡Ｂとが接触状態になっていると、半導体素子接続パッド１４間の電気的な絶縁性が不十分となる恐れがあった。   However, when the sealing resin is spread from the central portion of the mounting portion 11a toward the outer peripheral portion, as shown in FIG. 4, the opening edge of the solder resist layer 13 between the semiconductor element connection pads 14 arranged in parallel with each other, as shown in FIG. 16, the sealing resin entrains and retains the bubbles B, and the semiconductor element connection pad 14 and the bubbles B may be in contact with each other. Thus, when the semiconductor element connection pad 14 and the bubble B are in contact with each other, there is a fear that the electrical insulation between the semiconductor element connection pads 14 may be insufficient.

特開２０１１−１９９２０８号公報JP 2011-199208 A

本発明は、半導体素子搭載時に半導体素子と配線基板との隙間に封止樹脂が充填される配線基板について、並設された半導体素子接続パッド間のソルダーレジスト層の開口縁において半導体素子接続パッドと封止樹脂中の気泡との接触をなくすことで、並設された半導体素子接続パッド間の電気的な絶縁性が良好な配線基板を提供することを課題とする。   The present invention relates to a wiring board in which a sealing resin is filled in a gap between the semiconductor element and the wiring board when the semiconductor element is mounted, and the semiconductor element connection pad at the opening edge of the solder resist layer between the semiconductor element connection pads arranged side by side. It is an object of the present invention to provide a wiring substrate with good electrical insulation between semiconductor element connection pads arranged side by side by eliminating contact with bubbles in the sealing resin.

本発明の配線基板は、上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、絶縁基板の上面に搭載部の外周部を互いに隣接して半導体素子の外周辺に直角な方向に延在する複数の配線導体と、絶縁基板の上面に被着されており、外周部における配線導体の一部を外周辺に沿って互いに並設された複数の半導体素子接続パッドとして露出させる開口部を有するとともに配線導体の残余の部分を被覆するソルダーレジスト層とを具備して成る配線基板であって、開口部は、並設された半導体素子接続パッド間の開口縁において、開口縁の両端部から半導体素子接続パッド間の中間位置に向かって漸次幅が小さくなっていく切り欠きが形成されていることを特徴とするものである。 The wiring board of the present invention includes an insulating substrate having a mounting portion on which the semiconductor element is mounted at the center of the upper surface, and an outer peripheral portion of the mounting portion adjacent to each other on the upper surface of the insulating substrate in a direction perpendicular to the outer periphery of the semiconductor element. A plurality of wiring conductors that extend and an opening that is attached to the upper surface of the insulating substrate and exposes a part of the wiring conductors in the outer peripheral portion as a plurality of semiconductor element connection pads arranged in parallel along the outer periphery And a solder resist layer covering the remaining portion of the wiring conductor, wherein the openings are at both ends of the opening edge at the opening edge between the semiconductor element connection pads arranged side by side A notch whose width gradually decreases toward an intermediate position between the semiconductor element connection pads is formed.

本発明の配線基板によれば、ソルダーレジスト層の開口部が、並設された半導体素子接
続パッド間の開口縁において、開口縁の両端部から半導体素子接続パッド間の中間位置に向かって漸次幅が小さくなっていく切り欠きが形成されていることから、封止樹脂が搭載部の中央部から外周部に向けて押し広げられる際に、半導体素子接続パッド間の開口縁において気泡を巻き込んだ場合でも、気泡が半導体素子接続パッドと接触状態となることなく切り欠きの中に誘導されていく。このため、半導体素子接続パッド間の開口縁において半導体素子接続パッドと封止樹脂中の気泡との接触をなくすことが可能となり、並設された半導体素子接続パッド間の電気的な絶縁性が良好な配線基板を提供することができる。


According to the wiring substrate of the present invention, the opening of the solder resist layer is gradually widened from both ends of the opening edge toward the intermediate position between the semiconductor element connection pads at the opening edge between the semiconductor element connection pads arranged side by side. When the sealing resin is spread from the central part of the mounting part toward the outer peripheral part, bubbles are involved at the opening edge between the semiconductor element connection pads. However, the bubbles are guided into the notches without coming into contact with the semiconductor element connection pads . For this reason, it is possible to eliminate contact between the semiconductor element connection pads and the bubbles in the sealing resin at the opening edges between the semiconductor element connection pads, and the electrical insulation between the semiconductor element connection pads arranged in parallel is good. A simple wiring board can be provided.


図１（ａ）および（ｂ）は、本発明の配線基板の実施の形態の一例を示す概略断面図および平面図である。1A and 1B are a schematic cross-sectional view and a plan view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の要部拡大平面図である。FIG. 2 is an enlarged plan view of a main part of the wiring board shown in FIG. 図３（ａ）および（ｂ）は、従来の配線基板の実施の形態の一例を示す概略断面図および平面図である。3A and 3B are a schematic cross-sectional view and a plan view showing an example of an embodiment of a conventional wiring board. 図４は、図３に示す配線基板の要部拡大平面図である。4 is an enlarged plan view of a main part of the wiring board shown in FIG.

次に、本発明の実施形態の一例を図１（ａ）および（ｂ）を基に説明する。図１（ａ）に示すように本例の配線基板は、主として絶縁基板１と、配線導体２とソルダーレジスト層３とを具備している。   Next, an example of an embodiment of the present invention will be described based on FIGS. 1 (a) and 1 (b). As shown in FIG. 1A, the wiring board of this example mainly includes an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3.

絶縁基板１は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁基板１は、この例では単層構造であるが、同一または異なる電気絶縁材料から成る複数の絶縁層を多層に積層した多層構造であってもよい。   The insulating substrate 1 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The insulating substrate 1 has a single-layer structure in this example, but may have a multilayer structure in which a plurality of insulating layers made of the same or different electrically insulating materials are stacked in multiple layers.

絶縁基板１は、その上面中央部に半導体素子Ｓが搭載される搭載部１ａを有している。搭載部１ａは半導体素子Ｓに対応する大きさおよび形状をしている。また、絶縁基板１の下面は、外部の電気回路基板と接続するための接続面となっている。   The insulating substrate 1 has a mounting portion 1a on which the semiconductor element S is mounted at the center of the upper surface. The mounting portion 1a has a size and shape corresponding to the semiconductor element S. The lower surface of the insulating substrate 1 is a connection surface for connecting to an external electric circuit substrate.

配線導体２は、絶縁基板１の上面を搭載部１ａの外周部において互いに隣接して半導体素子Ｓの外周辺に直角な方向に延在するとともに絶縁基板１を貫通して絶縁基板１の下面に導出している。このような、配線導体２は、例えば銅めっきから成り、周知のサブトラクティブ法やセミアディティブ法により形成されている。   The wiring conductor 2 extends in a direction perpendicular to the outer periphery of the semiconductor element S adjacent to each other on the outer peripheral portion of the mounting portion 1 a on the upper surface of the insulating substrate 1 and penetrates the insulating substrate 1 to the lower surface of the insulating substrate 1. Derived. Such a wiring conductor 2 is made of, for example, copper plating and is formed by a known subtractive method or semi-additive method.

配線導体２は、その一部が搭載部１ａの外周部において、ソルダーレジスト層３に形成された開口部３ａから露出されて半導体素子接続パッド４として機能する。また、絶縁基板１の下面に導出した部位に外部の電気回路基板に接続するための外部接続パッド５を有している。そして、半導体素子Ｓの電極Ｔを半導体素子接続パッド４に半田を介して接続するとともに、外部接続パッド５を外部の電気回路基板の配線導体に半田を介して接続することにより半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体２に信号を伝送することにより半導体素子Ｓが作動する。   A part of the wiring conductor 2 is exposed from the opening 3 a formed in the solder resist layer 3 in the outer peripheral portion of the mounting portion 1 a and functions as the semiconductor element connection pad 4. In addition, an external connection pad 5 for connecting to an external electric circuit board is provided at a portion led out to the lower surface of the insulating substrate 1. Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 via solder, and the external connection pad 5 is connected to the wiring conductor of the external electric circuit board via solder, whereby the semiconductor element S is externally connected. The semiconductor element S is operated by transmitting a signal to the wiring conductor 2 between the semiconductor element S and the external electric circuit board.

半導体素子接続パッド４は、図１（ｂ）に示すように、半導体素子Ｓの電極Ｔに対応するように配置されている。この例では、絶縁基板１の中央部から外周部に向けて延在する複数の配線導体２のそれぞれの一部が開口部３ａから露出されることで、開口部３ａ内に複数の半導体素子接続パッド４が並設されている。   The semiconductor element connection pad 4 is disposed so as to correspond to the electrode T of the semiconductor element S as shown in FIG. In this example, a part of each of the plurality of wiring conductors 2 extending from the central portion to the outer peripheral portion of the insulating substrate 1 is exposed from the opening 3a, so that a plurality of semiconductor element connections are formed in the opening 3a. Pads 4 are juxtaposed.

ソルダーレジスト層３は、アクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂を硬化させた電気絶縁材料から成る。ソルダーレジスト層３は、搭載部１ａにおける配線導体２の一部を露出させる開口部３ａを有しているとともに、配線導体２の残余の部分を被覆している。これにより半導体素子接続パッド４に半導体素子Ｓの電極Ｔを接続可能とするとともに配線導体２の残余の部分を外部環境より保護している。   The solder resist layer 3 is made of an electrically insulating material obtained by curing a photosensitive thermosetting resin such as an acrylic-modified epoxy resin. The solder resist layer 3 has an opening 3 a that exposes a part of the wiring conductor 2 in the mounting portion 1 a and covers the remaining portion of the wiring conductor 2. Thus, the electrode T of the semiconductor element S can be connected to the semiconductor element connection pad 4 and the remaining portion of the wiring conductor 2 is protected from the external environment.

開口部３ａは、並設された半導体素子接続パッド４間の開口縁６において、半導体素子接続パッド４間の中間位置に向かって幅が細くなっていく切り欠き７が形成されている。これにより、半導体素子Ｓと配線基板１０との間の隙間に封止樹脂を充填する際に、図２に示すように、並設された半導体素子接続パッド４間の開口縁６において封止樹脂が気泡Ｂを巻き込んだ場合でも、気泡Ｂが切り欠き７の中に誘導されることで、半導体素子接続パッド４と気泡Ｂとが接触状態となることを回避することができる。なお、切り欠き７の開口幅Ｗは２０μｍ以上であり、奥行きＬは１５μｍ以上であることが好ましい。開口幅Ｗが２０μｍより小さく、奥行きＬが１５μｍより小さいと、気泡Ｂを半導体素子接続パッド４に接触しないように切り欠き７内に完全に誘導することが困難になる恐れがある。   The opening 3 a is formed with a notch 7 whose width becomes narrower toward an intermediate position between the semiconductor element connection pads 4 at the opening edge 6 between the semiconductor element connection pads 4 arranged side by side. Thus, when the sealing resin is filled in the gap between the semiconductor element S and the wiring substrate 10, the sealing resin is formed at the opening edge 6 between the semiconductor element connection pads 4 arranged side by side as shown in FIG. Even when the bubble B entrains, the bubble B is guided into the notch 7, thereby avoiding contact between the semiconductor element connection pad 4 and the bubble B. The opening width W of the notch 7 is preferably 20 μm or more and the depth L is preferably 15 μm or more. If the opening width W is smaller than 20 μm and the depth L is smaller than 15 μm, it may be difficult to completely guide the bubble B into the notch 7 so as not to contact the semiconductor element connection pad 4.

このように、本発明の配線基板１０によれば、半導体素子接続パッド４と気泡Ｂとの接触を回避することで、半導体素子接続パッド４間の電気的な絶縁性を良好なものにすることができる。   As described above, according to the wiring substrate 10 of the present invention, the electrical insulation between the semiconductor element connection pads 4 is improved by avoiding the contact between the semiconductor element connection pads 4 and the bubbles B. Can do.

１ 絶縁基板
１ａ 搭載部
２ 配線導体
３ ソルダーレジスト層
３ａ 開口部
４ 半導体素子接続パッド
６ 開口縁
７ 切り欠き
１０ 配線基板
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a Mounting part 2 Wiring conductor 3 Solder resist layer 3a Opening part 4 Semiconductor element connection pad 6 Opening edge 7 Notch 10 Wiring board S Semiconductor element

Claims (1)

上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、該絶縁基板の上面に前記搭載部の外周部を互いに隣接して前記半導体素子の外周辺に直角な方向に延在する複数の配線導体と、前記絶縁基板の上面に被着されており、前記外周部における前記配線導体の一部を前記外周辺に沿って互いに並設された複数の半導体素子接続パッドとして露出させる開口部を有するとともに前記配線導体の残余の部分を被覆するソルダーレジスト層とを具備して成る配線基板であって、前記開口部は、並設された前記半導体素子接続パッド間の開口縁において、該開口縁の両端部から前記半導体素子接続パッド間の中間位置に向かって漸次幅が小さくなっていく切り欠きが形成されていることを特徴とする配線基板。 An insulating substrate having a mounting portion on which a semiconductor element is mounted at the center of the upper surface, and a plurality of outer peripheral portions of the mounting portion adjacent to each other and extending in a direction perpendicular to the outer periphery of the semiconductor element on the upper surface of the insulating substrate Wiring conductors and openings that are attached to the upper surface of the insulating substrate and expose a part of the wiring conductors in the outer peripheral part as a plurality of semiconductor element connection pads arranged in parallel along the outer periphery. a wiring board formed by and a solder resist layer covering the remaining portion of the wiring conductor which has a said opening in the opening edge between the semiconductor element connection pads juxtaposed, said opening A wiring board, wherein notches whose width gradually decreases from both end portions of the edge toward an intermediate position between the semiconductor element connection pads are formed.
JP2012069282A 2012-03-26 2012-03-26 Wiring board Expired - Fee Related JP5892695B2 (en)

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