JP5882800B2 - Information processing device having list command verification function, list command verification method, and program for list command verification - Google Patents

Description

  The present invention relates to an information processing apparatus having a list instruction verification function for collectively performing a plurality of memory accesses, a list instruction verification method, and a program for verifying a list instruction

  Various techniques for speeding up and improving efficiency have been proposed for accessing the storage means constituting the information processing apparatus.

  For example, in Patent Document 1, in an information processing apparatus composed of a plurality of arithmetic devices and a plurality of storage devices, when a plurality of access requests to the same address of one storage device are issued, the plurality of requests are indicated. An example of a technique for compressing into one request is described.

  The technology related to request compression described in Patent Document 1 is compressed with a function of compressing a plurality of requests into one request when a plurality of requests to the same main memory address are issued from a plurality of arithmetic devices. A function of expanding reply data from the storage device for the requested request toward the plurality of arithmetic devices to be compressed.

  In addition, as an information processing apparatus that issues and processes a plurality of instructions at once, for example, there is a vector type computer, and this vector type computer generally executes an instruction for performing a plurality of memory accesses collectively called a list instruction. I have.

  There are two types of list instructions: a gather instruction that reads a plurality of data from the memory at once, and a scatter instruction that writes a plurality of data to the memory at a time.

  These two instructions specify the address of the memory to be accessed for each of a plurality of vector elements. Therefore, when a plurality of the same memory addresses are specified, a plurality of memory access requests are generated for the same address. For this reason, contention occurs in memory access processing, leading to performance degradation of the entire computer system.

  Therefore, when a plurality of memory access requests are generated for the same address, a high speed function for compressing the plurality of requests into one request and performing processing is often added to the computer system.

JP-A-9-44459

  The technique described in Patent Document 1 and the memory access request compression technique of the vector computer described above are difficult to verify with a test program whether or not these compression processes have been performed correctly. There is a point.

  The reason is that even if the compression process is not performed, it may not be determined from the execution result.

  For example, in the case where a plurality of memory access requests are generated for the same address with the above-mentioned vector computer gather instruction, in the case of no compression, a conflict occurs in the memory access processing, and the plurality of requests are processed in order. As a result, the same reply data is returned for each request.

  Next, when the plurality of memory access requests are compressed into one request, the reply data is one, but since the plurality of memory access requests are duplicated and returned, the execution result is the plurality of memory access requests. The same reply data is returned to the memory access request one by one.

  Therefore, the execution result is the same as when no compression is performed, and it is impossible to detect whether or not the compression process has been performed only by looking at the execution result.

  An object of the present invention is to provide an information processing apparatus having a list instruction verification function capable of solving the above-described problems, a list instruction verification method, and a program for verifying a list instruction.

The information processing apparatus of the present invention has a plurality of memory ports and stores a plurality of data, and a storage means for accessing the data via the memory ports;
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. Memory request control means for issuing to the storage means via the port;
The number of memory access requests provided in a one-to-one correspondence with the plurality of memory ports, when the list instruction is issued, and when the memory access request is issued to the corresponding port from the memory request control means And a plurality of counter means for counting.

The list instruction verification method of the present invention is an information processing apparatus comprising a storage means having a plurality of memory ports and storing a plurality of data, wherein the data is accessed via the memory ports.
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. And issued to the storage means via the port,
When the list command is issued and the memory access request is issued to the port in the memory request control step, the number of memory access requests is counted for each port.

A program for verifying a list instruction according to the present invention includes:
In an information processing apparatus having a plurality of memory ports and storing a plurality of data, and having a storage means for accessing the data via the memory ports,
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. A memory request control process to be issued to the storage means via the port;
When the list instruction is issued and the memory access request is issued to the port by the memory request control process, the computer executes a counting process for counting the number of memory access requests for each port. .

  According to the present invention, it is possible to verify whether or not the compression processing of the memory access request in the list instruction is correctly performed.

FIG. 1 is a block diagram showing a general configuration of an information processing apparatus that issues and processes a plurality of instructions at once. FIG. 2 is a schematic diagram showing an example of a general memory access operation at the time of gather instruction processing. FIG. 3 is a block diagram showing the configuration of the embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of the list command request number counter unit in the embodiment of the present invention. FIG. 5 is a flowchart showing the operation of the test program in the embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of the operation of the memory request control unit according to the embodiment of the present invention. FIG. 7 is a diagram showing a configuration of a list command request counter value transfer command in the embodiment of the present invention.

  An example of compression processing operation for the number of memory access requests of gather instructions, which is one of list instructions generally provided in an information processing apparatus (for example, a vector computer) that issues and processes a plurality of instructions in a batch A description will be given with reference to FIGS.

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus 10 that issues and processes a plurality of instructions at once.
Referring to FIG. 1, the information processing apparatus 10 includes a control unit 20 and a storage unit 30. Note that FIG. 1 shows only the components related to the present description in the overall configuration of the information processing apparatus 10.

  The control unit 20 includes a memory request control unit 21 and a vector register 22.

  The storage means 30 includes a data storage area 31.

  Then, there are eight ports (port 0 to port 7) for accessing the storage means 30 from the control means 20, and data in a specific storage area of the data storage area 31 can be accessed from each port.

  FIG. 2 is a schematic diagram showing an example of a memory access operation at the time of gather instruction processing in the memory request control unit 21.

  The gather instruction is an instruction that reads data from a plurality of address storage areas designated for each vector element and stores them in the vector register 22 at a time.

  First, a case where there is no compression of the number of memory access requests will be described with an example shown in FIG.

  Referring to the example shown in FIG. 2A, the access address of vector element 0 is “address A”. Similarly, the access address of the vector element 1 is “address B”, the access address of the vector element 2 is “address C”, and the access address of the last vector element 7 is “address H”. That is, eight memory access requests corresponding to vector element 0 to vector element 7 are issued, one for each.

  At this time, which memory access request the memory request control unit 21 issues to which memory port depends on the access addresses of the vector elements 0 to 7.

  In the example shown in FIG. 2A, “address A” is present in the storage area accessed from the memory port 0. Similarly, “address B” indicates that the memory area is accessed from the memory port 1, “address C” indicates that the memory area is accessed from the memory port 1, and the last “address H”. Indicates that the data exists in a storage area accessed from the memory port 7. That is, in the case of FIG. 2A, the memory request control unit 21 has one memory port 0, one memory port 3, one memory port 4, and one memory port 5, and one memory port 1 , A total of eight memory access requests are issued to the memory port 7, two each.

  In response to these memory access requests issued to each memory port, the data requested by each memory access request to each memory port is returned from the data storage area 31 as reply data. The memory request control unit 21 stores these reply data in the corresponding vector register.

  Next, a case where there is compression of the number of memory access requests will be described with reference to an example shown in FIG.

  In the gather instruction, a memory address to be accessed is designated for each vector element. When the same memory address is designated by a plurality of vector elements, the memory request control unit 21 selects an element number among the vector elements. Represents the request of the vector element with the larger one (processing of request compression) and performs processing.

  In the example of FIG. 2B, the access addresses of vector element 0 to vector element 3 all match at “address A”, and the access addresses of vector element 4 to vector element 7 all match at “address E”. This is the case. In this case, the memory request control unit 21 employs the memory access request to the “address A” of the vector element 3 and the memory access request to the “address E” of the vector element 7 as a representative. Then, the memory request control unit 21 issues a memory access request to the memory port 0 and the memory port 4 corresponding to each address. That is, the memory request control unit 21 compresses eight memory access requests from the vector element 0 to the vector element 7 into two requests of the vector element 3 and the vector element 7. That is, the number of requests is reduced from 8 to 2.

  When the reply data is returned to each memory port, the memory request control unit 21 converts the returned reply data A from the vector element 0 to the vector register for the vector element 3 from the stored compression information. In addition, the reply data E is stored in the vector registers for the vector element 4 to the vector element 7, respectively.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention.
Referring to FIG. 3, the information processing apparatus 100 includes a control unit 200 and a storage unit 300. FIG. 3 shows only components related to the present invention in the overall configuration of the information processing apparatus 100.

  The control unit 200 includes a memory request control unit 210, a vector register 220, and a software visible register 230.

  The storage means 300 includes a data storage area 310 and a software simulator execution result storage area 320.

  There are eight ports (port 0 to port 7) for accessing the storage means 300 from the control means 200, and access to data in a specific storage area of the data storage area 310 from each port. Can do.

  Next, the configuration and operation of the control means 200 will be briefly described.

  The software visible register 230 is a register in which a value can be referred from a program, and there are a plurality of software visible registers 230.

  The vector register 220 is a commonly used register, and usually stores an address and data when a program operates.

  The control means 200 transfers the value of the list instruction request number counter block 211 provided in the memory request control unit 210 described later to the software visible register 230 by a list instruction request number counter value transfer instruction.

The configuration of the list command request counter value transfer command is shown in FIG.
Referring to FIG. 7, the list command request number counter value transfer command is composed of “opcode”, “MODE”, and “REG”. The “opcode” is a code that instructs the memory request control unit 210 to execute a list command request number counter value transfer command. “MODE” indicates a data transfer direction between the list command request counter block 211 and the software visible register 230. When the value of “MODE” is “0”, data is transferred from the list command request counter block 211 to the software visible register 230. On the contrary, when the value of “MODE” is “1”, data is transferred from the software visible register 230 to the list instruction request number counter block 211. “REG” represents a number for identifying one of the plurality of software visible registers 230.

  The memory request control unit 210 includes a list command request counter block 211. Then, the memory request control unit 210 determines whether the instruction of the memory request issued by the program is a list instruction. If the instruction is a list instruction, the memory request control unit 210 performs a compression process if the number of requests can be compressed. The count-up process of the instruction request counter block 211 is performed.

  FIG. 4 shows a configuration of the list command request counter 211-2 provided for each port in the list command request counter 211. In other words, the list command request counter block 211 has eight list command request counters 211-0 corresponding to the memory ports of the memory request controller 210.

  Referring to FIG. 4, the list command request counter 211-2 includes an AND gate 211-1, a selector 211-2, an 8-bit list command request counter 211-3, and a +1 adder 211-4. Prepare.

  Next, the configuration and operation of the list command request counter 211-2 will be briefly described.

  First, the list command request counter 211-0 receives memory request command information from the memory request controller 210. Here, the input V of the AND gate 211-1 indicates whether or not the memory request instruction is valid, and possible values are “1” is valid and “0” is invalid. The input L indicates whether the memory request command is a list command. Possible values are “1” for a list command and “0” for other than a list command.

  The list command request counter 211-0 has a case where the input V of the AND gate 211-1 is "1" (memory request command is valid) and L is "1" (list command). That is, the output is “1” only when the memory request instruction is valid and is a list instruction. Therefore, the selector 211-2 selects the output of the +1 adder 211-4 (that is, a value obtained by adding 1 to the value of the counter 211-3 at that time) and stores it in the list instruction request number counter 211-3. . As a result, 1 is added to the value of the list command request counter 211-1.

  Next, the configuration and operation of the storage unit 300 will be briefly described.

  The software simulator execution result storage area 320 is a storage area for storing simulation results of the number of list instruction requests executed by the software simulator. The program reads the value stored in this storage area and compares it with the value of the list instruction request counter block stored in the software visible register 230.

  The data storage area 310 is a storage area for storing normal data, and a memory request instruction issued by a program reads and writes data through a memory port corresponding to a specified address.

  The operation of the information processing apparatus 100 configured as described above will be described with reference to the flowchart of FIG. 5 and the schematic diagram of FIG.

  FIG. 5 is a flowchart showing an outline of the operation of the test program in the embodiment of the present invention.

  FIG. 6 is a schematic diagram showing an example of the memory access operation when the memory request control unit 210 executes the above-described test program.

  Note that the example of FIG. 6 uses the same conditions as the example of the memory access operation during the gather instruction processing of FIG. That is, when access to the same memory address is specified by a plurality of vector elements, the memory request control unit 210 adopts a request of a vector element having a larger vector element number (request compression). Process.

  In the example of FIG. 2, the access addresses of the vector element 0 to the vector element 3 all match at “address A”, and the access addresses of the vector element 4 to the vector element 7 all match at “address E”. In this case, the memory request control unit 210 compresses the eight memory access requests from the vector element 0 to the vector element 7 into two requests of the vector element 3 and the vector element 7, thereby reducing the number of requests from eight. Reduced to 2.

  When reply data is returned to each memory port, the memory request control unit 210 transfers the returned reply data A from the vector element 0 to the vector register for the vector element 3 from the stored compression information. In addition, the reply data E is stored in the vector registers for the vector element 4 to the vector element 7, respectively.

  As shown in FIG. 5, first, the test program generates a test instruction sequence (step S101).

  Next, the test program executes this test instruction sequence on the control means 200 (step S102).

  The test instruction sequence includes a list instruction that can compress a memory access request. Now, a case where a gather instruction which is one of such list instructions is executed will be described with reference to FIG.

  Referring to FIG. 6, in the gather instruction, when all the access addresses A of the vector element 0 to the vector element 3 match and all the access addresses E of the vector element 4 to the vector element 7 match, as described above, the memory access The request is compressed, and the memory request control unit 210 issues only two access requests of the vector element 3 and the vector element 7. These requests are issued to the memory port 0 and the memory port 4, respectively.

  At this time, the memory request control unit 210 increments the value of the list instruction request number counter unit 211-0 corresponding to the memory port 0 and the memory port 4 that issued the request by +1. The value of the list command request counter 211-0 corresponding to another memory port remains the initial value “0”.

Specifically, the memory request valid bit V is “1” at one input of the AND gate 211-1 of the list instruction request counter 211-2 (see FIG. 4) corresponding to each of the memory ports 0 and 4. A certain signal is sent from the control unit 210 to the other input and the list instruction bit L is “1” (indicating that it is a list instruction) at the other input. As a result, an 8-bit counter 211-3 is sent. Is counted up from the initial value “0” to “1”.
On the other hand, a signal having a memory request valid bit V of “0” is sent from the control unit 210 to one input of the AND gate 211-1 in the list command request counter 211-0 corresponding to another port. No count up operation is performed.

  Here, if the memory request is not compressed due to a failure or a design error, three memory requests for the access address A are transmitted to the memory port 0. Therefore, the counter 211-3 is +3. Since it is counted up and its content becomes “3”, it becomes inconsistent with the result of software simulation described later, and an abnormality can be found.

  When the memory request is normally compressed, the memory request control unit 210 thereafter sends the reply data A returned to the memory port 0 from the vector element 0 to the vector register for the vector element 3, and The reply data E returned to the memory port 4 is stored in the vector registers for the vector elements 4 to 7 respectively.

  When the execution of the test instruction sequence is completed in step S102, the test program determines whether the test instruction sequence includes a list instruction for performing a plurality of memory accesses at once (step S103).

  If a list command is included, the process proceeds to step S105.

In step S105, the test program uses the above-described list instruction request number counter value transfer instruction (described with reference to FIG. 7) to set the value stored in the list instruction request number counter block 211 to the software visible register 230. Transport to. Here, the test program connects the value of the counter 211-3 in the list command request counter 211-0 for eight ports from the memory port 0 to the memory port 7 to obtain a 64-bit value, which is the list command. It is stored in one 64-bit software visible register designated by “REG” of the request number counter value transfer instruction.
For example, if only one gather instruction described in FIG. 6 is included in the test instruction sequence as a list instruction, “0100000001000000” (because it becomes longer when written in bits, it is expressed in hexadecimal notation for convenience here). Is transferred to the software visible register 230.
If the compression of the memory access request is not normally performed as described above and three requests are issued to the memory port 0, the value “030000000000000” (hexadecimal notation) is transferred to the software visible register 230. become.

  Next, the test program performs software simulation of the test instruction sequence (step S106). At this time, in addition to the software simulation of the normal test instruction sequence, the test program also performs the software simulation of the operation of the list instruction request counter block 211 (the operation of the list instruction request counter 211-3, etc.). It is stored in the software simulator execution result storage area 320 (in the example of FIG. 6, it is “010000000000000” (hexadecimal number)).

  Next, the test program reads the software simulation result of the list command request counter block stored in step S106 (step S107). The test program then stores the value of the read simulation result and the test command string. The list instruction (here, the gather instruction in FIG. 6) is compared with the value of the software visible register 230 in which the actual hardware execution result is stored (step 108). If these two values match, it is normal, and if they do not match, it can be seen that compression of the memory access request was not performed normally.

  If the list instruction is not included in the test instruction sequence in step S103, the test program performs a normal software simulation of the test instruction sequence that does not include the software simulation of the operation of the list instruction request counter block 211. (Step S104).

  As described above, the information processing apparatus 100 ends the execution of the test program.

  As described above, this embodiment has an effect that it is possible to verify whether or not the compression process of the memory access request in the list instruction is correctly performed.

  The reason is that the actual number of memory access requests issued by the list instruction is counted by the list instruction request counter block on the actual hardware, and the count result is obtained by software simulation of the number of memory access requests of the list instruction. This is because it can be compared with the result of the above, and it can be determined whether or not the compression processing or the like of the memory access request has been correctly performed.

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 20 Control means 21 Memory request control part 22 Vector register 30 Storage means 31 Database storage area 100 Information processing apparatus 200 Control means 210 Memory request control part 211 List instruction request number counter block 211-0 List instruction request number counter part 211-1 AND gate 211-2 selector 211-3 list instruction request number counter 211-4 +1 adder 220 vector register 230 software visible register 300 storage means 310 data storage area 320 software simulator execution result storage area

Claims (6)

Storage means having a plurality of memory ports and storing a plurality of data, wherein the data is accessed via the memory ports;
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. Memory request control means for issuing to the storage means via the port;
The number of memory access requests provided in a one-to-one correspondence with the plurality of memory ports, when the list instruction is issued, and when the memory access request is issued to the corresponding port from the memory request control means A plurality of counter means for counting
Control means for comparing the contents of the plurality of counter means and the result of software simulation of the counter means to determine the presence or absence of a failure related to the list command;
An information processing apparatus including: 2. An information processing apparatus according to claim 1, further comprising register means for concatenating the contents of said plurality of counter means and storing them as one count value. In an information processing apparatus having a plurality of memory ports and storing a plurality of data, and having a storage means for accessing the data via the memory ports,
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. A memory request control step for issuing to the storage means via the port;
A counting step of counting the number of memory access requests for each port when the list instruction is issued and the memory access request is issued to the port in the memory request control step;
A method for verifying a list instruction, comprising: a step of comparing a count result in the counting step with a result of software simulation in the counting step to determine whether there is a fault related to the list instruction. 4. The list instruction verification method according to claim 3 , further comprising a storage step of concatenating the count values counted for each port into one and storing them in a register means. In an information processing apparatus having a plurality of memory ports and storing a plurality of data, and having a storage means for accessing the data via the memory ports,
When a list instruction that performs a plurality of accesses to the storage unit collectively issues a plurality of memory access requests to the same port, the plurality of access requests are compressed into one memory access request. A memory request control process to be issued to the storage means via the port;
A counting process for counting the number of memory access requests for each port when the list instruction is issued and the memory access request is issued to the port by the memory request control process;
For verifying the list instruction, the computer executes a determination process for comparing the counting result of the counting process with the result of the software simulation of the counting process and determining whether there is a fault related to the list instruction. Program. 6. A program according to claim 5 , wherein said computer is caused to execute a storage process of concatenating count values counted for each port into one and storing them in a register means.

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