JP5879585B2 - Display device and driving method thereof - Google Patents

Description

  The present invention relates to a display device that displays an image by current-driving light emitting elements arranged for each pixel and a driving method thereof. The present invention also relates to an electronic device using such a display device. Specifically, the present invention relates to a driving method of a so-called active matrix display device in which an amount of current supplied to a light emitting element such as an organic EL is controlled by an insulated gate field effect transistor provided in each pixel circuit.

  In recent years, development of flat self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device is a device that utilizes the phenomenon of light emission when an electric field is applied to an organic thin film. Since the organic EL device is driven at an applied voltage of 10 V or less, it has low power consumption. In addition, since the organic EL device is a self-luminous element that emits light, it does not require an illumination member and can be easily reduced in weight and thickness. Furthermore, since the response speed of the organic EL device is as high as several μs, an afterimage does not occur when displaying a moving image.

  Among planar self-luminous display devices that use organic EL devices as pixels, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active. Active matrix type flat self-luminous display devices are described in, for example, Patent Documents 1 to 5 below.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  However, in the conventional active matrix type flat self light emitting display device, the threshold voltage and mobility of a transistor (drive transistor) for driving the light emitting element vary due to process variations. In addition, the current / voltage characteristics of the organic EL device change with time. Such variations in the characteristics of the drive transistor and the characteristics of the organic EL device affect the light emission luminance. In order to uniformly control the light emission luminance over the entire screen of the display device, it is necessary to correct the characteristic variation of the drive transistor and the organic EL device described above in each pixel circuit. Conventionally, a display device having such a correction function for each pixel has been proposed.

  In order to stably perform the threshold voltage correction operation and the mobility correction operation of the drive transistor, it is preferable to increase the capacitance value of the capacitor element formed in each pixel as much as possible. The capacitive element is formed of a thin film element like the drive transistor, and the dielectric film of the capacitive element is in the same layer as the gate insulating film of the drive transistor. In order to increase the capacity of the capacitive element, it is necessary to make the dielectric film thin, and the gate insulating film is inevitably thin. For this reason, the withstand voltage between the drain and source of the drive transistor tends to decrease.

  On the other hand, in order to execute the mobility correction operation and the threshold voltage correction operation in each pixel circuit, it is necessary to switch the power supply voltage supplied to each pixel between high and low levels according to a predetermined sequence. In the process of switching the level of the power supply voltage, a large potential difference is generated between the source and drain of the drive transistor, and in some cases, the withstand voltage of the drive transistor may be exceeded. For this reason, conventionally, it has been necessary to ensure a certain level of dielectric strength of the drive transistor, which has hindered the increase in capacity of the capacitive element.

Display device of the present invention consists and the drive unit pixel array unit, image element array portion, the feeding line and the first and second potentials less than this is selectively supplied, the scanning of rows Lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect. Each pixel includes at least a sampling transistor, Ru includes a drive transistor, a light emitting element, and a storage capacitor. The sampling transistor is inserted between the signal line and the storage capacitor, and is configured to write a video signal in accordance with a control signal from a scanning line connected to the control end of the sampling transistor. It is configured to control the drive current to the light emitting element according to the voltage applied to the control terminal, inserted between the power supply line and the storage capacitor is connected to the control terminal of the drive transistor A voltage corresponding to the voltage is applied to the control terminal of the drive transistor. The driving unit supplies a control signal and a video signal according to a predetermined sequence, and drives each pixel by switching the potential of the power supply line, thereby correcting the dependency of the driving current on the threshold voltage of the drive transistor. It is configured to perform a series of operations including a threshold voltage correction operation, a writing operation for writing the signal potential of the video signal to the holding capacitor, and a light emitting operation for causing the light emitting element to emit light according to the signal potential written to the holding capacitor. Has been. When the gate potential of the drive transistor is Vg, the threshold voltage is Vth, and the first potential is Vcc, the first potential in the light emission period is set to satisfy Vg <Vcc + Vth. The threshold voltage correction operation and the writing operation are performed with the second potential supplied to the power supply line, and the sampling transistor is turned off at the end of the writing operation, and then the drive is performed by the current from the power supply line via the drive transistor. The potential of the source / drain on the light emitting element side of the transistor rises, and the potential of the gate of the drive transistor rises accordingly. After the rise, the potential of the power supply line rises from the second potential to the first potential. Is configured to do.

Preferably, the drive unit, the hourly wires are picture element performs a light emitting operation with a first high potential, the pixel is a second high potential hourly wire lower than the first high potential for performing threshold voltage correction operation. Preferably, the levels of the first high potential, the second high potential, and the low potential are set so that the voltage applied between the source and drain of the drive transistor in all the operations of the pixel enters the saturation operation region.
More preferably, the drive unit includes a power supply scanner for controlling the potential of the feed line, the power supply scanner includes a shift register and its output buffer connected to each stage, the shift register sequentially in each stage It generates a cut signal, the output buffer is switched to the low potential of the first or second high-potential and the ground line side of the power line side in accordance with該切Ri signal is arranged between the power supply line and a ground line Applied to the corresponding feeder. In this case, the output buffer, while the first high potential and a second high potential is supplied while switched to the power supply line side, the first low potential and this lower than the second low to the ground line side Correspondingly The voltage is supplied while switching the potential so that the voltage applied between the source and drain of the transistor constituting the output buffer arranged between the power supply line and the ground line does not exceed the withstand voltage. The output buffer switches from the first high potential to the second high potential on the power supply line side, then switches from the first low potential to the second low potential on the ground line side, and switches to the second low potential on the ground line side. After returning to the first low potential, the second high potential is returned to the first high potential on the power line side.
According to the display device driving method of the present invention, a feeding line, a row-shaped scanning line, a column-shaped signal line, and each scanning line to which a first potential and a second potential lower than the first potential are selectively supplied. And each signal line have a pixel array portion having matrix-like pixels arranged at the intersections, and each pixel of the pixel array portion has at least a sampling transistor, a drive transistor, a light emitting element, and a storage capacitor The sampling transistor is inserted between the signal line and the storage capacitor, and is configured to write a video signal in accordance with a control signal from a scanning line connected to a control terminal thereof, and the drive transistor emits light The drive capacitor is inserted between the device and the power supply line, and the drive current to the light emitting device is controlled in accordance with the voltage applied to the control terminal. The storage capacitor is connected to the control terminal of the drive transistor. It is a method of driving a display device configured to apply a voltage corresponding to the holding voltage to the control terminal of the drive transistor. A threshold voltage correction step for setting a voltage corresponding to the threshold voltage of the drive transistor to the holding capacitor, a writing step for writing the signal potential of the video signal to the holding capacitor, and after the sampling transistor is turned off at the end of the writing step Then, the equivalent capacitance of the light emitting element is charged by the current from the feeder line through the drive transistor, thereby raising the potential of the source / drain on the light emitting element side of the drive transistor, and the gate of the drive transistor is adjusted accordingly. A potential raising step for raising the potential, and a light emitting step for causing the light emitting element to emit light in accordance with the signal potential written in the storage capacitor, wherein the gate potential of the drive transistor is Vg, the threshold voltage is Vth, When the potential is Vcc, the first potential in the light emission period is set to satisfy Vg <Vcc + Vth. Thus, the threshold voltage correcting step and the writing step are executed in a state where the second potential is supplied to the power supply line, the processing of the potential raising step is started, and after the rise of the potential of the gate of the drive transistor is finished, The potential is raised from the second potential to the first potential.

  According to the present invention, the high potential applied to the power supply line is switched between the first high potential and the second high potential having different levels according to a predetermined sequence. This prevents an excessive voltage from being applied to the source and drain of the drive transistor in a series of pixel operations. As a result, the withstand voltage between the source and drain of the drive transistor can be lowered as compared with the prior art. In other words, since the gate insulating film of the drive transistor can be thinned, the dielectric film of the storage capacitor is also thinned accordingly, so that the capacity can be increased.

1 is a block diagram showing an overall configuration of a display device according to the present invention. It is a circuit diagram which shows an example of the pixel integrated in the display apparatus shown in FIG. 3 is a reference timing chart for explaining the operation of the display device shown in FIGS. 1 and 2. 3 is a timing chart for explaining the operation of the embodiment of the display device shown in FIGS. 1 and 2. FIG. 3 is a circuit diagram for explaining operations of the display device shown in FIGS. 1 and 2. It is a circuit diagram similarly used for operation | movement description. It is a circuit diagram similarly used for operation | movement description. It is a circuit diagram similarly used for operation | movement description. FIG. 3 is a partial view illustrating a configuration of a power supply scanner included in the display device illustrated in FIGS. 1 and 2. It is a fragmentary figure which shows another example of a power supply scanner similarly. 10 is a timing chart for explaining the operation of the power supply scanner shown in FIG. 9. 11 is a timing chart for explaining the operation of the power supply scanner shown in FIG. 10. 11 is another timing chart for explaining the operation of the power supply scanner shown in FIG. 10. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, the display device includes a pixel array unit 1 and a drive unit that drives the pixel array unit 1. The pixel array section 1 corresponds to a row-shaped scanning line WS, a column-shaped signal line (signal line) SL, a matrix-shaped pixel 2 arranged at a portion where both intersect, and each row of each pixel 2. The power supply line (power supply line) VL is provided. In this example, any one of the three RGB primary colors is assigned to each pixel 2, and color display is possible. However, the present invention is not limited to this, and includes a monochrome display device. The drive unit sequentially supplies a control signal to each scanning line WS to scan the pixels 2 line-sequentially in units of rows, and the first potential and the second potential to each power supply line VL in accordance with the line sequential scanning. And a signal selector (horizontal selector) 3 for supplying a signal potential serving as a drive signal and a reference potential to the column-shaped signal lines SL in accordance with the line sequential scanning. ing.

  FIG. 2 is a circuit diagram showing a specific configuration and connection relationship of the pixel 2 included in the display device shown in FIG. As illustrated, the pixel 2 includes a light emitting element EL represented by an organic EL device, a sampling transistor Tr1, a drive transistor Trd, and a storage capacitor Cs. The control terminal (gate) of the sampling transistor Tr1 is connected to the corresponding scanning line WS, one of the pair of current terminals (source and drain) is connected to the corresponding signal line SL, and the other is connected to the control terminal of the drive transistor Trd. Connect to (Gate G). In the drive transistor Trd, one of a pair of current ends (source S and drain) is connected to the light emitting element EL, and the other is connected to the corresponding power supply line VL. In this example, the drive transistor Trd is an N-channel type, and its drain is connected to the power supply line VL, while the source S is connected to the anode of the light emitting element EL as an output node. The cathode of the light emitting element EL is connected to a predetermined cathode potential Vcath. The storage capacitor Cs is connected between the source S that is one of the current ends of the drive transistor Trd and the gate G that is the control end.

  In such a configuration, the sampling transistor Tr1 is turned on in response to a control signal supplied from the scanning line WS, samples the signal potential supplied from the signal line SL, and holds it in the holding capacitor Cs. The drive transistor Trd is supplied with current from the power supply line VL at the first potential (high potential Vcc), and flows drive current to the light emitting element EL in accordance with the signal potential held in the holding capacitor Cs. The write scanner 4 outputs a control signal having a predetermined pulse width to the control line WS in order to bring the sampling transistor Tr1 into a conductive state in a time zone in which the signal line SL is at the signal potential, and thus the signal potential to the holding capacitor Cs. At the same time, a correction for the mobility μ of the drive transistor Trd is added to the signal potential. Thereafter, the drive transistor Trd supplies a drive current corresponding to the signal potential Vsig written in the storage capacitor Cs to the light emitting element EL, and starts a light emitting operation.

  The pixel circuit 2 has a threshold voltage correction function in addition to the mobility correction function described above. That is, the power supply scanner 6 switches the power supply line VL from the first potential (high potential Vcc) to the second potential (low potential Vss2) at the first timing before the sampling transistor Tr1 samples the signal potential Vsig. Similarly, the write scanner 4 applies the reference potential Vss1 from the signal line SL to the gate G of the drive transistor Trd from the signal line SL by making the sampling transistor Tr1 conductive at the second timing before the sampling transistor Tr1 samples the signal potential Vsig. The source S of Trd is set to the second potential (Vss2). The power supply scanner 6 switches the power supply line VL from the second potential Vss2 to the first potential Vcc at a third timing after the second timing, and holds a voltage corresponding to the threshold voltage Vth of the drive transistor Trd in the holding capacitor Cs. With this threshold voltage correction function, the display device can cancel the influence of the threshold voltage Vth of the drive transistor Trd that varies from pixel to pixel.

  The pixel circuit 2 further has a bootstrap function. That is, the write scanner 4 cancels the application of the control signal to the scanning line WS at the stage where the signal potential Vsig is held in the holding capacitor Cs, and the sampling transistor Tr1 is turned off to connect the gate G of the drive transistor Trd from the signal line SL. By electrically disconnecting, the potential of the gate G is interlocked with the potential fluctuation of the source S of the drive transistor Trd, and the voltage Vgs between the gate G and the source S can be maintained constant.

  As a feature of the present invention, the power supply scanner 6 switches the high potential Vcc applied to the power supply line VL between the first high potential and the second high potential having different levels in accordance with a predetermined sequence, so that a series of pixels 2 In operation, the voltage applied between the source S and drain D of the drive transistor Trd is prevented from exceeding the withstand voltage. In the embodiment shown in FIG. 2, the first high potential corresponds to Vcc, and the second high potential is at a lower level. In this specification, this second high potential is represented by Vcc2. In a specific operation, the power supply scanner 6 sets the power supply line VL to the first high potential Vcc when the pixel 2 performs the light emission operation, and sets the power supply line VL from the first high potential Vcc when the pixel 2 performs the threshold voltage correction operation. The second high potential Vcc2 is also low. In the power supply scanner 6, the voltage applied between the source S and the drain D of the drive transistor Trd is saturated in all operations including the threshold voltage correcting operation, the mobility correcting operation, the signal potential writing operation, and the light emitting operation of the pixel 2. The levels of the first high potential Vcc, the second high potential Vcc2, and the low potential Vss2 are set so as to enter the region.

  FIG. 3 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. However, this timing chart is a reference example, and the potential supplied from the power supply scanner 6 to the power supply line VL is not three levels, but two levels of a high potential Vcc and a low potential Vss2. This timing chart represents a change in the potential of the scanning line WS, a change in the potential of the power supply line VL, and a change in the potential of the signal line SL, with a common time axis. In parallel with these potential changes, the potential changes of the gate G and the source S of the drive transistor Trd are also shown. As shown in the timing chart of FIG. 3, the pixel enters the non-light emission period of the field from the light emission period of the previous field, and then becomes the light emission period of the field. During this non-emission period, a preparation operation, a threshold voltage correction operation, a signal writing operation, a mobility correction operation, and the like are performed.

  In the light emission period of the previous field, the power supply line VL is at the high potential Vcc, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line VL at the high potential Vcc through the light emitting element EL through the drive transistor Trd to the cathode line.

  Subsequently, when the non-light-emission period of the field starts, the power supply line VL is first switched from the high potential Vcc to the low potential Vss2 at timing T1. As a result, the power supply line VL is discharged to Vss2, and the potential of the source S of the drive transistor Trd drops to Vss2. As a result, the anode potential of the light emitting element EL (that is, the source potential of the drive transistor Trd) is in a reverse bias state, so that the drive current does not flow and the light is turned off. Further, the potential of the gate G also drops in conjunction with the potential drop of the source S of the drive transistor.

  Subsequently, at timing T2, the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vss1. Therefore, the potential of the gate G of the drive transistor Trd becomes the reference potential Vss1 of the signal line SL through the conducting sampling transistor Tr1. At this time, the potential of the source S of the drive transistor Trd is at a potential Vss2 that is sufficiently lower than Vss1. In this way, the voltage Vgs between the gate G and the source S of the drive transistor Trd is initialized so as to be larger than the threshold voltage Vth of the drive transistor Trd. A period T1-T3 from the timing T1 to the timing T3 is a preparation period in which the gate G / source S voltage Vgs of the drive transistor Trd is set to Vth or higher in advance.

  Thereafter, at timing T3, the power supply line VL changes from the low potential Vss2 to the high potential Vcc, and the potential of the source S of the drive transistor Trd starts to rise. Eventually, the current is cut off when the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written into the storage capacitor Cs. This is the threshold voltage correction operation. At this time, the cathode potential Vcath is set so that the light emitting element EL is cut off in order to prevent the current from flowing to the storage capacitor Cs and not to the light emitting element EL.

  At timing T4, the scanning line WS returns from the high level to the low level. In other words, the first pulse applied to the scanning line WS is released, and the sampling transistor is turned off. As is clear from the above description, the first pulse is applied to the gate of the sampling transistor Tr1 in order to perform the threshold voltage correction operation.

  Thereafter, the signal line SL is switched from the reference potential Vss1 to the signal potential Vsig. Subsequently, at timing T5, the scanning line WS rises again from the low level to the high level. In other words, the second pulse is applied to the gate of the sampling transistor Tr1. As a result, the sampling transistor Tr1 is turned on again, and the signal potential Vsig is sampled from the signal line SL. Therefore, the potential of the gate G of the drive transistor Trd becomes the signal potential Vsig. Here, since the light emitting element EL is initially in the cut-off state (high impedance state), the current flowing between the drain and the source of the drive transistor Trd flows exclusively into the holding capacitor Cs and the equivalent capacity of the light emitting element EL and starts charging. Thereafter, by the timing T6 when the sampling transistor Tr1 is turned off, the potential of the source S of the drive transistor Trd rises by ΔV. In this way, the signal potential Vsig of the video signal is written to the storage capacitor Cs in a form added to Vth, and the mobility correction voltage ΔV is subtracted from the voltage stored in the storage capacitor Cs. Therefore, the period T5-T6 from the timing T5 to the timing T6 becomes a signal writing period & mobility correction period. In other words, when the second pulse is applied to the scanning line WS, a signal writing operation and a mobility correction operation are performed. The signal writing period & mobility correction period T5-T6 is equal to the pulse width of the second pulse. That is, the pulse width of the second pulse defines the mobility correction period.

  In this way, in the signal writing period T5-T6, the signal voltage is written to Vsig and the correction amount ΔV is adjusted simultaneously. As Vsig increases, the current Ids supplied from the drive transistor Trd increases and the absolute value of ΔV also increases. Therefore, mobility correction is performed according to the light emission luminance level. When Vsig is constant, the absolute value of ΔV increases as the mobility μ of the drive transistor Trd increases. In other words, the larger the mobility μ is, the larger the negative feedback amount ΔV with respect to the storage capacitor Cs is, so that variation in the mobility μ for each pixel can be removed.

  Finally, at timing T6, as described above, the scanning line WS shifts to the low level side, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At the same time, the drain current Ids starts to flow through the light emitting element EL. As a result, the anode potential of the light emitting element EL rises according to the drive current Ids. The increase in the anode potential of the light emitting element EL is none other than the increase in the potential of the source S of the drive transistor Trd. When the potential of the source S of the drive transistor Trd rises, the potential of the gate G of the drive transistor Trd also rises in conjunction with the bootstrap operation of the storage capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd is kept constant during the light emission period. The value of Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ. The drive transistor Trd operates in the saturation region. That is, the drive transistor Trd supplies a drive current Ids according to the gate G / source S voltage Vgs. The value of Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ.

  In the reference example shown in FIG. 3, the write scanner 4 outputs the control signal pulse twice within 1H. The pixel 2 performs threshold voltage correction in response to the first pulse, and simultaneously performs a signal potential writing operation and a mobility correction operation in response to the second pulse. On the other hand, the power supply voltage supplied to the power supply line DS by the power supply scanner 6 uses two values of the high potential Vcc and the low potential Vss2, and when starting the threshold voltage correction operation, the source S of the drive transistor Trd is low as shown in the timing chart. The potential becomes Vss2, and the drain becomes the high potential Vcc. In terms of operation, the potential difference between the high potential Vcc and the low potential Vss2 reaches 15V or more.

  On the other hand, as the definition of the panel increases, the area per pixel decreases, and the capacitance value of the storage capacitor Cs per pixel decreases accordingly. As the capacitance value of the storage capacitor Cs decreases, the mobility correction time decreases in proportion to this, so the margin for variations in the mobility correction time decreases, and stripes along the scanning line occur on the screen. End up.

  As a countermeasure, it is conceivable to increase the capacity by thinning the dielectric film of the storage capacitor. In general, a storage capacitor and a transistor constituting a pixel circuit are formed simultaneously using a thin film process. The dielectric film of the storage capacitor Cs and the gate insulating film of the transistor are in the same layer. If the dielectric film is made thin in order to increase the storage capacity Cs, the gate insulating film of the drive transistor must inevitably be made thin, and the breakdown voltage of the drive transistor is lowered. In particular, the source / drain breakdown voltage of the drive transistor Trd is reduced to about 12V. Since the display device shown in FIG. 1 and FIG. 2 performs a complex correction operation with two transistors, the power supply voltage supplied to the pixel is alternately switched between a high potential and a low potential, and between the source and drain of the drive transistor A voltage of 15 V or more is applied to the worst case. Therefore, if the storage capacitor is increased, there is a risk that a voltage will be applied beyond the allowable value of the source / drain breakdown voltage of the drive transistor Trd. In this state, the gate insulating film of the drive transistor Trd is made thinner and the storage capacitor Cs. It is difficult to increase the capacity.

  FIG. 4 is a timing chart for explaining the operation of the display device shown in FIGS. This timing chart represents an embodiment of the present invention, and the same notation as the timing chart of the reference example shown in FIG. 3 is adopted for easy understanding. As shown in the drawing, in this embodiment, the voltage applied to the power supply line VL is changed from the binary value (Vcc, Vss2) of the reference example to the ternary value (Vcc, Vcc2, Vss2). The newly added potential Vcc2 is an intermediate potential between the high potential Vcc and the low potential Vss2 used in the reference example. During the period in which the newly added intermediate potential Vcc2 is applied to the power supply line VL, the threshold voltage correction operation, the signal potential writing operation, and the mobility correction operation are performed, and then the sampling transistor Tr1 is turned off to enter the light emission period. The rear feed line VL is pulled up to the high potential Vcc. As a result, the withstand voltage applied between the source and drain of the drive transistor Trd is set to 12 V or less, and the gate insulating film can be made thinner.

  As shown in the timing chart of FIG. 4, each pixel enters a non-light emission period from timing T1, and switches to a light emission period after timing T6. In the non-light emitting period T1-T6, the power supply line VL is at the low potential Vss2 in the first half. In the latter half of the threshold voltage correction period T3-T4 and the signal potential writing period T5-T6, the power supply line VL rises to the intermediate potential Vcc2. Thereafter, when the light emission period starts, the power supply line VL further rises to the high potential Vcc. The potential of the power supply line VL is applied to the drain D side of the drive transistor Trd.

  On the other hand, when attention is paid to the source potential of the drive transistor Trd, it becomes the lowest in the non-light emitting period T1-T3. At this time, since the power supply line VL is also at the low potential Vss2, there is no possibility of exceeding the withstand voltage. Subsequently, in the correction period T3-T6, the source potential rises slightly, but the drain side switches to a high potential. At this time, if the high potential Vcc is used instead of the intermediate potential Vcc2 as in the reference example, the withstand voltage of the drive transistor may be exceeded. Therefore, in the present invention, the potential of the feeder line VL is set to the intermediate potential Vcc2. Thereafter, when the light emission period starts, the power supply line VL becomes the high potential Vcc. At this time, the source potential of the drive transistor is also greatly increased by the bootstrap operation. Therefore, there is no possibility that the drain-source voltage of the drive transistor Trd exceeds the withstand voltage.

  As is apparent from the above description, the period during which the source / drain voltage of the drive transistor Trd has the highest risk of exceeding the withstand voltage is the threshold voltage correction period or the mobility correction period. Therefore, during the period during which these correction operations are performed, the power supply line VL is suppressed to the intermediate potential Vcc2, thereby preventing an excessive voltage from being applied between the source / drain of the drive transistor beyond the withstand voltage. In other words, the withstand voltage of the drive transistor Trd can be made lower than that of the reference example, and accordingly, the gate insulating film can be made thinner and the holding capacity can be increased accordingly.

  The operation of the display device according to the present invention will be described in detail with reference to FIGS. FIG. 5 shows the potential state of the pixel in the preparation period T2-T3. In this preparation period, the signal line SL is set to the reference potential Vss1, and the sampling transistor Tr1 is turned on. As a result, the reference potential Vss1 is written to the gate G of the drive transistor Trd. On the other hand, the power supply line is at the low potential Vss2, which is a value lower than the Vth by Vth1, so that the drive transistor Trd is in the on state and its source potential is also Vss2. In this way, in the preparation period T2-T3, the gate G and the source S of the drive transistor Trd are initialized to Vss1 and Vss2, respectively. At this time, the drain and source of the drive transistor Trd are both Vss2, and the potential difference is 0V.

  FIG. 6 shows the potential state of the pixel in the threshold voltage correction period T3-T4. In this threshold voltage correction period, the power supply voltage is raised to Vcc2 and the threshold voltage correction operation is executed. A drain current Ids flows through the drive transistor Trd in proportion to Vgs, and the source potential rises until the drive transistor Trd is cut off. Here, in the reference example, the potential difference between the high potential Vcc and the low potential Vss2 is 15 V or more, but in this embodiment, the potential difference between Vcc2 and Vss2 is set to be 12 V or less. Here, since the gate potential Vss1 of the drive transistor Trd is slightly larger than Vss2 + Vth as described above, the drive transistor Trd operates in a saturation region with respect to Vcc2.

  FIG. 7 shows the potential state of the pixel in the mobility correction period T5-T6. When the threshold voltage correction operation described above is completed, the sampling transistor Tr1 is once turned off, the signal line SL is rewritten to the signal potential Vsig, and then the sampling transistor Tr1 is turned on again. Thus, the mobility correction operation is performed by negatively feeding back the drain current Ids to the storage capacitor Cs while writing the signal potential Vsig to the gate G of the drive transistor Trd. At this time, the power supply voltage remains at the intermediate Vcc2. Generally, the potential of Vsig is set to about Vss1 + 5V due to the voltage setting of the signal selector. Thus, Vcc2 = Vss2 + 12 = Vss1−Vth + 12≈Vss1 + 10 (where Vth is 2V), and Vcc2> Vsig. Therefore, during this mobility correction operation, the drive transistor Trd always operates in the saturation region. In order to accurately perform the mobility correction operation, the drive transistor Trd needs to operate in the saturation region, and the present invention performs an accurate operation.

  FIG. 8 shows the potential state of the pixel in the light emission period. After the sampling transistor Tr1 is turned off to complete the mobility correction operation, the pixel power supply voltage is raised to Vcc. When the sampling transistor Tr1 is turned off, the impedance of the gate G of the drive transistor Trd increases, so the anode potential of the light emitting element EL (that is, the source potential of the drive transistor Trd) rises depending on the drain current Ids, and accordingly The potential of the gate G is also bootstrapped. Here, in the case of white display, the source potential rises by 5 V or more. Therefore, if the power supply voltage remains at the middle Vcc2, Vg (gate potential)> Vcc2 + Vth, and the drive transistor Trd may be linearly driven. With linear drive, image quality uniformity is degraded. Therefore, in the present invention, the power supply voltage Vcc is set to satisfy Vg <Vcc + Vth during the light emission period. As a result, the drive transistor Trd operates in the saturation region during the light emission period, and high uniformity can be obtained. However, the high potential Vcc is set so that the source-drain voltage of the drive transistor Trd is within 12V.

  As described above, according to the present invention, the source / drain voltage of the drive transistor Trd can be suppressed to 12 V or less of the allowable withstand voltage in all operations, and a process such as thinning the gate insulating film can be applied. Is possible.

  FIG. 9 is a partial circuit diagram illustrating the configuration of the power supply scanner included in the display device illustrated in FIGS. 1 and 2. The power scanner includes a shift register and an output buffer connected to each stage. The shift register sequentially outputs pulses for each stage in synchronization with line sequential scanning. An output buffer is provided for each stage of the shift register. FIG. 9 shows an output buffer for one stage. This output buffer is composed of an inverter arranged between the power supply voltage line and the GND voltage line. This inverter is composed of a pair of P-channel transistor TrP and N-channel transistor TrN, the input side corresponding to each stage of the shift register, and the output side connected to the corresponding feeder.

  The power supply voltage line is supplied with a power supply pulse that changes to two levels of Vcc and Vcc2 from an external pulse power supply. The GND ground line is fixed at Vss2. When the input signal is low, the inverter turns on the P-channel transistor TrP and outputs the potential of Vcc or Vcc2 supplied to the power supply voltage line. On the other hand, when the input signal becomes high level, the N-channel transistor TrN becomes conductive and supplies the low potential Vss2 to the output-side power supply line. In this way, the first high potential Vcc, the second high potential Vcc2, and the low potential Vss2 are supplied to the output side in a predetermined sequence according to the switching timing of the low level and the high level of the input signal.

  FIG. 10 shows a modification of the output buffer shown in FIG. Corresponding parts are given corresponding reference numbers for ease of understanding. The difference is that the first low potential Vss3 and the second low potential Vss2 lower than the first low potential Vss2 are supplied from an external pulse power supply to the GND voltage line (ground line) of the inverter constituting the output buffer. In this way, the high potential on the power supply voltage line side is switched between Vcc and Vcc2, and at the same time, the low potential on the GND voltage line side is switched between Vss3 and Vss2, so that the transistors TrP and TrN constituting the output buffer are connected between the source and drain. The applied voltage does not exceed the withstand voltage. In this way, the transistor on the pixel array side and the transistor of the power supply scanner included in the peripheral driver can be integrated and formed by the same thin film process.

  FIG. 11 is a timing chart for explaining the operation of the output buffer shown in FIG. As described above, the power supply voltage is switched between Vcc2 and Vcc according to a predetermined sequence. The inverter constituting the output buffer operates in response to the input pulse, selects Vcc or Vcc2 on the power supply voltage side and Vss2 on the ground line side as appropriate, and supplies it as an output pulse to the corresponding feeder line. As shown in the figure, the power supply voltage pulse and the input pulse are phase-adjusted in a predetermined relationship. As a result, the output pulse becomes the low potential Vss2 in the non-light emission period, and becomes an intermediate Vcc2 in the threshold voltage correction period and the signal writing period. In the light emission period, the potential is sequentially switched to the high potential Vcc.

  FIG. 12 is a timing chart for explaining the operation of the output buffer shown in FIG. In order to facilitate understanding, the same notation as the timing chart shown in FIG. 11 is adopted. As described above, the power supply voltage is switched between Vcc2 and Vcc. In accordance with this, the GND voltage (ground voltage) is switched between Vss2 and Vss3. Specifically, after switching from the first high potential Vcc2 to the second high potential Vcc2 on the power supply line side, the first low potential Vss3 is switched to the second low potential Vss2 on the ground line side, and the first low potential Vss2 is switched on the ground line side. 2 After returning from the low potential Vss2 to the first low potential Vss3, the second high potential Vcc2 is returned to the first high potential Vcc on the power supply line side. Such potential setting prevents excessive voltage from being applied between the source and drain of the P-channel transistor and N-channel transistor constituting the inverter.

  FIG. 13 is a timing chart for explaining the operation of the output buffer shown in FIG. In order to facilitate understanding, the same notation as the timing chart shown in FIG. 12 is adopted. The difference is that the rising timing of the input pulse is shifted forward compared to the embodiment of FIG. Even with this setting, it is possible to prevent an excessive voltage from being applied between the source and drain of the P-channel transistor and N-channel transistor constituting the inverter.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all fields which display the drive signal generated in the inside as an image or a picture. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 16 shows a television to which the present invention is applied, which includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 17 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a back view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 18 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when characters and the like are input, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 19 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 20 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

  DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel, 3 ... Horizontal selector, 4 ... Write scanner, 6 ... Power supply scanner, Tr1 ... Sampling transistor, Trd ... Drive transistor, Cs ... Retention capacitor, EL ... Light emitting element, WS ... Scanning line, VL ... Power supply line, SL ... Signal line

Claims (13)

It consists of a pixel array part and a drive part,
The pixel array unit includes a power supply line, a row-shaped scanning line, a column-shaped signal line, and each scanning line and each signal line to which a first potential and a second potential lower than the first potential are selectively supplied. With matrix-like pixels arranged at the intersection of
Each pixel of the pixel array unit includes at least a sampling transistor, a drive transistor, a light emitting element, and a storage capacitor,
The sampling transistor is inserted between the signal line and the storage capacitor, and is configured to write a video signal in accordance with a control signal from the scanning line connected to a control end of the sampling transistor,
The drive transistor is inserted between the light emitting element and the power supply line, and is configured to control a drive current to the light emitting element according to a voltage applied to a control terminal thereof.
The storage capacitor is connected to the control terminal of the drive transistor, and is configured to apply a voltage corresponding to the storage voltage to the control terminal of the drive transistor,
The driving unit supplies the control signal and the video signal in accordance with a predetermined sequence, and drives each pixel by switching the potential of the power supply line, so that the driving current depends on the threshold voltage of the drive transistor. A threshold voltage correcting operation for correcting the characteristics, a writing operation for writing the signal potential of the video signal to the holding capacitor, and a light emitting operation for causing the light emitting element to emit light according to the signal potential written to the holding capacitor. Configured to perform a series of operations including
When the gate potential of the drive transistor is Vg, the threshold voltage is Vth, and the first potential is Vcc, the first potential in the light emission period is set to satisfy Vg <Vcc + Vth ,
The drive unit performs the threshold voltage correction operation and the write operation in a state where a second potential is supplied to the power supply line,
Since the sampling transistor is turned off at the end of the write operation, the current from the power supply line through the drive transistor increases the potential of the source / drain on the light emitting element side of the drive transistor. The display device is configured such that the potential of the gate of the drive transistor rises, and the potential of the feeder line rises from the second potential to the first potential after the end of the rise.   2. The drive unit according to claim 1, wherein the drive unit is configured to supply a low potential lower than either the first potential or the second potential to the power supply line in the extinction period after the end of the light emission period. The display device described. The potential difference between the first potential and the low potential is set to 15V or more,
The display device according to claim 2, wherein the second potential is set so that a voltage applied to a source and a drain of the drive transistor does not exceed 12 V in a series of operations of the pixels.   4. The display device according to claim 1, wherein a voltage applied to a source and a drain of the drive transistor does not exceed a withstand voltage in a series of operations of the pixel. 5.   The driving unit sets a first potential level, a second potential level, and a low potential level so that a voltage applied between the source and drain of the drive transistor enters a saturation operation region in all operations of the pixel. The display device according to claim 2, configured as described above. The drive unit includes a power scanner that controls the potential of the power supply line,
The power scanner includes a shift register and an output buffer connected to each stage thereof.
The shift register sequentially generates a switching signal for each stage,
The output buffer is arranged between the power supply line and the ground line, and switches the first potential on the power supply line side or the second potential and the low potential on the ground line side in accordance with the switching signal, and supplies the corresponding power supply. The display device according to claim 2, wherein the display device is configured to be applied to an electric wire. The output buffer is supplied while the first potential and the second potential are switched to the power supply line side, while the first low potential and the second low potential lower than the first low potential are correspondingly supplied to the ground line side. It is supplied while switching,
The display device according to claim 6, wherein a voltage applied between a source and a drain of a transistor constituting the output buffer disposed between a power supply line and a ground line is configured not to exceed a withstand voltage.   The output buffer switches from the first potential to the second potential on the power supply line side, and then switches from the first low potential to the second low potential on the ground line side, and from the second low potential on the ground line side. 8. The display device according to claim 7, wherein the display device is configured to return from the second potential to the first potential on the power supply line side after returning to the first low potential. A power supply line to which a first potential and a second potential lower than the first potential are selectively supplied, a row-shaped scanning line, a column-shaped signal line, and a portion where each scanning line and each signal line cross each other It has a pixel array unit comprising arranged matrix pixels,
Each pixel of the pixel array unit includes at least a sampling transistor, a drive transistor, a light emitting element, and a storage capacitor,
The sampling transistor is inserted between the signal line and the storage capacitor, and is configured to write a video signal in accordance with a control signal from the scanning line connected to a control end of the sampling transistor,
The drive transistor is inserted between the light emitting element and the power supply line, and is configured to control a drive current to the light emitting element according to a voltage applied to a control terminal thereof.
The storage capacitor is connected to the control terminal of the drive transistor, and is a method for driving a display device configured to apply a voltage corresponding to the storage voltage to the control terminal of the drive transistor,
A threshold voltage correction step of setting a voltage corresponding to the threshold voltage of the drive transistor in the storage capacitor;
A writing step of writing the signal potential of the video signal to the storage capacitor;
The sampling transistor is turned off at the end of the writing step, and then the equivalent capacitance of the light emitting element is charged by the current through the drive transistor from the power supply line, whereby the light emission of the drive transistor A potential increasing step of increasing the potential of the source / drain on the element side and increasing the potential of the gate of the drive transistor in accordance with this,
A light emitting step of causing the light emitting element to emit light according to a signal potential written in the storage capacitor,
When the gate potential of the drive transistor is Vg, the threshold voltage is Vth, and the first potential is Vcc, the first potential in the light emission period is set to satisfy Vg <Vcc + Vth ,
The threshold voltage correcting step and the writing step are executed in a state where a second potential is supplied to the power supply line,
A display device driving method in which the potential of the power supply line is increased from a second potential to a first potential after the processing of the potential increasing step is started and the increase of the potential of the gate of the drive transistor is completed.   The method for driving a display device according to claim 9, wherein a low potential lower than both the first potential and the second potential is supplied to the power supply line in the extinction period after the light emission period ends. The potential difference between the first potential and the low potential is set to 15V or more,
11. The display device driving method according to claim 10, wherein the second potential is set so that a voltage applied to a source and a drain of the drive transistor does not exceed 12 V in a series of operations of the pixels.   12. The display device driving method according to claim 9, wherein driving is performed so that a voltage applied to a source and a drain of the drive transistor does not exceed a withstand voltage in a series of operations of the pixels.   11. The first potential, the second potential, and the low potential level are set so that a voltage applied between the source and drain of the drive transistor in all the operations of the pixel enters a saturation operation region. Item 13. A display device driving method according to any one of Items 12 to 12.

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