JP5872959B2 - Differential amplifier and semiconductor device - Google Patents

Description

  The present invention relates to a differential amplifier, and more particularly to a differential amplifier that amplifies an input signal in the form of a differential signal to obtain an output signal in the form of a differential signal, and a semiconductor device in which such a differential amplifier is formed.

  As a differential amplifier, a differential pair in which the current generated by the current source is divided by the magnitude ratio of the first and second input signals and respectively sent to the first and second lines, and the first and second lines respectively. There has been proposed a circuit including first and second current mirror circuits for flowing the same current as the flowing current through first and second output load resistors, respectively (see, for example, FIG. 19 of Patent Document 1). ).

  The gain of such a differential amplifier is determined by the product of the mutual conductance of a MOS (Metal Oxide Semiconductor) transistor serving as the differential pair and the resistance value of the output load resistor. Here, when such a differential amplifier is constructed with a semiconductor integrated chip, the characteristics of each element vary with variations in the manufacturing process, temperature, and power supply voltage. In particular, in MOS transistors and output load resistors having different structures, device characteristics fluctuate in different directions and sizes. Therefore, since there is no correlation in the degree of variation between the mutual conductance of the MOS transistor and the resistance value of the output load resistance, the gain of the differential amplifier determined by the product of the two varies depending on the manufacturing process, temperature, and power supply voltage. As a result, there was a problem that it varied greatly. Furthermore, when a resistance element such as the output load resistor described above is formed of a semiconductor integrated chip, the area corresponding to the resistance value is occupied, so that there is a problem that the device scale of the entire differential amplifier becomes large. .

JP 2011-199888 A

  An object of the present invention is to provide a differential amplifier capable of reducing the scale of the device and suppressing gain variations, and a semiconductor device in which the differential amplifier is formed.

A differential amplifier according to the present invention is a differential amplifier that amplifies first and second input signals in the form of a differential signal to generate first and second output signals in the form of a differential signal, each having a source terminal Are connected in common and the first and second transistors to which the first and second input signals are respectively supplied to the respective gate terminals, and the first and second transistors connected to the source terminals of the first and second transistors, respectively. 1 current source, a first current mirror section for flowing a first output current corresponding to the current flowing through the first transistor to the first output line, and a second output current corresponding to the current flowing through the second transistor as a second A second current mirror that flows through the output line; a first output load that outputs a voltage on the first output line as the first output signal; and a voltage on the second output line as the second output signal. Output And a second output load unit, and a second current source connected in parallel to the first output load unit, and a third current source connected in parallel to said second output load unit, wherein the first The output load unit includes a third transistor having the same conductivity type as the first transistor, the gate terminal and the drain terminal of which are both connected to the first output line, and the second output load unit includes the gate terminal and the drain terminal. Includes a fourth transistor of the same conductivity type as that of the second transistor, both connected to the second output line.

Further, a semiconductor device according to the present invention includes a limiter that limits an upper limit and a lower limit of an amplitude by sequentially amplifying the first and second received signals in a differential signal form with a multistage differential amplifier connected in series, A received signal strength detection circuit that obtains a received signal strength detection signal that represents the signal strength of the received signal in a logarithmic value based on the first and second amplified signals in the differential signal form output from each of the multi-stage differential amplifiers; Each of the differential amplifiers includes a first terminal and a second terminal having a source terminal commonly connected to each other and a first signal and a second signal in a differential signal form supplied to the respective gate terminals. A second transistor, a first current source connected to a source terminal of each of the first and second transistors, and a first output current corresponding to a current flowing through the first transistor, to the first output line. A first current mirror unit; a second current mirror unit configured to pass a second output current corresponding to a current flowing through the second transistor to a second output line; and a voltage on the first output line is output as the first output signal. A second output load unit that outputs a voltage on the second output line as the second output signal, a second current source connected in parallel to the first output load unit, A third current source connected in parallel to the second output load section , wherein the first output load section has both a gate terminal and a drain terminal connected to the first output line. The second output load unit includes a fourth transistor having the same conductivity type as that of the second transistor, the gate terminal and the drain terminal of which are both connected to the second output line. Including .

  In the differential amplifier according to the present invention, the first and second output currents corresponding to the currents flowing through the first and second transistors serving as the differential input section are caused to flow through the first and second output lines, respectively. The first and second output signals in the form of differential signals are generated by converting the second output current into a voltage at the first and second output load units as described below. That is, as the first output load, a third transistor having both the gate terminal and the drain terminal connected to the first output line and having the same conductivity type as the first transistor is provided, and the gate terminal and the drain are provided as the second output load unit. Both terminals are connected to the second output line, and a fourth transistor having the same conductivity type as the second transistor is provided.

  According to such a configuration, the first to fourth transistors can all be constructed of transistors of the same conductivity type (p channel or n channel). The gain of the differential amplifier is determined by the ratio of the mutual conductance of the first and second transistors responsible for the differential input section and the mutual conductance of the third and fourth transistors responsible for the output load. Therefore, even if the mutual conductance of the first to fourth transistors varies due to variations in manufacturing, or variations in temperature and power supply voltage, the mutual conductances of the first and second transistors that bear the differential input section Since the ratio of the third and fourth transistors carrying the output load to the mutual conductance is substantially constant, variation in gain is suppressed.

  Furthermore, according to the differential amplifier of the present invention, since all elements including the current source can be constructed by MOS type transistors, the area occupied by the semiconductor chip is relatively large, such as a resistor or a capacitor. It is possible to reduce the scale as compared with those including elements.

1 is a circuit diagram showing a first embodiment as a differential amplifier according to the present invention; FIG. FIG. 6 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 1. It is a circuit diagram which shows the 2nd Example as a differential amplifier based on this invention. FIG. 4 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 3. It is a circuit diagram which shows the 3rd Example as a differential amplifier based on this invention. FIG. 6 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 5. It is a circuit diagram which shows the 4th Example as a differential amplifier based on this invention. FIG. 8 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 7. FIG. 10 is a circuit diagram showing a fifth embodiment as a differential amplifier according to the present invention. FIG. 10 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 9. It is a circuit diagram which shows the 6th Example as a differential amplifier based on this invention. FIG. 12 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 11. It is a block diagram which shows schematic structure of the radio | wireless communication apparatus containing the differential amplifier which concerns on this invention. It is a circuit diagram which shows the internal structure of the limiter 6 and the RSSI circuit 8 which are shown in FIG.

In the differential amplifier according to the present invention, the first and second input signals (V _IP , V _IN ) in the form of differential signals are supplied to the respective gate terminals and the source terminals are commonly connected to each other. And the second transistor (11, 12, 21, 22) and the first current source (19, 29) connected to the source terminal of each of the first and second transistors, the following first and A second current mirror unit and an output load unit are included. The first current mirror unit (CM1) flows a first output current corresponding to the current flowing through the first transistor (11, 21) to the first output line (L _OP ). The second current mirror unit (CM2) flows a second output current corresponding to the current flowing through the second transistor (12, 22) to the second output line (L _ON ). The first output load unit uses a voltage on the first output line as a first output signal (V _OP ), and the second output load unit uses a voltage on the second output line as a second output signal (V _ON ) as a differential signal form. To output. At this time, the first output load section includes a third transistor (13, 23) having both a gate terminal and a drain terminal connected to the first output line and having the same conductivity type as the first transistor, and a second output. The load section includes fourth transistors (14, 24) having both gate terminals and drain terminals connected to the second output line and having the same conductivity type as the second transistors.

  FIG. 1 is a circuit diagram showing a circuit as a first embodiment of a differential amplifier 100 according to the present invention.

  A differential amplifier 100 shown in FIG. 1 includes n-channel MOS (Metal Oxide Semiconductor) transistors 11 to 14, p-channel MOS transistors 15 to 18, and a current source 19. The transistors 11 and 12 serve as a differential input section as the differential amplifier 100, and the transistor 13 and the transistor 12 having the same conductivity type as the transistor 11 serve as an output load. The transistors 15 and 16 serve as the first current mirror unit CM1, and the transistors 17 and 18 serve as the second current mirror unit CM2.

A non-inverted input signal _VIP is supplied to the gate terminal of the transistor 11 serving as the differential input unit, and its source terminal is connected to one end of the current source 19 and the source terminal of the transistor 12. The drain terminal of the transistor 11 is connected to the drain terminal of the transistor 15 and the gate terminals of the transistors 15 and 16 via a line L1. A power supply voltage VDD is applied to the source terminals of the transistors 15 and 16 as the first power supply voltage on the high potential side. The drain terminal of the transistor 16 is connected to the drain terminal and the gate terminal of the transistor 13 via the first output line _LOP . That is, the transistor 13 as the output load is in a diode-connected state. The source terminal of the transistor 13 is connected to the other end of the current source 19 and the source terminal of the transistor 14. A power supply voltage VSS is applied to the other end of the current source 19 and the source terminals of the transistors 13 and 14 as a second power supply voltage on the low potential side lower than the first power supply voltage. With this configuration, the voltage on the output line L _OP is outputted as a non-inverted output signal V _OP of the differential amplifier 100.

An inverted input signal V _IN is supplied to the gate terminal of the transistor 12 serving as the differential input unit, and its source terminal is connected to one end of the current source 19 and the source terminal of the transistor 11. That is, the source terminals of the transistors 11 and 12 that bear the differential input section are connected in common. The drain terminal of the transistor 12 is connected to the drain terminal of the transistor 17 and the gate terminals of the transistors 17 and 18 via a line L2. The power supply voltage VDD is applied to the source terminals of the transistors 17 and 18. The drain terminal of the transistor 18 is connected to the drain terminal and the gate terminal of the transistor 14 via the second output line L _ON . That is, the transistor 14 as the output load is in a diode-connected state. With this configuration, the voltage on the output line L _ON is output as the inverted output signal V _ON of the differential amplifier 100.

  Hereinafter, the operation of the differential amplifier 100 shown in FIG. 1 will be described.

The transistors 11 and 12 as the differential input sections flow currents I ₁ and I ₂ corresponding to the voltages of the non-inverted input signal _VIP and the inverted input signal V _IN input to the lines L1 and L2, respectively. Note that the total current of the current I ₁ and the current I ₂ is the current I ₀ generated by the current source 19. The current mirror portion CM1 has a first output current corresponding to the current I ₁ flowing in the line L1, and sends to the transistor 13 as an output load via the output line L _OP. As a result, a non-inverted output signal V _OP having a voltage corresponding to the current I ₁ is generated on the output line L _OP . On the other hand, the current mirror portion CM2 has a second output current corresponding to the current I ₂ flowing in the line L2, is sent to the transistor 14 as an output load via the output line L _ON. As a result, an inverted output signal V _ON having a voltage corresponding to the current I ₂ is generated on the output line L _ON .

The operation described above, the differential amplifier 100, first the first and second input signal (V _IP, V _IN) voltage, following a differential signal form amplified by a gain A _V of the differential signal form 1 And a second output signal (V _OP , V _ON ).
A _V = g _m / g _mls
g _m : mutual conductance of differential input section (transistors 11 and 12) g _mls : mutual conductance of output load (transistors 13 and 14)

That is, the gain A _V of the differential amplifier 100 is identical in structure to each other, that is determined by the transconductance ratio of transistors 11 to 14 are MOS transistors all having the same conductivity type (n-channel type).

  At this time, for transistors having the same structure, the directionality (increase or decrease tendency) of the mutual conductances and the amount of the dispersion can be made uniform by arrangement in the semiconductor chip. .

Therefore, according to the differential amplifier 100 shown in FIG. 1, the differential input section (transistors 11 and 12) and the output load (transistors 13 and 14) are affected by manufacturing variations or temperature and power supply voltage fluctuations. even variations occur in the transconductance, gain a _V of the differential amplifier 100 to determine a ratio of the two, it is possible to suppress the variation of gain a _V.

  Further, according to the differential amplifier 100 shown in FIG. 1, since all elements including the current source 19 can be constructed by MOS type transistors, the area occupied by the semiconductor chip such as a resistor or a capacitor is relatively large. Therefore, it is possible to reduce the size of the device as compared with the device including the element.

  In the above-described embodiment, the transistors 11 to 14 as the differential input section and the output load are all n-channel MOS type. However, all of them may be constructed by p-channel MOS type transistors.

  FIG. 2 is a circuit diagram showing a modification of the differential amplifier 100 shown in FIG. 1 made in view of such points.

  In FIG. 2, p-channel MOS transistors 21 and 22 carry a differential input section as the differential amplifier 100, and have the same conductivity type as the transistor 23 and transistor 22 (p-channel type). The p-channel type transistor 24 carries an output load. The transistors 25 and 26 serve as the first current mirror unit CM1, and the transistors 27 and 28 serve as the second current mirror unit CM2.

A non-inverted input signal _VIP is supplied to the gate terminal of the transistor 21 serving as the differential input unit, and its source terminal is connected to one end of the current source 29 and the source terminal of the transistor 22. The drain terminal of the transistor 21 is connected to the drain terminal of the transistor 25 and the gate terminals of the transistors 25 and 26 via a line L1. A power supply voltage VSS is applied to the source terminals of the transistors 25 and 26 as the second power supply voltage on the low potential side. The drain terminal of the transistor 26 is connected to the drain terminal and the gate terminal of the transistor 23 via the first output line _LOP . That is, the transistor 23 as the output load is in a diode-connected state. The source terminal of the transistor 23 is connected to the other end of the current source 29 and the source terminal of the transistor 24. The power supply voltage VDD is applied to the other end of the current source 29 and the source terminals of the transistors 23 and 24 as the first power supply voltage on the high potential side higher than the second power supply voltage. With this configuration, the voltage on the output line L _OP is outputted as a non-inverted output signal V _OP of the differential amplifier 100.

An inverted input signal V _IN is supplied to the gate terminal of the transistor 22 serving as the differential input section, and its source terminal is connected to one end of the current source 29 and the source terminal of the transistor 21. That is, the source terminals of the transistors 21 and 22 that bear the differential input section are connected in common. The drain terminal of the transistor 22 is connected to the drain terminal of the transistor 27 and the gate terminals of the transistors 27 and 28 via a line L2. The power supply voltage VSS described above is applied to the source terminals of the transistors 27 and 28. The drain terminal of the transistor 28 is connected to the drain terminal and the gate terminal of the transistor 24 via the second output line L _ON . That is, the transistor 24 as an output load is in a diode-connected state. With this configuration, the voltage on the output line L _ON is output as the inverted output signal V _ON of the differential amplifier 100.

In short, in the differential amplifier according to the first embodiment of the present invention, the source terminals are commonly connected to each other, and the first and second input signals (V _IP , V _IN ) in the form of differential signals are connected to the respective gate terminals. Together with the first and second transistors (11, 12, 21, 22) to be supplied respectively, and the first current sources (19, 29) connected to the source terminals of the first and second transistors, respectively, It has a 1st and 2nd current mirror part, and a 1st and 2nd output load part. That is, the first current mirror unit (CM1) flows the first output current corresponding to the current flowing through the first transistor (11, 21) to the first output line (L _OP ). The second current mirror unit (CM2) flows a second output current corresponding to the current flowing through the second transistor (12, 22) to the second output line (L _ON ). The first output load unit uses the voltage on the first output line as the first output signal, and the second output load unit uses the voltage on the second output line as the second output signal. The differential form signals (V _OP , V _ON ) Output as. At this time, the first output load unit includes a third transistor (13, 23) having both a gate terminal and a drain terminal connected to the first output line, and the second load unit has both a gate terminal and a drain terminal. A fourth transistor (14, 24) connected to the second output line is included.

  According to such a differential amplifier, it is possible to construct all of the first to fourth transistors described above with transistors of the same conductivity type channel (p-channel or n-channel). Further, the gain of this differential amplifier is determined by the ratio of the mutual conductance of the first and second transistors responsible for the differential input section and the mutual conductance of the third and fourth transistors responsible for the output load. Therefore, even if the mutual conductance of the first to fourth transistors varies due to variations in manufacturing, or variations in temperature and power supply voltage, the mutual conductances of the first and second transistors that bear the differential input section Since the ratio of the third and fourth transistors carrying the output load to the mutual conductance is substantially constant, variation in gain is suppressed.

  Furthermore, according to the differential amplifier of the present invention, since all elements including the current source can be constructed by MOS type transistors, the area occupied by the semiconductor chip is relatively large, such as a resistor or a capacitor. It is possible to reduce the scale as compared with those including elements.

  Further, in the differential amplifier 100 shown in FIG. 1 or FIG. 2, a new current source may be connected in parallel with each of the transistors (13, 14, 23, 24) serving as an output load.

  FIGS. 3 and 4 are circuit diagrams showing a second embodiment of the differential amplifier 100 made in view of such a point.

In the differential amplifier 100 shown in FIG. 3, current sources 31 and 32 are added to the configuration shown in FIG. 1, and one end and the other end of the current source 31 are connected to the drain terminal and the source terminal of the transistor 13, respectively. Except for the point that one end and the other end of the current source 32 are connected to the drain terminal and the source terminal of the transistor 14, respectively, the configuration is the same as that shown in FIG. That is, one end and the other end of the current source 31 are connected between the power supply voltage VSS and the output line L _{OP, respectively,} and one end and the other end of the current source 32 are connected between the power supply voltage VSS and the output line L _ON. Are connected to each other.

Therefore, according to the differential amplifier 100 shown in FIG. 3, the output load for converting the current flowing through the output line L _OP into a voltage is the transistor 13 and the current source 31 connected in parallel with each other. The output load for converting the current flowing through the output line L _ON into a voltage is the transistor 14 and the current source 32 connected in parallel with each other.

In the differential amplifier 100 shown in FIG. 4, current sources 31a and 32a are added to the configuration shown in FIG. 2, and one end and the other end of the current source 31a are connected to the drain terminal and the source terminal of the transistor 23 as an output load, respectively. In addition, the other configuration is the same as that shown in FIG. 2 except that one end and the other end of the current source 32a are connected to the drain terminal and the source terminal of the transistor 24, respectively. That is, the one end and the other end of the current source 31a between the power supply voltage VDD and the output line L _OP are respectively connected between the power supply voltage VDD and the output line L _ON, one end and the other end of the current source 32a Are connected to each other.

Therefore, according to the differential amplifier 100 shown in FIG. 4, the output load for converting the current flowing through the output line _LOP into a voltage is the transistor 23 and the current source 31a connected in parallel with each other. The output load for converting the current flowing through the output line L _ON into a voltage is the transistor 24 and the current source 32a connected in parallel with each other.

Here, on the differential input unit side of the current mirror unit, the operating point voltage is determined by the current flowing from the current source (19, 29) of the differential input unit. Based on this operating point voltage, the output side of the current mirror section allows current to flow to the diode-connected transistors (13, 14, 23, 24) via the output lines (L _OP , L _ON ). Therefore, the operating point voltage of the output is determined from the current. The operating region as a MOS transistor is determined according to the operating point voltage, and the characteristics (transconductance) of the transistor are determined from this operating region. At this time, in the differential amplifier 100, since the gain is determined from the transconductance ratio of the transistor, a shift occurs in the gain when the operating point shifts the operating region of the transistor. The operating point voltage that determines the operating region of the transistor changes greatly as the amplitude of the input signal (V _IP , V _IN ) increases. For this reason, when the amplitude of the input signal becomes so large that the operating region of the element is shifted, the gain may be unstable. In the differential amplifier 100 shown in FIG. 1 or FIG. 2, the magnitude of the amplitude of the input signal is directly connected to the fluctuation range of the current flowing through the diode-connected transistor. In the diode-connected transistor, when the fluctuation range of the flowing current becomes large, the assumed saturation region may shift to the linear region, and at this time, the mutual conductance changes. Further, when the fluctuation range becomes large and the transition from the saturation region to the cutoff region occurs, the mutual conductance changes by an order of magnitude in the cutoff region, so that not only the gain but also the amplification operation itself may become unstable.

However, in the differential amplifier 100 shown in FIG. 3 or FIG. 4, the current flowing into the output lines (L _OP , L _ON ) due to the operation of the current mirror units (CM1, CM2) is converted into diode-connected transistors (outputs). 13, 14, 23, 24) and current sources (31, 31 a, 32, 32 a). That is, the fluctuation of the current flowing through the output line is also distributed to the diode-connected transistor and the current source.

Therefore, according to the differential amplifier 100 shown in FIG. 3 or FIG. 4, since the fluctuation range of the current flowing through the diode-connected transistor is reduced, compared with the differential amplifier 100 shown in FIG. 1 or FIG. The instability of the gain and the amplification operation with respect to the non-inverted input signal _VIP and the inverted input signal _{VIN having} a large amplitude is reduced. In other words, according to the differential amplifier 100 shown in FIG. 3 or FIG. 4, it is possible to receive the non-inverted input signal _VIP and the inverted input signal V _IN having a large amplitude.

According to the differential amplifier 100 shown in FIG. 3 or FIG. 4, the output load is 1 / (g _mls + 1 / _ro ), and the gain _AV is
A _V = g _m / (g _mls + 1 / _ro )
g _m: transconductance g _mls of the differential input section (transistors 11, 12, 21, 22): mutual transistors 13,14,23,24 conductance r _o: current source 31, 31a, and an output impedance of 32,32a Become.

At this time, since the gain A _V can but will deviate from the ratio of the transconductance to sufficiently reduce the 1 / r _o compared to the transconductance g _mls of transistors 13,14,23,24, this deviation It is possible to make it as small as possible.

  In the differential amplifier 100 shown in FIG. 3 or FIG. 4, the current source (31, 31a, 32, 32a) is connected in parallel with each of the transistors (13, 14, 23, 24) serving as an output load. However, this may be connected in parallel to each of the current mirror units CM1 and CM2.

  5 and 6 are circuit diagrams showing a third embodiment of the differential amplifier 100 made in view of this point.

In the differential amplifier 100 shown in FIG. 5, the current source is connected in parallel from the transistors 13 and 14 as output loads to the output side of the first current mirror unit CM1 and the output side of the second current mirror unit CM2. Except for the changed points, the other configurations are the same as those shown in FIG. In the differential amplifier 100 shown in FIG. 5, one end and the other end of the current source 31b between the power supply voltage VDD and the output line L _OP are respectively connected, a current between the power supply voltage VDD and the output line L _ON One end and the other end of the source 32b are respectively connected.

Further, in the differential amplifier 100 shown in FIG. 6, the current source is connected in parallel from the transistors 23 and 24 as output loads, the output side of the first current mirror unit CM1, and the output of the second current mirror unit CM2. Except for the points changed to the respective sides, the other configuration is the same as that shown in FIG. In the differential amplifier 100 shown in FIG. 6, one end and the other end of the current source 31c between the supply voltage VSS and the output line L _OP are respectively connected between the power supply voltage VSS and the output line L _ON, One end and the other end of the current source 32c are respectively connected.

According to the differential amplifier 100 shown in FIGS. 5 and 6, the output to the line L _OP and L _ON, the input signal (V _IP, V _IN) to the other signal component corresponding to the amplitude of the current source (31b, 31c) and a constant current as a bias component generated by the current sources (32b, 32c) flows. As a result, it is possible to suppress fluctuations in the current flowing through the diode-connected transistors (13, 14, 23, 24) against such fluctuations in the signal component. Accordingly, as shown in FIGS. 1 to 4, a transistor serving as an output load is compared with a configuration in which only signal components corresponding to the amplitudes of the input signals (V _IP , V _IN ) flow into the output lines L _OP and L _ON. The transition of the operating region (13, 14, 23, 24) is suppressed, and the variation of the mutual conductance determined from the operating region is suppressed. Therefore, similarly to the differential amplifier 100 shown in FIGS. 3 and 4, the gain of the large amplitude input signals (V _IP , V _IN ) is stabilized, and the differential amplifier 100 shown in FIGS. The same gain A _V , that is,
A _V = g _m / g _mls
g _m : mutual conductance of the differential input section (transistors 11, 12, 21, and 22) g _mls : mutual conductance of the output load (transistors 13, 14, 23, and 24) is obtained.

In the differential amplifier 100 shown in FIGS. 1 to 6, the diode-connected output load transistors (13, 14, 23, 24) are provided in one stage for each output line (L _OP , L _ON ). However, it is also possible to provide each output line by connecting them in series over n stages (n is an integer of 2 or more).

  7 and 8 are circuit diagrams showing a fourth embodiment of the differential amplifier 100 made in view of the above points, and FIGS. 9 and 10 are circuit diagrams showing the fifth embodiment. FIG. 11 and FIG. 12 are circuit diagrams showing the sixth embodiment.

The differential amplifier 100 shown in FIG. 7 includes series n-stage transistors 13 _{1 to} 13 _n each of which is diode-connected instead of the transistor 13 shown in FIG. The other configuration is the same as that shown in FIG. 1 except that the n-stage transistors 14 _{1 to} 14 _n connected in series are diode-connected.

Further, the differential amplifier 100 shown in FIG. 8 is provided with series n-stage transistors 23 ₁ to 23 _n each of which is diode-connected instead of the transistor 23 shown in FIG. 2 is the same as that shown in FIG. 2 except that the n-stage transistors 24 _{1 to} 24 _n connected in series are diode-connected.

Further, the differential amplifier 100 shown in FIG. 9 is provided with series n-stage transistors 13 _{1 to} 13 _n each of which is diode-connected instead of the transistor 13 shown in FIG. 3 is the same as that shown in FIG. 3 except that the n-stage transistors 14 _{1 to} 14 _n connected in series are diode-connected. At this time, in the configuration shown in FIG. 9, the first transistor group including the above-described series n-stage transistors 13 _{1 to} 13 _n is connected in parallel to one end and the other end of the current source 31 and one end of the current source 32 is connected. The second transistor group consisting of the above-described n-stage transistors 14 _{1 to} 14 _n is connected in parallel to the other end. That is, one end and the other end of the current source 31 are connected between the power supply voltage VSS and the output line L _{OP, respectively,} and one end and the other end of the current source 32 are connected between the power supply voltage VSS and the output line L _ON. Are connected to each other.

Further, the differential amplifier 100 shown in FIG. 10 is provided with series n-stage transistors 23 ₁ to 23 _n each of which is diode-connected instead of the transistor 23 shown in FIG. 4 is the same as that shown in FIG. 4 except that the n-stage transistors 24 _{1 to} 24 _n connected in series are diode-connected. In this case, in the configuration shown in FIG. 10, the first transistor group including the above-described series n-stage transistors 23 ₁ to 23 _n is connected in parallel to one end and the other end of the current source 31 a and one end of the current source 32 a is connected. The second transistor group consisting of the above-described n-stage transistors 24 _{1 to} 24 _n is connected in parallel to the other end. That is, the one end and the other end of the current source 31a between the power supply voltage VDD and the output line L _OP are respectively connected between the power supply voltage VDD and the output line L _ON, one end and the other end of the current source 32a Are connected to each other.

Further, the differential amplifier 100 shown in FIG. 11 is provided with series n-stage transistors 13 _{1 to} 13 _n each of which is diode-connected instead of the transistor 13 shown in FIG. 5 is the same as that shown in FIG. 5 except that the n-stage transistors 14 _{1 to} 14 _n connected in series are diode-connected.

Further, the differential amplifier 100 shown in FIG. 12 is provided with series n-stage transistors 23 ₁ to 23 _n each of which is diode-connected instead of the transistor 23 shown in FIG. 6 is the same as that shown in FIG. 6 except that the n-stage transistors 24 _{1 to} 24 _n connected in series are provided.

  7 to 12, the common mode voltage can be adjusted by the number of stages in which the output load transistors are connected in series. That is, when the transistor used as the differential input section is an n-channel type as shown in FIG. 7, FIG. 9, or FIG. 11, as the number of stages for connecting output load transistors in series is increased, that is, as n described above increases. The common mode voltage will increase. On the other hand, when the transistor used as the differential input section is a p-channel type as shown in FIG. 8, FIG. 10, or FIG. 12, the common mode voltage decreases as the number of stages connecting the output load transistors in series increases. . At this time, the common mode voltage can be finely adjusted by changing the channel length and channel width of the output load transistor described above, or by changing the current that constantly flows through the output load transistor.

  In short, according to the configuration shown in FIGS. 7 to 12, the common mode voltage of the differential amplifier 100 can be set to a desired voltage depending on the number of series stages of the output load transistors.

  FIG. 13 is a block diagram showing a schematic configuration of a wireless communication apparatus including the differential amplifier 100 having the configuration shown in FIGS. Such a wireless communication device includes an amplifier 1, a mixer 3, a local oscillation circuit 4, a bandpass filter 5, a limiter 6, a demodulator 7, and a received signal strength, which are formed on a semiconductor chip as a semiconductor device as follows. An RSSI (Received Signal Strength Indication) circuit 8 as a detection circuit is included.

In FIG. 13, the amplifier 1 amplifies the reception signal received by the antenna 2 to generate an amplified reception signal AR, and supplies this to the mixer 3. The local oscillator 4 generates a local oscillation signal F having a predetermined frequency substantially equal to the carrier signal frequency in the received signal and supplies it to the mixer 3. The mixer 3 multiplies the amplified reception signal AR and the local oscillation signal F, and supplies this to the bandpass filter 5 as the frequency converted reception signal IF. The band pass filter 5 extracts a signal in a preset frequency band by removing unnecessary frequency components in the frequency converted reception signal IF, and uses the band limited reception signals LF _OP and LF as differential signals indicating the signal. _ON is supplied to the limiter 6. The limiter 6 amplifies the band-limited reception signals LF _OP and LF _ON in the differential signal form, and performs waveform shaping by applying a limiter to the amplitude upper limit side and the lower limit side, thereby receiving the signal in the differential signal form SSS _OP and _SSON are generated.

  FIG. 14 is a diagram showing an internal configuration of the limiter 6.

As shown in FIG. 14, the limiter 6, the differential amplifier 100 ₁ to 100 _M of M each having a same gain _{A V (A V> 1)} (M is an integer of 2 or more) are connected in series It will be. Note that each of the differential amplifiers 100 _{1 to} 100 _M has any one of the configurations shown in FIGS. According to the configuration shown in FIG. 14, the amplitude level of the output signal of each of the differential amplifiers 100 _{1 to} 100 _M increases as the differential amplifier 100 in the subsequent stage increases. Therefore, as the amplitude levels of the band limited reception signals LF _OP and LF _ON increase, the amplitude level of the output signal saturates in order from the differential amplifier 100 at the subsequent stage. That is, when the differential amplifier 100 _{M at} the final stage is saturated, the reception signals SS _OP and SS _ON at a certain level are generated even if the amplitude levels of the band limited reception signals LF _OP and LF _ON are further increased thereafter. Is done.

Here, the limiter 6 supplies the received signal SS _OP and SS _ON as described above in the demodulator 7, the differential amplification signal VP ₁ ~VP _M-1 output from the differential amplifier 100 ₁ to 100 _M, respectively, VN _{1 to} VN _M-1 are supplied to a received signal strength indication (RSSI) circuit 8 as a received signal strength detection circuit. Demodulator 7, and outputs this to obtain original baseband signals by performing predetermined demodulation processing on the received signal SS _OP and SS _ON.

As shown in FIG. 14, the RSSI circuit 8 includes peak detection circuits 80 ₁ to 80 _M−1 provided in association with the differential amplifiers 100 _{1 to} 100 _M−1 described above, and an adder 81. Including. The peak detection circuit 80 ₁ detects the peak level of the amplitude based on the differential amplified signals VP ₁ and VN ₁ as differential signals, and supplies this to the adder 81 as the amplitude value VF ₁ . The peak detection circuit 80 ₂ detects the peak level of the amplitude based on the differential amplification signals VP ₂ and VN ₂ as differential signals, and supplies this to the adder 81 as the amplitude value VF ₂ . Hereinafter, similarly, the peak detection circuit 80 _Q [Q: integer of 3 to (M−1)] detects the peak level of the amplitude by the differential amplification signals VP _Q and VN _Q , and this is detected as the amplitude value VF _Q. To the adder 81. The adder 81 outputs the the sum of all the amplitude values VF ₁ ~VF _M-1 supplied from the peak detecting circuit 80 ₁ ~80 _M-1 respectively as a received signal strength detection signal SSI representative of the intensity of the received signal . That is, the received signal strength detection signal SSI is a signal that increases or decreases according to the amplitude (signal strength) of the received signal. In the RSSI circuit 8, the output signal saturates in order from the subsequent differential amplifier 100 as the received signal strength increases, so that the received signal strength detection signal SSI is a piecewise linear signal strength of the received signal. The signal is expressed by a pseudo logarithmic value by approximation.

  As described above, according to the RSSI circuit 8, the received signal strength detection signal SSI that represents the signal strength of the received signal as a logarithmic value can be obtained. Therefore, a wide range change in the signal strength can be detected within a limited voltage range. It becomes possible.

Here, the RSSI circuit 8, as described above, the signal strength of a received signal for which as represented in pseudo logarithm by linear approximation, the differential amplifier 100 ₁ ~100 _M-1 Each of the gain A _V If there is variation, the linear approximation is distorted and the accuracy of the received signal strength detection signal SSI is lowered. In particular, as shown in FIG. 14, in the configuration in which a plurality of differential amplifiers are connected in series, error of the differential amplifier of the differential amplifier signal with a variation in the gain A _V of the differential amplifier (VP, VN) Therefore, the accuracy of the received signal strength detection signal SSI significantly decreases due to the gain variation of the differential amplifier 100. The mutual conductances of the transistors (11, 12, 21, 22) responsible for the differential input section of the differential amplifier 100 and the transistors (13, 14, 23, 24) responsible for the output load vary in manufacturing. Alternatively, variations occur due to the influence of temperature and power supply voltage fluctuations.

However, according to the internal configuration shown in FIGS. 1 to 12, the gain A _V of the differential amplifier 100, to determine the ratio of the transconductance of the transistor responsible for differential input section, a mutual conductance of the output load transistor , gain a _V of the differential amplifier 100 even if variations occur in the transconductance of the differential amplifier 100 ₁ to 100 _M-1, each example is uniform.

  Therefore, when the differential amplifier 100 according to the present invention is employed as a limiter amplifier formed by connecting a plurality of amplifiers in series, high accuracy can be achieved regardless of manufacturing variations or temperature or power supply voltage fluctuations. It is possible to detect received signal strength.

11-14, 25-28 n-channel MOS transistors 21-24, 15-18 p-channel MOS transistors 19, 29, 31, 32 Current source 100 Differential amplifier

Claims (4)

A differential amplifier for amplifying first and second input signals in a differential signal form to generate first and second output signals in a differential signal form,
First and second transistors having source terminals connected in common to each other and having the first and second input signals supplied to the respective gate terminals;
A first current source connected to a source terminal of each of the first and second transistors;
A first current mirror section for flowing a first output current corresponding to a current flowing through the first transistor to a first output line;
A second current mirror section for passing a second output current corresponding to the current flowing through the second transistor to the second output line;
A first output load unit for outputting a voltage on the first output line as the first output signal;
A second output load for outputting the voltage on the second output line as the second output signal;
A second current source connected in parallel to the first output load section;
A third current source connected in parallel to the second output load section ,
The first output load unit includes a third transistor having the same conductivity type as the first transistor, the gate terminal and the drain terminal of which both are connected to the first output line.
2. The differential amplifier according to claim 1, wherein the second output load section includes a fourth transistor having the same conductivity type as the second transistor, the gate terminal and the drain terminal of which are both connected to the second output line. The first output load section includes a first transistor group including a third transistor including a third transistor in which a plurality of transistors each having a gate terminal and a drain terminal connected to each other are connected in series.
2. The second output load section includes a second transistor group including a plurality of transistors each having a gate terminal and a drain terminal connected to each other, the first transistor group including the fourth transistor. Differential amplifier. The first and second received signals in the form of differential signals are sequentially amplified by a multi-stage differential amplifier connected in series to limit the upper and lower limits of the amplitude, and output from each of the multi-stage differential amplifiers A received signal strength detection circuit that obtains a received signal strength detection signal that represents the signal strength of the received signal in a logarithmic value based on the first and second amplified signals in the differential signal form,
Each of the differential amplifiers has a first terminal and a second transistor, the source terminals of which are commonly connected to each other and the first and second signals in the form of differential signals are supplied to the respective gate terminals,
A first current source connected to a source terminal of each of the first and second transistors;
A first current mirror section for flowing a first output current corresponding to a current flowing through the first transistor to a first output line;
A second current mirror section for passing a second output current corresponding to the current flowing through the second transistor to the second output line;
A first output load unit for outputting a voltage on the first output line as the first output signal;
A second output load for outputting the voltage on the second output line as the second output signal;
A second current source connected in parallel to the first output load section;
A third current source connected in parallel to the second output load section,
The first output load unit includes a third transistor having the same conductivity type as the first transistor, the gate terminal and the drain terminal of which both are connected to the first output line.
The second output load unit, the gate and drain terminals connected together to said second output line, a semiconductor device which comprises a fourth transistor of the second transistor of the same conductivity type. The first output load section includes a first transistor group including a third transistor including a third transistor in which a plurality of transistors each having a gate terminal and a drain terminal connected to each other are connected in series.
The second output load unit, the fourth includes transistors, according to claim 3, wherein the plurality of transistors having a gate and drain terminals are connected to each other is characterized by having a second transistor group formed by connecting in series Semiconductor device .

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