JP5844667B2 - Decoding device, decoding method, and wireless communication device - Google Patents

Description

  The present invention relates to a decoding device, a decoding method, and a wireless communication device that perform error correction decoding on received data.

  As the quality of electronic equipment that handles video and audio has improved, the capacity of data has increased, and the capacity of data to be transmitted and received has also increased in communication systems. Electronic devices (for example, mobile phones) are required to be downsized, low cost, and low power consumption, and communication systems are required to transmit and receive data with as few errors as possible. For this reason, an error correction function (for example, FEC: Forward Error Correction) plays a major role in data communication.

  Conventionally, error correction technology has shifted from hard decision error correction (for example, Reed-Solomon code, BCH code) to soft decision error correction (for example, Viterbi decoding), but in recent years, soft decision error correction with higher correction capability has been performed. (For example, a Turbo code or a Low-Density Parity-Check (LDPC) code) is used.

  The soft decision error correction code does not express the received data as a binary bit string of “0” and “1” (hard decision), but expresses the probability of the received data by a plurality of bits (soft). Judgment) improves the correction ability.

  In recent error correction coding systems, turbo codes or LDPC codes are used as a result of tackling the problem of how to realize communication close to the Shannon limit, which is a theoretical limit.

  However, in order to use an error correction code using a turbo code or LDPC code, the circuit configuration increases in complexity and the circuit scale is large. The cause of the complexity is that an operation for performing error correction on received data during communication is included in an error correction circuit currently in practical use. Therefore, the error correction circuit also increases power consumption, which hinders downsizing and low power consumption.

  Another factor that increases the circuit scale is the number of bits of data to be processed. That is, since the soft decision expresses the certainty of received data by a plurality of bits, the circuit scale increases as the number of bits of data (soft decision value) increases. Also, as the number of bits increases, the power consumption of the circuit also increases.

  With respect to the number of soft decision bits, Patent Documents 1 and 2 disclose prior arts that change (scaling) the number of soft decision bits according to the quality of a channel as a transmission path. An outline of Patent Document 1 is shown in FIG. 12, and an outline of Patent Document 2 is shown in FIG.

  In U.S. Pat. No. 6,057,056, a soft value (soft decision value) output from a demodulator 56 is used through a decoder 58 through a processor 44 to determine a scale factor to be used as a function of a preselected channel quality value 66. To supply. The processor 44 returns the scaled soft value to the decoder 58. The scaling circuit included at the input of the decoder 58 is a circuit used to perform a scaling dependent iterative decoding process. That is, a scaling circuit is used to scale the soft input value before iterating the decoding process. The scaling factor is determined by solving an equation using the processor 44.

  Further, in Patent Document 2, the communication channel monitoring unit 49 constantly calculates a bit error rate (BER) based on the correction result output from the error correction decoding unit 25, and determines the state of the communication channel based on the bit error rate. It is constantly monitored. Further, the communication channel monitoring unit 49 obtains a signal-to-noise ratio (SNR) of the communication channel based on the bit error rate, and outputs the signal-to-noise ratio to the scaling unit 50. Based on the signal-to-noise ratio received from communication channel monitoring unit 49, scaling unit 50 determines whether or not to multiply log-likelihood ratio λn from likelihood determining unit 48 by a predetermined magnification. When the log likelihood ratio λn from the likelihood determining unit 48 is to be multiplied by a predetermined magnification, the scaling unit 50 multiplies the log likelihood ratio λn by a predetermined magnification and outputs the result to the error correction decoding unit 25.

JP-T-2006-515483 JP 2009-159037 A

  However, in Patent Document 1, it is necessary to finish calculating the scaling factor in advance before executing error correction. In addition, the calculation of the scaling factor is complicated, and the time from the start to the end of the calculation is long. Also in Patent Document 2, it takes a long time to perform processing from measurement of the bit error rate to determination of scaling of the soft decision value.

  Here, in a mobile terminal such as a mobile phone, the communication quality changes with time, so it is necessary to adaptively reflect the scaling value.

  However, in the prior art, even if the communication quality of the transmission path is good, it is difficult to adaptively reduce the number of bits processed by the error correction decoding circuit because the processing time for scaling determination is long. For this reason, it is difficult to reduce the power consumption in the error correction decoding circuit in the calculation of the scaling value of the conventional configuration.

  The present invention has been made in view of the above-described conventional circumstances, and includes a decoding device, a decoding method, and wireless communication that perform high-speed decoding by reducing the amount of decoding processing of received data according to the communication quality of a transmission path. An object is to provide an apparatus.

  The present invention is a decoding device for decoding received data including a header, based on an error correction decoding unit that performs error correction decoding of the soft decision value of the received data by iterative decoding, and an output result of the error correction decoding, The data error detection unit that detects the presence or absence of a data error, the number of repetitions of iterative decoding in the error correction decoding of the header, and the reception subject to the error correction decoding based on the detection result of the presence or absence of the data error And a control unit that determines the number of effective bits of data.

  In addition, the present invention is a decoding method for decoding received data including a header, the step of performing error correction decoding of the header of the received data by iterative decoding, and the presence or absence of a data error based on the output result of error correction decoding The number of effective bits of the received data to be subjected to the error correction decoding is determined based on the detection step, the number of repetitions of iterative decoding in the error correction decoding of the header, and the detection result of the presence or absence of the data error Including the steps of:

  ADVANTAGE OF THE INVENTION According to this invention, according to the communication quality of a transmission line, the decoding processing amount of received data can be reduced and it can decode at high speed.

The block diagram which shows the structural example of the transmission / reception apparatus of this embodiment The block diagram which shows the structural example of the error correction receiver of this embodiment Block diagram showing a configuration example of an error correction decoding unit Time chart showing an operation example of the error correction receiver when the transmission line quality is poor Time chart showing an operation example of the error correction receiving apparatus when the transmission path quality is better than FIG. Time chart showing an operation example of the error correction receiving apparatus when the transmission line quality is better than FIG. Schematic diagram showing a configuration example (1) of the effective bit number table Schematic diagram showing a configuration example (2) of the effective bit number table Flowchart explaining the operation for the header of the error correction decoder Flowchart for explaining operation of payload of error correction decoder The graph which shows the relationship between the effective bit number of a soft decision value, and an error rate (BER) Block diagram showing outline of Patent Document 1 Block diagram showing outline of Patent Document 2

  Hereinafter, embodiments of a decoding device, a decoding method, and a wireless communication device according to the present invention will be described with reference to the drawings.

<Configuration of Transmission / Reception Device 300 as a Wireless Communication Device>
FIG. 1 is a block diagram illustrating a configuration example of the transmission / reception device 300 of the present embodiment. The transmission / reception device 300 as a wireless communication device includes a transmission unit TX and a reception unit RX.

  The transmission unit TX of the transmission / reception apparatus 300 includes an error correction encoder 301, a modulator 302, a DAC (Digital Analog Converter) 303, a transmission analog processing unit 304, a PA (Power Amplifier) 305, and an antenna (ANT) to which an antenna Ant is connected. ) Circuit 306.

  The reception unit RX of the transmission / reception apparatus 300 includes an antenna circuit 306 to which an antenna Ant is connected, a reception analog processing unit 307, an ADC (Analog Digital Converter) 308, a demodulation unit 309, an error correction decoder 310, and a data recognition unit 311. The antenna Ant is configured using, for example, an antenna element. The antenna circuit 306 to which the antenna Ant is connected may be included in either the transmission unit TX or the reception unit RX.

<Operation when Transmission / Reception Device 300 Transmits Radio Signal>
The error correction encoder 301 adds an error correction code (for example, a parity code generated by a low density parity check (LDPC) code as an error correction check code) to transmission data. The transmission data to which the parity code is added by the error correction encoder 301 is input to the modulator 302.

  The modulator 302 modulates the input transmission data according to a modulation scheme shared in advance with another receiving apparatus (not shown). Examples of the modulation scheme include BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), and 16QAM (Quadrature Amplitude Modulation). The transmission data modulated by the modulator 302 is input to the DAC 303.

  The DAC 303 converts the transmission data of the digital signal into an analog signal. An analog signal output from the DAC 303 is input to the transmission analog processing unit 304 and subjected to predetermined signal processing (for example, up-conversion processing from a baseband signal to a high-frequency signal), and then input to the PA 305.

  The PA 305 amplifies the input analog signal and outputs it to the antenna circuit 306. Accordingly, a wireless transmission signal (radio wave) is output from the antenna circuit 306 via the antenna Ant.

<Operation when Transmission / Reception Device 300 Receives Radio Signal>
A radio signal transmitted from another transmission device (not shown) is received by the antenna circuit 306 via the antenna Ant and input to the reception analog processing unit 307 as a reception signal. The reception analog processing unit 307 performs predetermined signal processing (for example, down-conversion processing from a high-frequency signal to baseband, AGC (Auto Gain Control) processing) on the input reception signal. The reception signal processed by the reception analog processing unit 307 is input to the ADC 308.

  The ADC 308 converts the received signal input as an analog signal into a digital signal, and outputs it as received data. The demodulator 309 demodulates the received data input from the ADC 308 according to a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM) shared in advance with another transmitting apparatus (not shown).

  The received data demodulated by the demodulator 309 is input to an error correction decoder 310 as a decoding device of this embodiment. The error correction decoder 310 performs error correction decoding on the input received data, and outputs the received data after error correction decoding to the data recognition unit 311.

  The data recognition unit 311 receives the error-corrected received data output from the error correction decoder 310 and recognizes data necessary for control of the transmission / reception device 300. For example, the data recognizing unit 311 recognizes information on the modulation format and coding rate of the payload included in the header of the received data, and determines the timing necessary for controlling the transmission / reception device 300 based on the guard interval (GI). Generate.

  Hereinafter, the configuration and operation of the error correction decoder 310 as the decoding apparatus of the present embodiment will be described in detail.

<Configuration of Error Correction Reception Device 400 as Decoding Device (Error Correction Decoder 310)>
An example of the configuration of the error correction receiving apparatus 400 of this embodiment is shown in FIG. An error correction receiving apparatus 400 shown in FIG. 2 corresponds to the error correction decoder 310 shown in FIG.

  The error correction receiving apparatus 400 includes a bit number limiting unit 401, an error correction decoding unit 402, a parity check unit 403, a control unit 404, and a clock generation unit 405.

  Bit number limiting section 401 receives received data as an output of demodulation section 309 shown in FIG. The received data is a soft decision value representing the probability of bit data “0” and “1”. In the present embodiment, the reception data RD1 is input to the bit number limiting unit 401 as a 5-bit parallel signal. Note that the number of bits of the reception data RD1 may be changed as necessary.

  Bit number limiting section 401 limits the number of effective bits of received data RD2 input to error correction decoding section 402 as a soft decision value. Specifically, the bit number limiting unit 401 outputs, as received data RD2, a result of fixing each bit other than the most significant bit of the parallel signal to “0” for the received 5-bit received data RD1. For example, in the 5 bits of the reception data RD2, the same signal as that of the reception data RD1 is output except for the fixed bits, or a rounding process is performed on the bits fixed to 0 and output.

  The bits fixed by the bit number limiting unit 401 are determined according to the control signal CON1 output from the control unit 404. Specifically, the bit number limiting unit 401 is configured to fix the received data of the input 5-bit parallel signal in a state where the least significant bit of the received data RD2 is fixed, a state where the lower 2 bits are fixed, and a lower 3 bits. To the fixed state, the lower 4 bits are fixed, or all the bits are not fixed (same as RD1).

  Note that changing the number of effective bits of the received data RD2 input to the error correction decoding unit 402 by the bit number limiting unit 401 is synonymous with scaling of the soft decision value. That is, if the number of effective bits of the received data RD2 is increased, the error correction capability of the error correction decoding unit 402 is increased, and if the number of effective bits is decreased, the error correction capability of the error correction decoding unit 402 is decreased.

  Error correction decoding section 402 receives received data RD2 as a soft decision value, and repeats predetermined decoding, that is, iteratively decodes the received data to correct errors. The number of decoding iterations may be changed as necessary. The processing result of the error correction decoding unit 402 is input to the parity check unit 403 as 1-bit signal reception data RD3. In addition, the error correction decoding unit 402 operates in synchronization with a clock pulse CLK having a fixed period supplied by the clock generation unit 405.

  A parity check unit 403 serving as a data error detection unit sequentially receives the received data RD3 output from the error correction decoding unit 402 and performs parity check, thereby converting the error correction processing result data of the error correction decoding unit 402 into data. Identify if there are no errors.

  The parity check unit 403 outputs a signal PCH indicating the presence or absence of a data error to the control unit 404 as a result of the parity check. The corrected reception data RD4 output from the parity check unit 403 is a 1-bit signal that is the same as the reception data RD3 output from the error correction decoding unit 402. Note that the parity check unit 403 operates in synchronization with a clock pulse CLK having a fixed period supplied by the clock generation unit 405.

  The control unit 404 receives the “reception data enable” and “coding rate” signals output from the data recognition unit 311 shown in FIG. “Received data enable” is a timing signal representing a valid period of received data, and is generated by the data recognition unit 311 based on a guard interval in the received signal. The “coding rate” is information included in the header area of the received signal.

  The control unit 404 grasps the number of repetitions of decoding in the error correction decoding unit 402 and grasps the presence / absence of a data error based on the signal PCH. Since the time required for one decoding in the error correction decoding unit 402 is constant, the control unit 404 grasps the number of decoding iterations of the error correction decoding unit 402 based on the elapsed time from the start of decoding. To do.

  The control unit 404 determines the number of effective bits of the reception data RD2 limited by the bit number limiting unit 401 based on the number of decoding iterations of the error correction decoding unit 402 and the presence / absence of a data error grasped by the signal PCH, A control signal CON1 corresponding to the number of effective bits is output. When receiving the header area of the received signal (received data), the control unit 404 determines the number of effective bits by monitoring the operation status of the error correction decoding unit 402, that is, the quality of the transmission path.

  In addition, the control unit 404 controls the output of the control signal CON2 to stop the supply of the clock pulse CLK output from the clock generation unit 405 or restart the supply of the clock pulse CLK. Specific operations of the control unit 404 will be described later.

<Configuration Example of Error Correction Decoding Unit 402>
FIG. 3 shows a configuration example of the error correction decoding unit 402 in the error correction receiving apparatus 400 of FIG. That is, when a known minisum decoding method is used as an LDPC code decoding method, the error correction decoding unit 402 can be configured by the circuit shown in FIG.

  The error correction decoding unit 402 includes a column processing unit 501 and a row processing unit 502. Each processing unit performs arithmetic processing according to the mathematical formulas (1) and (2). That is, although not illustrated, the inside of the column processing unit 501 and the row processing unit 502 is configured using an adder and a comparator that searches for a minimum value.

  For this reason, when each bit of the received data RD2 remains “0” and does not change, the state of the circuit that processes the corresponding bit does not change. For example, since the result of adding “0” and “0” is “0”, the output bit does not change unless the input bit remains “0”. Since the circuit that processes the bits does not move, the power consumed by the circuit of the error correction decoding unit 402 is greatly reduced. In Equations (1) and (2), m represents a row number, n represents a column number, and ω represents a positive real number of 1 or less.

  Note that the error correction decoding unit 402 using the “minisum decoding method” can obtain an error rate characteristic equivalent to the “sum-product” algorithm, for example, by giving a value of about “0.8” as ω. Note that the value “0.8” is merely an example, and the optimum value varies depending on the check matrix H.

<Example of operation timing of error correction receiving apparatus 400>
Specific examples of timing related to the operation of the error correction receiving apparatus 400 are shown in FIGS. 4, 5, and 6. FIG. 4 is a time chart showing an operation example of the error correction receiving apparatus 400 when the transmission path quality is poor. FIG. 5 is a time chart showing an operation example of the error correction receiving apparatus 400 when the transmission path quality is better than FIG. FIG. 6 is a time chart showing an operation example of the error correction receiving apparatus 400 when the transmission path quality is better than FIG.

  In this embodiment, as an example, it is assumed that the error correction receiving apparatus 400 receives the reception data having the frame format shown in FIG. That is, the received data includes header data DH, and first payload data DP1, second payload data DP2, third payload data DP3,.

  The header data DH holds information for managing data transmitted and received by the transmission / reception device 300. Specifically, it holds information on the modulation format and coding rate of the payload storing the data body. The modulation format of the header of the received data is shared in advance with other transmission devices (not shown). Further, a guard interval (GI) as a known signal is provided between each data in the frame format.

  The operation of each unit of error correction receiving apparatus 400 is as follows.

  When the control signal CON1 from the control unit 404 is not input, the bit number limiting unit 401 outputs the reception data RD1 output from the demodulation unit 309 to the error correction decoding unit 402 as reception data RD2. Error correction decoding section 402 receives received data RD2 and repeats error correction decoding. Each time the error correction decoding process is executed, the reception data RD3 after error correction is output.

  The parity check unit 403 performs a parity check on the received error-corrected received data RD3. If the syndrome becomes 0, the parity check unit 403 determines that there is no data error in the error-corrected received data RD3, and outputs a signal PCH in which the parity check is “OK”.

  In addition, the error correction decoding unit 402 shown in FIG. 2 has an upper limit on the number of repetitions of error correction decoding. For example, in the operation examples shown in FIGS. 4 to 6, the upper limit of the number of repetitions of error correction decoding is six.

  In the operation example shown in FIG. 4, since it is assumed that the quality of the transmission path is poor, the parity check is “OK” when the number of repetitions reaches the upper limit of 6. Note that the 0th iteration is a state in which error correction is not executed.

  Therefore, in FIG. 4, when the error correction decoding unit 402 repeats the error correction decoding many times until the result of the parity check becomes “OK”, it can be determined that the quality of the transmission path is poor. The restriction on the number of effective bits by the control signal CON1 is not performed. That is, the bit number limiting unit 401 outputs the reception data RD1 output from the demodulation unit 309 to the error correction decoding unit 402 as reception data RD2.

  On the other hand, in the operation example shown in FIG. 5, the parity check is “OK” when the number of repetitions of error correction decoding is the first. In other words, since the error correction decoding unit 402 has relatively good transmission path quality, it can decode received data without data error in the first error correction decoding.

  When the parity check is “OK”, the clock generation unit 405 stops supplying the clock pulse CLK to the error correction decoding unit 402 based on the control signal CON2 output from the control unit 404. Since the error correction decoding unit 402 operates in synchronization with the clock pulse CLK, when the supply of the clock pulse CLK is stopped, the circuit operation of the error correction decoding unit 402 is also stopped. That is, when the parity check becomes “OK” at an early stage, the error correction receiving apparatus 400 can reduce the power consumption of the error correction decoding unit 402 by stopping the supply of the clock pulse CLK.

  In the operation example shown in FIG. 6, the parity check is “OK” when the number of repetitions of error correction decoding is zero. That is, since the error correction decoding unit 402 can decode the received data without data error before error correction decoding, the quality of the transmission path is good.

  Also in the operation example shown in FIG. 6, after the parity check becomes “OK”, the clock generation unit 405 clocks the error correction decoding unit 402 based on the control signal CON2 from the control unit 404. The supply of the pulse CLK is stopped, and the circuit operation of the error correction decoding unit 402 is stopped.

<Limit on number of valid bits>
In the operation example shown in FIG. 5 or FIG. 6, even when the quality of the transmission path is good and the correction capability of the error correction decoding unit 402 is lowered, there is a high possibility that an appropriate error correction result is obtained. That is, the bit number limiting unit 401 can limit the number of effective bits of the reception data RD2 input to the error correction decoding unit 402.

  The control unit 404 determines the number of effective bits, and controls the operation of the bit number limiting unit 401 using the control signal CON1. The extent to which the number of effective bits can be limited is determined according to the quality of the transmission path. 4 to 6, there is a large correlation between the number of repetitions of decoding by the error correction decoding unit 402 until the parity check is detected as “OK” and the quality of the transmission path. Therefore, the control unit 404 determines the number of effective bits by associating the number of repetitions of decoding until the parity check is detected as “OK” with the number of effective bits.

<Description of effective bit number table>
The control unit 404 holds an effective bit number table and determines the effective bit number using the effective bit number table. Thereby, the control unit 404 can efficiently determine the number of effective bits limited by the bit number limiting unit 401. Specific configuration examples of the effective bit number table are shown in FIGS. 7 and 8, respectively.

  The effective bit number table TBL1 shown in FIG. 7 is different from the effective bit number table TBL2 shown in FIG. Either one of the effective bit number tables TBL1 and TBL2 may be used, or may be selectively used according to the state of the quality of the transmission path. The contents of the effective bit number table may be stored in a memory (for example, a non-volatile memory) in the control unit 404, and the control unit 404 may rewrite the contents as necessary.

  The effective bit number table TBL1 shown in FIG. 7 includes the following four types of data DT1, DT2, DT3, and DT4. That is, the data DT1 represents the number of times the decoding process is repeated until the parity check “OK” is detected. Data DT2 represents the number of soft decision bits. Data DT3 represents the number of effective bits. Data DT4 represents the number of bits fixed to “0”.

  The minimum necessary information in the effective bit number table TBL1 is data DT1 and data DT3 or data DT4. That is, the control unit 404 can associate the number of repetitions of decoding corresponding to the data DT1 with the number of effective bits corresponding to the data DT3 or the data DT4 by referring to the effective bit number table TBL1 shown in FIG.

<Specific example for determining the number of effective bits>
A specific example of using the effective bit number table TBL1 will be described. For example, in the operation example illustrated in FIG. 6, when decoding the header data DH, the parity check “OK” is performed when the number of repetitions of decoding is zero. The control unit 404 refers to the “0th” of the data DT1 of the effective bit number table TBL1, recognizes that the content of the data DT3 corresponding to the “0th” of the data DT1 is “1 bit”, and determines the number of effective bits. Is determined to be “1 bit”.

  The control unit 404 gives information indicating that the number of effective bits is “1 bit” to the bit number limiting unit 401 as the control signal CON1. As a result, the bit number limiting unit 401 fixes the lower 4 bits to “0” in the received data RD2 configured by the 5-bit parallel signal, and sets the most significant 1 bit as a valid bit.

  Therefore, in the operation example shown in FIG. 6, when the received data of the payload data DP1 following the header data DH is decoded, the number of effective bits of the received data RD2 input to the error correction decoding unit 402 is 1. That is, even if the 5-bit received data RD1 which is the soft decision value changes, the lower 4 bits in the 5 bits constituting the received data RD2 remain “0”.

  Further, in the operation example shown in FIG. 5, when decoding the header data DH, the number of repetitions of decoding is the first and the parity check is “OK”. The control unit 404 refers to the “first time” of the data DT1 of the effective bit number table TBL1, recognizes that the content of the data DT3 corresponding to the “first time” of the data DT1 is “2 bits”, and determines the number of effective bits. Is determined to be “2 bits”.

  The control unit 404 gives information indicating that the number of effective bits is “2 bits” to the bit number limiting unit 401 as the control signal CON1. As a result, the bit number limiting unit 401 fixes the lower 3 bits to “0” in the received data RD2 configured by the 5-bit parallel signal, and sets the remaining upper 2 bits as effective bits.

<Description of Operation Flow in Error Correction Receiver 400>
FIG. 9 shows a flowchart for explaining the operation of the error correction receiving apparatus 400 for the header. FIG. 10 is a flowchart for explaining the operation of the error correction decoder with respect to the payload. In other words, the control is performed sequentially according to the procedures shown in FIGS. 9 and 10 under the control of the control unit 404.

  When the header data DH appears as the reception data RD1, steps S11 to S16 in FIG. 9 are executed. When payload data (DP1, DP2,...) Appears, steps S21 to S28 in FIG. 10 are executed.

<Operation when Decoding Header Data DH>
The bit number limiting unit 401 does not limit the number of valid bits of the reception data RD2. That is, 5-bit received data RD1 is input to error correction decoding section 402 as received data RD2.

  Error correction decoding section 402 calculates error correction parameters and performs error correction decoding on received data RD2. The initial value of the error correction parameter is 0. Accordingly, the error correction decoding unit 402 performs decoding without correction at the first time, that is, the “0th” in FIGS. 4 to 6 (S11).

  The control unit 404 counts the number of repetitions of error correction decoding in the error correction decoding unit 402 (S12). The initial value of the number of repetitions is 0. Since the time required for one error correction decoding is determined in advance, the control unit 404 counts the number of repetitions of the error correction decoding in the error correction decoding unit 402 according to the elapsed time from the start of the error correction decoding. .

  Each time the error correction decoding unit 402 executes decoding once, the control unit 404 monitors the signal PCH as a parity check result in which the parity check unit 403 performs a parity check on the decoding result, and whether or not the parity check is OK. Is identified (S13).

  If there is a data error in the received data RD3 output from the error correction decoding unit 402 (S13, NO), the parity check is NG, and the operation of the error correction receiving apparatus 400 returns from step S13 to step S11. . That is, the error correction decoding unit 402 repeats error correction decoding a plurality of times (S11). Further, the control unit 404 counts the number of repetitions (S12).

  When the parity check is OK (S13, YES), the control unit 404 outputs the control signal CON2 to the clock generation unit 405, and supplies the clock pulse CLK to the error correction decoding unit 402 and the parity check unit 403. Is stopped by the clock generator 405 (S14). As a result, the operation of the error correction decoding unit 402 and the operation of the parity check unit 403 are stopped.

  When the parity check is OK (S13, YES), the control unit 404 determines the effective bit number by referring to the effective bit number table TBL1 using the number of repetitions of error correction decoding (S15). The control unit 404 outputs the control signal CON1 and sets the number of effective bits limited by the bit number limiting unit 401 (S16).

<Operation when decoding payload data (DP1, DP2,...)>
In step S16 shown in FIG. 9, the bit number limiting unit 401 limits the number of effective bits. Therefore, when the error correction receiving apparatus 400 receives payload data, the received data RD2 with the limited number of effective bits is error-correction decoded. The data is input to the unit 402 (S21).

  Error correction decoding section 402 calculates error correction parameters and performs error correction decoding on received data RD2. The initial value of the error correction parameter is 0. Accordingly, the error correction decoding unit 402 performs decoding without correction at the first time, that is, the “0th” in FIGS. 4 to 6 (S22).

  The control unit 404 counts the number of repetitions of error correction decoding in the error correction decoding unit 402 (S23). The initial value of the number of repetitions is 0. Since the time required for one error correction decoding process is determined in advance, the control unit 404 performs error correction decoding in the error correction decoding unit 402 according to the elapsed time from the start of error correction decoding for one payload data. Count the number of repetitions.

  Each time the error correction decoding unit 402 executes decoding once, the control unit 404 monitors the signal PCH as a parity check result in which the parity check unit 403 performs a parity check on the decoding result, and whether or not the parity check is OK. Is identified (S24).

  If there is a data error in the received data RD3 output from the error correction decoding unit 402 (S24, NO), the parity check is NG, and the operation of the error correction receiving apparatus 400 goes from step S14 to step S26. Then, the process returns to step S22. That is, the error correction decoding unit 402 repeats error correction decoding a plurality of times (S22). Further, the control unit 404 counts the number of repetitions (S23).

  Further, when the parity check is NG (S24, NO), the control unit 404 identifies whether it is NG even when the number of repetitions reaches a predetermined maximum value (for example, 6 times) (S26). ). In the case of NG even when the number of repetitions reaches the maximum value (S26, YES), the control unit 404 refers to the valid bit number table TBL1 or TBL2 again, and the number of valid bits is larger than the previous valid bit number. (S27). The control unit 404 outputs the control signal CON1, and sets the number of effective bits changed in step S27 as the number of effective bits limited by the bit number limiting unit 401 (S28).

  The state where the number of effective bits is limited in step S16 is when the quality of the transmission path is good. Therefore, even when the bit number limiting unit 401 limits the number of valid bits, the parity check is OK before the number of repetitions of error correction decoding reaches the maximum value. Therefore, steps S26 to S28 are not always necessary.

  However, depending on the case, the quality of the transmission path may suddenly deteriorate. When the quality of the transmission path deteriorates, the error correction capability of the error correction decoding unit 402 can be improved by the control unit 404 increasing the number of effective bits in steps S27 and S28. Thereby, error correction receiving apparatus 400 can decode received data in response to a dynamic change in the quality of the transmission path.

<Verification on Effectiveness of Operation of Error Correction Receiver 400>
FIG. 10 shows the relationship between the number of effective bits of the soft decision value and the error rate (BER). Specifically, FIG. 10 shows a simulation result of the relationship between the error rate (BER) in the noise ratio (Eb / No) per bit and the number of soft decision bits of the received data RD2.

  In FIG. 10, when there is a lot of noise (Eb / No = 3), the error rate deteriorates if the number of soft decision bits is reduced to 2 bits or 1 bit. On the other hand, when the noise is low (Eb / No = 9, Eb / No = 10), it can be seen that the error rate is almost constant even if the number of soft decision bits is reduced from 5 bits to 1 bit.

  That is, when the quality of the transmission path is good and the noise is low, even if the number of soft decision bits is reduced from 5 bits to 1 bit, the error rate does not change and the same error correction decoding result is obtained. Therefore, the number of effective bits of the soft decision value of the reception data RD2 input to the error correction decoding unit 402 may be reduced.

  Therefore, for example, in the effective bit number table TBL1 of FIG. 7, when the parity check is “OK”, the control unit 404 determines that the quality of the transmission path is good when the number of decoding iterations DT1 is small, and the The number of bits DT3 can be reduced.

  That is, the control unit 404 can appropriately determine an appropriate number of effective bits using the effective bit number table TBL1. In the example of FIG. 6, when the parity check is “OK” at the 0th repetition, the bit number limiting unit 401 fixes the lower 4 bits of the reception data RD2 to 0. Of the 5 bits of data calculated in the error correction decoding unit 402, 4 bits are 0 and fixed, so that power consumption can be reduced.

  The error correction decoding unit 402 uses a sum-product decoding method or a decoding method obtained by simplifying the sum-product decoding method (for example, a mini-sum decoding method) for decoding an LDPC code. The internal circuit of the error correction decoding unit 402 is configured mainly using an adder, for example.

  Therefore, when the multi-bit signal to be processed includes a bit fixed to “0”, a circuit for processing the fixed bit becomes unnecessary. Therefore, the power consumed by the circuit of the error correction decoding unit 402 is reduced.

  In FIG. 9, the control unit 404 determines the number of valid bits when processing the header of the received data, and therefore the number of valid bits can be reduced in the processing of the payload including the data body. Thereby, the effect of reducing power consumption increases.

  As described above, the error correction receiving apparatus 400 according to the present embodiment changes the effective number of soft decision bits according to the parity check result for the number of repetitions of the error correction decoding unit 402. As a result, the operation circuit of the error correction decoding unit 402 can be reduced, and the power consumption of the transmission / reception device 300 including the error correction reception device 400 can be reduced.

  In particular, when the transmission path quality is good, the error correction receiver 400 further reduces the power consumption by stopping the operation of the error correction decoding unit 402 and the parity check unit 403 in addition to reducing the power consumption by stopping the clock. Can be reduced.

  As mentioned above, although each embodiment was described with reference to drawings, this invention is not limited to this example. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  INDUSTRIAL APPLICABILITY The present invention is useful as a decoding device, a decoding method, and a wireless communication device that perform high-speed decoding by reducing the amount of decoding processing of received data according to the communication quality of the transmission path.

300 Transmission / Reception Device 301 Error Correction Encoder 302 Modulator 303 DAC
304 Transmission analog processing unit 305 PA unit 306 Antenna circuit 307 Reception analog processing unit 308 ADC
309 Demodulator 310 Error correction decoder 311 Data recognition unit 400 Error correction receiver 401 Bit number limiter 402 Error correction decoder 403 Parity check unit 404 Control unit 405 Clock generation unit 501 Column processing unit 502 Row processing unit

Claims (9)

A decoding device for decoding received data including a header,
An error correction decoding unit that performs error correction decoding of the soft decision value of the received data by iterative decoding;
Based on the output result of the error correction decoding, a data error detection unit for detecting the presence or absence of a data error;
A control unit that determines the number of effective bits of the received data to be subjected to error correction decoding based on the number of repetitions of iterative decoding in error correction decoding of the header and the detection result of presence or absence of the data error;
A decoding device comprising: The decoding device according to claim 1,
A bit number limiting unit that limits the number of effective bits of the soft decision value of the received data input to the error correction decoding unit,
The bit number limiter is
A decoding device that limits the number of effective bits of the soft decision value of the received data input to the error correction decoding unit according to the determined number of effective bits. The decoding device according to claim 2,
The bit number limiter is
A decoding device that fixes the least significant bit or a plurality of bits including the least significant bit to 0 among a plurality of bits constituting the soft decision value according to the determined number of effective bits. The decoding device according to any one of claims 1 to 3,
The controller is
An effective bit number table holding information representing a correspondence relationship between the number of repetitions of the iterative decoding process and the effective bit number;
The controller is
A decoding device that determines the effective bit number according to the effective bit number table. The decoding device according to any one of claims 1 to 4,
The controller is
In the error correction decoding for the payload of the received data, if the data error is detected even if the number of repetitions of iterative decoding exceeds a predetermined upper limit number, the number of effective bits is increased. A decoding device according to any one of claims 1 to 5,
The error correction decoding unit
A decoding device that performs error correction decoding on the input received data by iterative decoding using a low density parity check code or a turbo code. The decoding device according to any one of claims 1 to 6,
The data error detector is
A decoding device that detects the data error in the output of the error correction decoding unit by a parity check. A decoding method for decoding received data including a header,
Error correcting decoding the received data header by iterative decoding;
Detecting the presence or absence of a data error based on the output result of error correction decoding;
Determining the number of effective bits of the received data to be subjected to error correction decoding based on the number of repetitions of iterative decoding in error correction decoding of the header and the detection result of the presence or absence of the data error. Decryption method.   A wireless communication device including the decoding device according to claim 1.

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