JP5842017B2 - Signal analysis apparatus and signal analysis method - Google Patents

Description

  The present invention relates to a signal analysis apparatus and a signal analysis method for analyzing signal frequency, power, and the like.

  In general, there is an apparatus that receives a signal such as a radio wave emitted from a wireless device, etc., analyzes its frequency component and power, and measures the change with time. For example, the signal analysis device (signal analysis device) described in Patent Document 1 displays a spectrum indicating a frequency component within a range desired by the user on the display unit, or power within the range desired by the user. Is provided with a display control unit that displays a spectrogram indicating a change in the magnitude of the power on the display unit (see, for example, paragraphs [0008] and [0026] of Patent Document 1).

  By the way, the signal analyzing apparatus as described above, for example, uses a trigger signal when the signal under measurement (signal to be analyzed) input to the signal analyzing apparatus is converted into digital data and displayed on the display unit. Based on this, it is converted into digital data and a signal is displayed on the display unit. The trigger signal is generated by a signal generator connected to a signal analyzer such as a function generator.

JP 2009-250719 A

  However, there may be a difference between the input timing of a trigger signal to a control unit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array) in the signal analyzer and the timing of latching the trigger signal. The magnitude of this timing shift is determined by the operation clock of the control unit. That is, as the time resolution for the control unit to latch the trigger signal is lower, the deviation becomes larger. When such a deviation becomes large, for example, the actual measurement start time is delayed from the measurement start time of the signal assumed by the user.

  An object of the present invention is to provide a signal analysis apparatus and a signal analysis method capable of reducing the deviation of the measurement start time of the signal under measurement by reducing the deviation between the trigger signal input timing and the latch timing of the trigger signal. It is to provide.

  In order to achieve the above object, the signal analyzing apparatus according to claim 1 is configured such that an RF unit 10 that receives a signal under measurement, a clock generation unit 41 that generates a clock, and an input trigger signal that is input are input to the clock signal. A delay unit 42 that generates a delay trigger signal by delaying it by a time shorter than a cycle; and a latch unit 43 that outputs each latch trigger signal obtained by latching the input trigger signal and the delay trigger signal with the clock; The determination unit 44 for determining the input timing of the input trigger signal based on the output latch trigger signal, and the measured signal received by the RF unit at the input timing of the input trigger signal determined by the determination unit And an analysis processing unit 20 for starting signal measurement.

  In such a signal analysis device, the delay unit generates a delayed trigger signal obtained by delaying the input trigger signal by a time shorter than the clock cycle. Therefore, the latch trigger signal having a resolution equivalent to the delay amount higher than the clock is generated. Can be generated. Thereby, the determination part can determine the input timing of an input trigger signal with the resolution. As a result, the difference between the input trigger signal input timing and the input trigger signal latch timing can be reduced.

The signal analysis device according to claim 2 is the signal analysis device according to claim 1, wherein the delay unit includes a plurality of delay elements connected in series, and the latch unit receives the input trigger signal. A first latch element that outputs a latch trigger signal obtained by latching, and a plurality of second latch elements that output a latch trigger signal obtained by latching the delay trigger signals respectively output from the plurality of delay elements; It is characterized by having.
As a result, the resolution can be increased by the number of delay elements.

  The signal analysis device according to claim 3 is the signal analysis device according to claim 2, wherein the determination unit is configured to input the trigger signal according to the number of the latch trigger signals obtained by the clock by the latch unit. The timing is determined.

The signal analysis device according to claim 4 is the signal analysis device according to claim 3, wherein the value of the digital data of each latch trigger signal obtained by the latch unit is from the value of the minimum digit to the value of the maximum digit. If the value fluctuates twice or more in the meantime, the determination unit includes a correction unit that performs correction to replace the value with a predetermined value that fluctuates once or less between the minimum digit value and the maximum digit value. It is characterized by having.
As a result, a value that should not be detected and fluctuates twice or more between the minimum digit side and the maximum digit is replaced with a value that should be detected, and the detected value falls within a predetermined allowable error range. Can be a value.

  In order to achieve the above object, the signal analysis method according to claim 5 receives the signal under measurement, generates a clock, and delays the input trigger signal to be input in a time shorter than the period of the clock. A delayed trigger signal is generated, and the latch trigger signal obtained by latching the input trigger signal and the delayed trigger signal with the clock is output. Based on the output latch trigger signal, the input trigger signal input timing is output. And measurement of the signal under measurement received by the RF unit is started at the input timing of the determined input trigger signal.

  As described above, according to the signal analysis device and the signal analysis method according to the present invention, the deviation in the measurement start time of the signal under measurement is reduced by reducing the deviation between the input timing of the trigger signal and the latch timing of the trigger signal. be able to.

FIG. 1 is a block diagram showing a functional configuration of the signal analyzing apparatus according to the first embodiment of the present invention. FIG. 2 is a block diagram illustrating a hardware configuration of the signal analysis apparatus according to the present embodiment. FIG. 3 shows sampling timing when the control unit generates digital data of the RF signal based on the trigger signal. FIG. 4 is a block diagram illustrating a functional configuration of the control unit. FIG. 5 shows an example of input data and output data of the delay element. FIG. 6 is a flowchart showing processing of the control unit. FIG. 7 shows a signal generated by the latch unit when the input timing of the input trigger signal is smaller than the delay time 90 ° from t1. FIG. 8 shows a signal generated by the latch unit when the input timing of the input trigger signal is smaller than the delay time 180 ° from t1. FIG. 9 shows a signal generated by the latch unit when the input timing of the input trigger signal is smaller than the delay time 270 ° from t1. FIG. 10 shows a signal generated by the latch unit when the input timing of the input trigger signal is smaller than the delay time 360 ° from t1. FIG. 11 is a graph conceptually showing the effect of this embodiment. 12A and 12B show the relationship between the trigger actual input time and the trigger deviation detection amount. FIG. 13 is another diagram illustrating the state of FIG. 12B in which an overlapping region is generated by two transition regions. FIG. 14 shows a state where an overlapping region is generated by three transition regions. FIG. 15 is a table showing possible values that the output from the latch unit can take.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1. First embodiment

1) Configuration of Signal Analysis Device FIG. 1 is a block diagram showing a functional configuration of a signal analysis device (SA: Signal (Spectrum) Analyzer) according to the first embodiment of the present invention. The signal analysis apparatus SA includes an RF unit 10, an A / D conversion unit 21, an analysis processing unit 20, a display unit 30, and a control unit 40 in a casing 50. The casing 50 includes an operation unit 45 and a trigger signal. An input terminal 48 is provided.

  The RF unit 10 includes a sweep unit 11, a local signal generation unit 12, and a mixer unit 13, and receives an input RF signal.

The local signal generation unit 12 receives an instruction of the center frequency f _c of the measurement frequency from the control unit 40 via the sweep unit 11, oscillates a local signal of the local frequency (f _c + f _IF ), and sends it to the mixer unit 13. It is like that.

The mixer unit 13 mixes the input RF signal and the local signal (or reference frequency signal) of the local frequency (f _c + f _IF ), and converts them to a signal of the intermediate frequency (f _IF ± ΔF _Max / 2). Thus, the intermediate frequency signal is sent to the A / D converter 21.

The A / D conversion unit 21 converts the intermediate frequency signal (frequency: f _IF ± ΔF _Max / 2) output from the RF unit 10 into digital data with a predetermined clock from the control unit 40.

  The control unit 40 controls the entire signal analysis device SA. In particular, the control unit 40 receives a trigger signal input from the trigger signal input terminal 48 and starts measurement processing (analysis processing) of the signal under measurement by the RF unit 10 and the analysis processing unit 20 as will be described later. The timing is controlled. The control unit 40 controls the display timing of the signal analysis result on the display unit 30.

  The analysis processing unit 20 includes, for example, an original data storage unit 22, a processing unit 23, a detection unit 24, a log conversion unit 25, and a storage unit 26, and performs signal analysis processing on an input RF signal.

  The original data storage unit 22 stores the digital data (amplitude value) output from the A / D conversion unit 21 in the memory area with the measurement frequency and the elapsed time of the clock as an address by using a write signal at almost the same timing as the clock. It is supposed to be. The stored digital data is so-called time domain data.

  The processing unit 23 receives the measurement frequency fv and the measurement time tv received from the operation unit 45, and reads the corresponding measurement frequency and time domain data (digital data) of the clock elapsed time from the original data storage unit 22. It has become.

  Then, the processing unit 23 performs, for example, FFT (Fast Fourier Transform) processing on the received time domain data at a predetermined time interval to convert it into frequency domain data, and within the measurement bandwidth ΔF specified by the operation unit 45. Each frequency component and its size are calculated with a desired resolution bandwidth (RBW).

  At this time, the processing unit 23 stores, as original data, time domain data corresponding to the time window ΔT (ΔT ≧ Δt) at each processing timing from the time domain data of the measurement frequency, where Δt is the time interval of the timing of the FFT processing. The data is read from the unit 22 and subjected to FFT processing.

  Then, the processing unit 23 repeatedly performs the FFT processing until the measurement time reaches tv while shifting the processing timing by the time interval T by one interval Δt. That is, the FFT processing unit 23 reads out time domain data between ± ΔT / 2 centered on the time position (address) m × Δt at a timing of m × Δt (for example, m is 1 to tv / Δt). The FFT calculation is repeated until m = tv / Δt.

  The time window ΔT is a time sufficient to convert time domain data into frequency domain data. In an extreme example, even if time domain data that is less than one cycle is converted into frequency domain data, the frequency may not be specified with good resolution. Note that the timing time interval Δt may be the same cycle as the clock of the A / D converter 21.

  In the configuration illustrated in FIG. 1, the analysis processing unit 20 performs the FFT process. However, this is merely an example, and the processing method of the analysis processing unit 20 is not limited to the FFT process. For example, the analysis processing unit 20 may perform modulation analysis, or may perform processing such as Power vs Time, Frequency vs Time, Phase vs Time, and the like. That is, these analysis processing methods can also be applied to the present invention. Note that these analysis processing methods are methods that can be understood by those skilled in the art of signal analysis devices, and therefore their details are omitted.

  The detector 24 converts the magnitude of each frequency component into an effective value, an average value, or a peak value and outputs it. Hereinafter, this is referred to as “power”. The log conversion unit 25 compresses the output from the detection unit 24 logarithmically and sends it to the storage unit 26.

  For example, the storage unit 26 stores the power of the corresponding frequency component in a memory area in which one address is the measurement frequency fv and the other address is the elapse of the measurement time tv.

  The display unit 30 displays the power of each component of the measurement frequency stored in the storage unit 26 as a color parameter, for example, at coordinates with the measurement frequency as the vertical axis and the measurement time as the horizontal axis.

  FIG. 2 is a block diagram showing a hardware configuration of the signal analyzing apparatus SA according to the present embodiment.

  The signal analyzing device SA mainly includes an RF / IF circuit 10 ′, an ADC (AD converter) 21 ′, and an FPGA (Field Programmable Gate Array) 65.

  The RF / IF circuit 10 ′ is a circuit that mainly realizes the RF unit 10. Further, the RF / IF circuit 10 ′ is configured to receive an RF signal as a signal under measurement and also to receive the signal under measurement, for example, by a wired connection.

  The ADC 21 ′ is a circuit that realizes the above-described AD conversion unit 21. The FPGA 65 is a circuit that implements each element of the analysis processing unit 20 other than the AD conversion unit 21 and the control unit 40.

2) Delay time due to the internal path of the signal analyzer SA Due to the internal path of the signal analyzer SA, a delay time occurs between the input to the signal analyzer SA and the processing by the FPGA 65 and ADC 21 ′. For example RF signal RF / IF circuit 10 'reception processing is input to is performed, ADC 21' delay time t _a before it is input to occur. On the other hand, the trigger signal input through the trigger signal input terminal 48 to the signal analyzer SA delay time t _b until the input is generated in FPGA65.

  Here, it is assumed that the RF signal and the trigger signal as shown in FIG. 3 are input to the RF / IF circuit 10 ′ and the trigger signal input terminal 48, respectively. At this time, the sampling timing when the ADC 21 ′ generates digital data by the clock of the FPGA 65 is considered.

  The sampling timing is indicated by black circles (sampling points) on the RF signal and the trigger signal. As can be seen from this figure, the timing at which the sampling point captures (latches) each trigger signal may be delayed from the actual rise timing of the trigger signal.

t _d indicates the time difference between the actual rise timing of the trigger signal and the latch timing. This t _d is determined by the sampling frequency, that is, the clock frequency of the FPGA 65 that latches the trigger. For example, when the clock frequency is 100 MHz, the maximum Max (t _d ) can be expressed by the following equation.

Max (t _d ) = (1 / 100M) + t _s = 10 [ns] + t _s

t _s is a set-up time, the time it takes to finish rising from the start of the rise of the trigger signal.

From the above equation, the above t _d takes the following range.

t _s ≤t _d <10 [ns] + t _s

It is not known which value t _d takes in this range until the trigger signal is input. This value t _d is determined by the temporal accuracy of the trigger signal. When the latch frequency (clock frequency) is 100 MHz, an error of ± 5 [ns] occurs. This error distribution is considered to be a uniform distribution with an average value of 5 [ns].

Frequency of the latch, i.e. without changing the clock frequency of the FPGA65, if it is possible to improve the temporal accuracy of the trigger signal, it is possible to reduce the t _d, it can be expected to be able to measure signal with high accuracy.

The difference between the delay time t _a from the input end of the RF signal analyzer SA to the input end of the ADC 21 ′ and the delay time t _b from the trigger signal input terminal 48 of the trigger signal to the input end of the FPGA 65. Since t _a -t _b is corrected by a separate means, this is not mentioned in this specification.

3) Means and Method for Realizing High Resolution of Trigger Signal FIG. 4 is a block diagram showing a functional configuration of the control unit 40. FIG. 6 is a flowchart showing processing of the control unit 40. Below, the structure of the control part 40 is demonstrated in order of the step of each process of the flowchart shown in FIG.

  The control unit 40 includes a clock generation unit 41, a delay unit 42, a latch unit 43, and a determination unit 44.

  The clock generator 41 generates an operation clock for the FPGA 65 (hereinafter referred to as a clock clk) (step 101). As described above, the clock clk has a frequency on the order of MHz, such as 100 MHz.

  Delay unit 42 includes a plurality of delay elements connected in series. In the present embodiment, for example, four delay elements 42a, 42b, 42c, and 42d are provided. The delay elements 42a to 42d are realized by various known circuits, and include, for example, a PLL (Phase Locked Loop) circuit, a latch circuit such as a D-FF (Delay Flip-Flop), or an inverter circuit.

  FIG. 5 shows an example of input data and output data of the delay element. The delay element outputs data at a timing delayed by m [s] from the input timing.

  The delay elements 42a to 42d generate the delay trigger signals s_1, s_2, s_3, and s_4 (see FIG. 4) by delaying the input trigger signal trg by a time shorter than the cycle of the clock clk (step 102). The delay trigger signals s_1, s_2, s_3, and s_4 are delayed from the input trigger signal trg by m, 2m, 3m, and 4m [s], respectively. Here, when n is the number of delay elements, the following formula (a) or (b) needs to be satisfied in order to obtain a resolution higher than the clock cycle.

m × n ≦ 1 / clk (a)
m ≦ 1 / clk and m × n ≦ 1 / clk (b)
(N: natural number)

  The latch unit 43 latches the input trigger signal trg and the delayed trigger signals s_1, s_2, s_3, and s_4 output from the delay unit 42 with the clock clk, respectively. , trg_ltc4 is output (step 103)

  Specifically, the latch unit 43 includes a plurality of latch elements. There are five latch elements 43a, 43b, 43c, 43d, 43e, one more than the number of delay elements 42a-42d. For example, a D-FF element is used as the latch element.

The input trigger signal trg is input to the D terminal of the latch element 43a.
The delay trigger signal s_1 from the delay element 42a is input to the D terminal of the latch element 43b.
The delay trigger signal s_2 from the delay element 42b is input to the D terminal of the latch element 43c.
The delay trigger signal s_3 from the delay element 42c is input to the D terminal of the latch element 43d.
The delay trigger signal s_4 from the delay element 42d is input to the D terminal of the latch element 43e.
The clock clk is input to the clock input terminals of the latch elements 43a to 43e.

  Respective latch trigger signals trg_ltc0, trg_ltc1, trg_ltc2, trg_ltc3, trg_ltc4 obtained by latching by the latch elements 43a to 43e are input to the determination unit 44 as signals to be determined.

  The determination unit 44 determines the input timing of the trigger signal trg based on the acquired determination target signal (step 104). The control unit 40 starts processing by the analysis processing unit 20, that is, measurement of the signal under measurement, at the input timing of the high-resolution input trigger signal trg obtained by the determination unit 44.

  The determination unit 44 acquires the latch trigger signals trg_ltc1 to trg_ltc4 output from the remaining four latch elements 43b to 43e as signals to be determined, particularly when the latch element 43a latches the first input trigger signal trg. .

4) Signal generated by the latch unit 43 a) When the input timing tg of the input trigger signal trg is after the rising timing t1 of the clock clk and is smaller than the delay time 90 ° from t1

  FIG. 7 shows a signal generated by the latch unit 43 when the input timing tg of the input trigger signal trg is after the rising timing t1 of the clock clk and is smaller than the delay time 90 ° from t1.

  As shown in the figure, the delayed trigger signals s_1, s_2, s_3, and s_4 are signals that are sequentially delayed from the input trigger signal trg for a predetermined time. The latch elements 43a to 43e latch the input trigger signal trg and the delayed trigger signals s_1, s_2, s_3, and s_4 at the next rising t2 after the timing t1 of the clock clk. Then, latch trigger signals trg_ltc0, trg_ltc1, trg_ltc2, trg_ltc3, trg_ltc4 as shown in the lower part of FIG. 7 are generated. Since the delay trigger signal s_4 is delayed from the timing t1, it is not latched at the timing t1. As a result, the value “01111” is output as the signal to be determined.

  Here, since the latch trigger signal trg_ltc0 is always latched at t2, the minimum digit is always “1”. The determination unit 44 pays attention to only the first four digits, sets “01111” to “0111”, and sets this determination target signal to “3”, for example.

  The determination unit 44 generates a determination result corresponding to “3” using, for example, a logic circuit (not shown). The determination result corresponding to “3” means that the input timing tg of the input trigger signal trg is t1 ≦ tg <t1 + 90 °.

  b) When the input timing tg of the input trigger signal trg is a delay time of 90 ° or more from the rising timing t1 of the clock clk and smaller than 180 °

  FIG. 8 shows a signal generated by the latch unit 43 when the input timing tg of the input trigger signal trg is 90 ° or more from the rising timing t1 of the clock clk and smaller than 180 °.

  In this case, since the delay trigger signals s_3 and s_4 are delayed from the timing t1, they are not latched at the timing t1. Therefore, an output “00111” is obtained. As described above, the determination target signal “0011” = “2” is output by paying attention to only the first four digits.

  The determination unit 44 generates a determination result corresponding to “2”. The determination result corresponding to “2” means that the input timing tg of the input trigger signal trg is t1 + 90 ° ≦ tg <t1 + 180 °.

  c) When the input timing tg of the input trigger signal trg is a delay time of 180 ° or more from the rising timing t1 of the clock clk and smaller than 270 °

  In this case, as shown in FIG. 9, since the delayed trigger signals s_2, s_3, and s_4 are delayed from the timing t1, they are not latched at the timing t1. Therefore, an output “00011” is obtained. As described above, the determination target signal “0001” = “1” is output by paying attention to only the first four digits.

  The determination unit 44 generates a determination result corresponding to “1”. The determination result corresponding to “1” means that the input timing tg of the input trigger signal trg is t1 + 180 ° ≦ tg <t1 + 270 °.

  d) When the input timing tg of the input trigger signal trg is a delay time of 270 ° or more from the rising timing t1 of the clock clk and smaller than 360 °

  In this case, as shown in FIG. 10, since the delayed trigger signals s_1, s_2, s_3, and s_4 are delayed from the timing t1, they are not latched at the timing t1. Therefore, an output “00001” is obtained. Similar to the above, the determination signal “0000” = “0” is output by paying attention to only the first four digits.

  The determination unit 44 generates a determination result corresponding to “0”. The determination result corresponding to “0” means that the input timing tg of the input trigger signal trg is t1 + 270 ° ≦ tg <t1 + 360 °.

  As described above, in this embodiment, the delay unit 42 generates the delayed trigger signals s_1, s_2, s_3, and s_4 obtained by delaying the input trigger signal by a time shorter than the cycle of the clock clk. A latch trigger signal having a high resolution corresponding to the delay amount can be generated. Thereby, the determination part 44 can determine the input timing of the input trigger signal trg with the resolution. As a result, the difference between the input timing of the input trigger signal trg and the latch timing of the input trigger signal trg can be reduced, and the control unit 40 measures the signal under measurement at the input timing of the high-resolution trigger signal trg. Can start. That is, the error in the measurement start time can be reduced.

  In the present embodiment, high resolution can be obtained without using an expensive ADC or FPGA device having a high-speed operation clock of GHz level.

  FIG. 11 is a graph conceptually showing the effect of this embodiment. The horizontal axis indicates the actual trigger input time (actual input timing), and the vertical axis indicates the trigger detection time. This graph shows that four triggers are detected while one trigger indicated by a broken line is input and a trigger is detected. That is, since n = 4 in this embodiment, it is possible to obtain a resolution that is four times the resolution of the clock clk. By increasing the number n of delay elements, higher resolution can be obtained. As n which a real product can take, it is n = 8-16, for example.

In particular, in a communication system using MIMO (Multiple-Input Multiple-Output) technology, an error in transmission timing transmitted from two transmission antennas is defined as 65 ns or less. In addition, an error (measurement error) of a measurement device that receives the signal (for example, a signal analysis device SA as in the present embodiment) is defined by the standard as 25 ns. As described above, if the time difference t _d can be sufficiently reduced, the measurement error range of 25 ns can be sufficiently cleared.

  2. Second embodiment

  Next, a second embodiment of the present invention will be described. In the following description, the same hardware and functional blocks included in the signal analysis apparatus SA according to the first embodiment will be simplified or omitted, and different points will be mainly described.

  FIG. 12A shows the relationship between the trigger actual input time and the trigger deviation detection amount in the first embodiment. The horizontal axis corresponds to the rising shape of the input trigger signal. The vertical axis corresponds to the added value (determined signal) of the outputs from the latch elements 43b to 43e when the number n of delay elements is 4 as described above.

  The transition area S indicated by hatching is an area indicating the steepness of the rising edge of the trigger signal. The steeper the horizontal width of the transition area S is expressed. As shown in FIG. 12B, the slower the trigger signal rises, the wider the transition region S becomes. If the transition region S is too wide, a region S ′ where the transition regions S overlap is generated. In this overlapping region S ′, the obtained bit becomes unstable. For example, in the overlapping region S ′ where the transition regions S1 and S2 overlap, the value within the range of the vertical arrow, that is, four values “0000”, “0001”, “0010”, and “0011” can be taken.

  FIG. 13 is another diagram showing the state of FIG. 12B. For example, even if the value that should be detected originally is “0001”, 0 and 1 are not fixed in the transition regions S1 to S4, and both 0 and 1 can be determined. Therefore, four values of “0000”, “0001”, “0010”, and “0011” may be detected at the timing indicated by the vertical broken line.

  Of these four values, “010” of “0010” is a value that fluctuates twice between the value of the minimum digit and the value of the maximum digit. This is a value that should not be detected in the algorithm of the present embodiment. The value that should be detected is “0011”, “0000”, or when the number of delay elements is n = 8, such as “0011111”, “00000011”, etc. It is a value that fluctuates once or less until.

  FIG. 15 is a table showing values that the outputs from the latch elements 43b to 43e can take. The portion indicated by hatching is a value that should not be detected originally. In the case of “0010”, the result is that the output value 0 of the latch element 43d that should be detected transitions to 1, and the output value 1 of the latch element 43e that should be detected transitions to 0. This situation is a situation in which both the output values of the latch elements 43d and 43e are unstable and the bits are inverted from each other.

  Of course, the bit of one of these output values may be inverted. For example, when the value to be detected is “0001” and the output value 0 of only the latch element 43d is inverted to 1, the detected value is “0011”. When the output value 1 of only the latch element 43e is inverted to 0, the detected value becomes “0000”.

  From the above, when the value to be detected is “0001”, for example, the above four values including “0010” can be taken on the circuit. However, since “0010” is not a value that should be detected originally, the determination unit 44 sets three ranges “0000” = “0”, “0001” = “1”, and “0011” = “2”. It can be estimated that Specifically, in the table shown in FIG. 15, “0010” = “1 ′” is replaced with “0001” = “1”. That is, when “0010” is detected, it is assumed that it is within an allowable error range of “1” ± 1.

  Note that the determination unit 44 may replace “0010” with “0011” or “0000”.

  As described above, the determination unit 44 performs correction to replace a value that should not be detected originally with any one of the values that should be detected. In this case, the determination unit 44 functions as a “correction unit”. This correction can be realized by either a logic circuit or software.

  The resolution of the conventional technique is m [s] (= 1 / clk). Further, when the number of transition regions S overlapping at a certain timing is x (: positive integer) and n is the number of delay elements, the resolution can be expressed by the following equation. In the following formula, when n> x, the resolution can be improved.

  m / n ± x × m / 2n [s]

  In the above example, a resolution of m / 4 ± 2 × m / (2 × 4) [s] (= 1 / (clk × 4) ± 1 / (clk × 4)) can be obtained. That is, the resolution is improved as compared with the conventional case.

  As illustrated in FIG. 15, the determination unit 44 is not limited to the case where “0010” is detected, and when “0101” or “1010” is detected, “0101” = “2 ′” is set to “0011”. = Replace with “2” and replace “1010” = “3 ′” with “0111” = “3”.

  In the above example, the number of transition areas S that overlap at a certain timing is two. However, for example, as illustrated in FIG. 14, a case where the number of transition areas S that overlap at a certain timing is three is also assumed. At the timing indicated by the broken line, the output value of the latch unit 43 among the eight of “0001”, “0000”, “0011”, “0010”, “0111”, “0101”, “0110”, “0100” is Anything is ready. Even in such a case, the resolution is improved to m / 4 ± 3 × m / (2 × 4) [s] (= 1 / (clk × 4) ± 3 / (clk × 8)). .

  3. Other embodiments

  The present invention is not limited to the embodiment described above, and other various embodiments can be realized.

  In the signal analysis device SA according to the above embodiment, an FPGA is used. However, instead of this, another PLD (Programmable Logic Device) may be used, or a CPU (Central Processing Unit) may be used. Good.

  As the delay element, for example, a coaxial delay line may be used in addition to the element shown in the above embodiment. Also, a system having a variable delay amount such as a trombone coaxial delay line can be used.

  In the above embodiment, the delay amount by each delay element of the delay unit 42 is equal, but the delay unit may include at least two delay elements having different delay amounts.

  It is also possible to combine at least two feature portions among the feature portions of each embodiment described above.

DESCRIPTION OF SYMBOLS 10 ... RF part 10 '... RF / IF circuit 20 ... Analysis processing part 40 ... Control part 41 ... Clock generation part 42 ... Delay part 42a-42d ... Delay element 43 ... Latch part 43a-43e ... Latch element 44 ... Determination part 48 ... Trigger signal input terminal SA ... Signal analysis device

Claims (2)

An RF unit (10) for receiving a signal under measurement;
A clock generator (41) for generating a clock;
A delay unit (42) having a plurality of delay elements connected in series and generating an input trigger signal by delaying an input trigger signal by a time shorter than the period of the clock;
A first latch element that outputs a latch trigger signal obtained by latching the input trigger signal with the clock, and a latch trigger signal obtained by latching the delay trigger signal output from each of the plurality of delay elements with the clock. A latch unit (43) having a plurality of second latch elements that output
A determination unit (44) for determining an input timing of the input trigger signal according to the number of the latch trigger signals obtained by the clock by the latch unit ;
An analysis processing unit (20) for starting measurement of the signal under measurement received by the RF unit at the input timing of the input trigger signal determined by the determination unit ;
When the value of the digital data of each latch trigger signal obtained by the latch unit is a value that fluctuates twice or more between the minimum digit value and the maximum digit value, the determination unit sets the value to the minimum digit The signal analysis apparatus which has a correction | amendment part which performs correction | amendment substituted by the predetermined value which fluctuates 1 time or less between the value of 1 and the value of the largest digit A signal analysis method using a signal analyzer,
Receive the signal under measurement,
Generate clock,
A delay trigger signal is generated by delaying an input trigger signal inputted by a plurality of delay elements connected in series in a time shorter than the cycle of the clock,
Of the latch unit having a first latch element and a plurality of second latch elements, the first latch element outputs a latch trigger signal obtained by latching the input trigger signal with the clock;
A latch trigger signal obtained by latching the delay trigger signal output from each of the plurality of delay elements with the clock by the plurality of second latch elements in the latch unit;
According to the number of latch trigger signals obtained by the clock by the latch unit , determine the input timing of the input trigger signal,
Wherein at the input timing of the determined the input trigger signal, to initiate the measurement of the received signal to be measured,
When the value of the digital data of each latch trigger signal obtained by the latch unit is a value that fluctuates twice or more between the value of the minimum digit and the value of the maximum digit, the value is minimized in the determination step. A signal analysis method, wherein correction is performed by replacing with a predetermined value that fluctuates once or less between a digit value and a maximum digit value .

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