JP5825272B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a Cu wiring electrode and a method for manufacturing the same.

  Conventionally, Al (aluminum) -based materials have been used as wiring materials for semiconductor devices used for power applications and the like. Conventional semiconductor devices are operated at temperatures below 200 ° C. However, as semiconductor devices are required to operate at high temperatures, reliability of the semiconductor devices is reduced due to mutual reaction, oxidation, etc. at high temperatures above 200 ° C. As a wiring material that replaces Al, Cu (copper) that can be used at a high temperature of 200 ° C. or more has attracted attention (for example, see Patent Document 1).

  The wiring electrode is required to have a certain thickness from the viewpoints of heat dissipation and wiring resistance. In particular, it is desirable that the wiring electrode be thick in a semiconductor device that operates at a high temperature. When Cu or a metal containing Cu is used as the wiring electrode for high temperature, the Cu wiring electrode is formed thick, so that the surface step of the semiconductor element provided with the Cu wiring electrode becomes large, and the organic resin is coated. Poor filling of organic resin is likely to occur. When a hole portion due to poor filling is formed between the organic resin film and the Cu wiring electrode, charges are accumulated in the hole portion, leading to destruction of the semiconductor element. Therefore, there is a problem that the reliability of the semiconductor device is lowered.

  Therefore, a conventional semiconductor device uses a structure in which a convex portion of a P-SiN film is provided at the skirt portion of the Cu wiring electrode and the filling failure of the organic resin film is suppressed at the skirt portion of the Cu wiring electrode (for example, Patent Document 2).

International Publication No. 2007-108439 JP 2006-108233 A, p. 3-4

  In a conventional semiconductor device using a Cu wiring electrode, in order to suppress poor filling of the organic resin film at the skirt of the Cu wiring electrode, a P-SiN film is used to provide a protrusion at the skirt of the Cu wiring electrode. Since the formation process was necessary, there was a problem that the manufacturing process of the semiconductor device was complicated.

  The present invention has been made to solve the above-described problems, and suppresses the filling failure of the Cu wiring electrode skirt portion of the organic resin film covering the Cu wiring electrode by a simple manufacturing process, and is reliable. An object is to provide a highly reliable semiconductor device.

The semiconductor device according to the present invention includes a semiconductor element, a first metal layer mainly comprising Cu provided on a part of the semiconductor element, and Cu mainly provided on the upper surface of the first metal layer. A second metal layer, and an organic resin covering the side surface of the first metal layer and the side surface of the second metal layer, and the side surface of the first metal layer is the second metal layer It protrudes from the side surface of the bottom, and the density of the first metal layer is different from the density of the second metal layer .

According to the invention, the side surface of the first metal layer is, protrudes from the side surface of the bottom of the second metal layer, the density of the first metal layer, by which is different from the density of the second metal layer, single net the skirt organic resins of defective filling of the wiring electrode can be obtained a highly reliable semiconductor device with suppressed at Do manufacturing process.

It is sectional drawing of the left half which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until formation of JTE area | region of the silicon carbide Schottky barrier diode used for Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until back surface barrier metal layer formation of the silicon carbide Schottky barrier diode used for Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until formation of the 2nd Cu layer of the silicon carbide Schottky barrier diode used for Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until removal of the resist mask of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method before formation of the surface protective film of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing for demonstrating the etching of Cu wiring electrode among the manufacturing methods of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until formation of the surface protective film of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing to which the bottom of the Cu wiring electrode was expanded for demonstrating the filling defect improvement of an organic resin film using the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method until back surface external output electrode formation of the semiconductor device in Embodiment 1 of this invention. It is the SEM photograph image which expanded the skirt part of Cu wiring electrode of the semiconductor device in Embodiment 1 of this invention.

Embodiment 1 FIG.
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described. In this embodiment, a case where an n-type silicon carbide Schottky barrier diode is used as a semiconductor element of a semiconductor device will be described as an example.

  FIG. 1 is a cross-sectional view for illustrating the configuration of the semiconductor device according to the first embodiment, and shows a left half of a cross section when the semiconductor element is an n-type silicon carbide Schottky barrier diode. That is, the cross section of the semiconductor device in this embodiment has a structure in which FIG.

  In a silicon carbide Schottky barrier diode which is a semiconductor element constituting the semiconductor device shown in FIG. 1, a drift layer 2 which is an n-type silicon carbide layer is formed by epitaxial growth on a main surface of a substrate 1 made of n-type silicon carbide. Is formed.

  On the surface layer side of the drift layer 2, the ring-shaped guard ring region 3 extends further across the position of the end of the Schottky electrode 6, and is a junction termination extension region at a predetermined distance from the end of the Schottky electrode 6. (Junction Termination Extension) regions 4 are formed adjacent to each other.

  The Schottky electrode 6 is formed on the inner peripheral side from a position covering a part of the guard ring region 3 on the surface of the drift layer 2 in which the guard ring region 3 and the JTE region 4 are formed. A surface barrier metal layer 7 and a third metal layer 9 are formed on the upper surface of the Schottky electrode 6. Furthermore, on the upper surface of the third metal layer 9, in order from the top, a second Cu layer 11 that is a second metal layer that is a surface external output electrode and a second Cu layer 11 that is a surface external output electrode. The first Cu layer 10 which is a seed layer for forming the first metal layer is formed. That is, in this embodiment, the Cu wiring electrode is composed of the first metal layer and the second metal layer provided on the upper surface of the first metal layer, both of which are formed on the upper surface of the third metal layer 9. Is formed. The outer peripheral portions of the Schottky electrode 6, the surface barrier metal layer 7, the third metal layer 9, the first Cu layer 10, and the second Cu layer 11 stacked on the surface of the drift layer 2, drift The surface of the layer 2 is covered with a surface protective film 12 made of an organic resin.

  Here, the first Cu layer 10 is a first metal layer containing Cu as a main component, and the second Cu layer is a second metal layer containing Cu as a main component. The first metal layer and the second metal layer may be Cu or a Cu alloy, and may further contain impurities.

  An ohmic electrode layer 5 is formed on the back surface of the substrate 1, and a back barrier metal layer 8 is formed on the back surface of the ohmic electrode layer 5. A rear external output electrode 13 is formed on the rear surface of the rear barrier metal layer 8. With the above structure, the semiconductor device shown in FIG. 1 is obtained.

  In the configuration of the semiconductor device shown in FIG. 1, a portion excluding the third metal layer 9, the first Cu layer 10, the second Cu layer 11, the surface protective film 12, and the back surface external output electrode 13 is a semiconductor element. In the present embodiment, it is an n-type silicon carbide Schottky barrier diode. That is, in the present embodiment, an n-type silicon carbide Schottky barrier diode, which is a semiconductor element, is provided with a Cu wiring electrode composed of the first Cu layer 10 and the second Cu layer 11, and the first Cu layer 10, the side surface of the second Cu layer, the upper surface corner portion, the surface of the drift layer 2, which is the surface of the semiconductor element, the side surface of the Schottky electrode 6, the side surface of the surface barrier metal layer 7, and the upper surface corner portion. The side surface of the third metal layer 9 is covered with the surface protective film 12. Further, a back external output electrode 13 is formed on the back surface of the n-type silicon carbide Schottky barrier diode that is a semiconductor element.

  Here, the semiconductor device using the silicon carbide Schottky barrier diode of the present embodiment shown in FIG. 1 as a semiconductor element has a skirt portion of a Cu wiring electrode composed of a first Cu layer 10 and a second Cu layer 11. 17, the protrusion 15 of the first Cu layer 10 is provided. In FIG. 1, a skirt 17 is a region surrounded by a broken line in the first Cu layer 10 and the second Cu layer 11, and an enlarged view is shown in FIG. Due to the protrusion 15 provided at the skirt portion 17 of the Cu wiring electrode, the side surface 18 at the bottom of the second Cu layer 11 is recessed from the side surface of the first Cu layer 10 at the bottom of the second Cu layer 11. Yes. In FIG. 1, the side surface 18 at the bottom of the second Cu layer 11 is a side surface near the point where the second Cu layer 11 contacts the first Cu layer 10 at the skirt portion 17 of the Cu wiring electrode. That is, in the present embodiment, the side surface of the first Cu layer 10 protrudes from the side surface 18 at the bottom of the second Cu layer 11.

  In the present embodiment, the protrusion 15 can suppress the filling failure of the skirt portion 17 of the Cu wiring electrode. That is, it is possible to improve the filling failure of the surface protective film 12 of the skirt portion 17 of the Cu wiring electrode without using an inorganic insulating film such as a P-SiN film.

  Next, a method for manufacturing a semiconductor device using the silicon carbide Schottky barrier diode according to the first embodiment of the present invention as a semiconductor element will be described. 2 and 3 are sectional views showing a method for manufacturing the silicon carbide Schottky barrier diode according to the first embodiment of the present invention. 2 and 3 also show the left half of the cross section of the silicon carbide Schottky barrier diode.

FIG. 2 is a cross-sectional view showing a manufacturing method up to formation of JTE region 4 of the silicon carbide Schottky barrier diode constituting the semiconductor device in the present embodiment. Substrate 1 is a silicon carbide substrate having a high concentration of n-type (n ⁺ -type) impurity density. In the present embodiment, the substrate 1 is made of silicon carbide. For example, when a silicon Schottky barrier diode is used as a semiconductor element, a substrate made of silicon is used.

First, drift region 2 which is a silicon carbide layer having a low concentration n-type (n ⁻ -type) impurity density is formed on the main surface of substrate 1 by an epitaxial growth method.

  Next, a resist pattern is patterned by photolithography, and Al ions are implanted into the guard ring region 3 using the resist pattern as a mask.

  Further, Al ions having an impurity concentration lower than that of the guard ring layer 3 are implanted into a position of the JTE region 4 continuous on the outer peripheral side of the guard ring region 3.

  Next, annealing (heat treatment) is performed to activate Al ions implanted in the guard ring region 3 and the JTE region 4. By annealing at a high temperature of 1500 ° C. or higher, for example, 1700 ° C., Al ions are activated, and the p-type guard ring region 3 and the p-type JTE region 4 are formed.

  Next, Ni is deposited on the back surface of the substrate 1 by, for example, sputtering, and annealed at about 1000 ° C. by lamp annealing to form an NiSi ohmic electrode layer 5 on the back surface.

  FIG. 3 is a cross-sectional view showing a manufacturing method until formation of back surface barrier metal layer 8 of the silicon carbide Schottky barrier diode constituting the semiconductor device in the present embodiment. A Schottky electrode 6 is formed on the surface of the drift layer 2 by using, for example, a sputtering method using a target such as Ti, Mo, or Ni. The film thickness is 50 nm to 500 nm. The Schottky electrode 6 is formed on the entire surface of the drift layer 2.

  Further, TiN is formed as a surface barrier metal layer 7 on the entire surface of the Schottky electrode 6 by, for example, sputtering. The film thickness is desirably 10 nm or more. The surface barrier metal layer 7 is applied for the purpose of preventing diffusion of the wiring electrode material from the wiring electrode to the Schottky electrode 6.

  Next, a chemical-resistant, low-resistance back barrier metal layer 8 is formed on the back surface of the ohmic electrode layer 5 by, for example, sputtering. The back barrier metal layer 8 is formed of, for example, TaN, TiN, TiWN, WN, WSiN alone or a laminate of Ti.

  Next, an etching mask 14 made of a resist pattern by photolithography is formed on the surface of the surface barrier metal layer 7. The etching mask 14 is formed so as to cover the upper portion of the surface barrier metal layer 7 to be left like a region surrounded by a dotted line in FIG. When the metal of the surface barrier metal layer 7 is, for example, TiN, the surface barrier metal layer 7 is wet-etched with a hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution or hydrochloric acid.

  Further, when the metal of the Schottky electrode 6 is, for example, Ti, the Schottky electrode 6 is wet-etched with a solution diluted with hydrofluoric acid. After the wet etching, the etching mask 14 is removed by a wet process using an organic solvent or an ashing process using oxygen plasma.

Next, heat treatment (sinter) is performed to stabilize characteristics such as the barrier height (φ _b ) of the Schottky junction.

  Thereby, the structure shown in the cross section of FIG. 3 excluding the dotted line portion which is the etching mask 14 is obtained. Further, the structure shown in FIG. 3 is a structure of a silicon carbide Schottky barrier diode which is a semiconductor element of the present embodiment. That is, the semiconductor element used in this embodiment so far is obtained.

  4 to 10 are cross-sectional views for explaining a method of manufacturing a semiconductor device by forming a Cu wiring electrode and a surface protective film on the silicon carbide Schottky barrier diode which is the semiconductor element obtained in FIG. is there. 4 to 10 also show the left half of the cross section of the semiconductor device.

  FIG. 4 is a cross-sectional view showing a manufacturing method up to formation of the second Cu layer 11 of the semiconductor device in the present embodiment. First, a third metal layer 9 such as Ti is formed on the upper surface of the surface barrier metal layer 7 formed in FIG.

  In FIG. 4, the third metal layer 9 is inserted to improve the adhesion between the surface barrier metal layer 7 and the Cu wiring electrode.

  Since the third metal layer 9 is also formed on the surface of the drift layer 2 as shown in FIG. 4, the third metal layer 9 formed on the surface of the drift layer 2 is directly on the surface of the drift layer 2. The formation of Cu wiring electrodes is prevented. By providing the third metal layer 9 between the drift layer 2 and the Cu wiring electrode, the third metal layer 9 also functions as a barrier metal related to Cu, and the drift that is silicon carbide from the Cu wiring electrode. Cu can be prevented from diffusing into the layer 2.

  That is, the third metal layer 9 is provided for improving adhesion and preventing Cu diffusion. However, for example, depending on the material of the surface barrier metal layer 7, sufficient adhesion may be ensured even without the third metal layer 9. Further, due to a manufacturing method different from the present embodiment (for example, the first Cu film 10 is lifted off only on the upper surface of the surface barrier metal layer 7), Cu diffusion into the drift layer 2 may not be a problem. In such a case, the third metal layer 9 may be omitted.

  In the present embodiment, the third metal layer 9 is provided on the surface of the drift layer 2 and the upper surface of the surface barrier metal layer 7, and Cu plating is formed on the upper surface of the third metal layer 9 (second Cu layer). The first Cu layer 10 which is a Cu or Cu alloy film as a base of 11) is deposited by a PVD method such as thermal evaporation, electron beam evaporation and sputtering, or a metal CVD method using a gas such as an organic metal. The thickness is 100 to 1000 nm.

  In the present embodiment, the first Cu layer 10 is indispensable in order to form the protruding portion 15 of the first Cu layer 10 at the skirt portion 17 of the Cu wiring electrode as described later. The second Cu layer 11 is formed on the upper surface of the first Cu layer 10 by plating. To use Cu plating as the Cu wiring electrode, a Cu or Cu alloy film is used as a base. Is desirable.

  When the Cu plating film is formed directly on the surface barrier metal layer 7 that does not contain Cu as a main component without forming the first Cu layer 10, the Cu plating film formation reflects the components of the surface barrier metal layer 7. Therefore, the film quality of Cu plating film formation is deteriorated. Specifically, voids are formed, the resistance of Cu plating film formation increases, or the in-plane distribution of Cu plating film formation deteriorates.

  In the present embodiment, by using Cu or a Cu alloy film as the first Cu layer 10, Cu plating film formation with excellent film quality that does not cause the above problems can be obtained. That is, the present embodiment can be realized by the first Cu layer 10, but the use of the first Cu layer 10 also has an effect that a Cu plating film having a good quality can be formed as a Cu wiring electrode.

  Further, when Cu plating film formation is performed directly on the surface of the surface barrier metal layer 7, the adhesion between the surface barrier metal layer and the Cu plating film formation may deteriorate depending on the material of the surface barrier metal layer 7. In the embodiment, a Cu wiring electrode having high adhesion can be obtained.

  Next, a resist mask 20 is formed by patterning the resist on a portion of the upper surface of the first Cu layer 10 where the second Cu layer 11 is not desired to be formed by applying, exposing, and developing the resist. That is, the resist patterned so that the second Cu layer 11 is formed on the center side on the first Cu layer 10 and is opened on the first Cu layer 10 so as not to be formed on the peripheral side. A mask 20 is formed.

  It is desirable that the height of the resist mask 20 be lower than the height of the second Cu layer 11 to be deposited next by plating. If the height of the resist mask 20 is lower than that of the second Cu layer 11, the upper surface corner portion of the second Cu layer 11 is surrounded by a one-dot chain line in FIG. 4 reflecting the shape of the side wall of the resist mask 20. This is because the roundness 16 is less likely to be attached to the upper surface corner portion.

  If the height d of the resist mask 20 is greater than 0.5 μm, for example, the thickness difference d of the second Cu layer 11, a certain degree of roundness 16 is formed.

  In FIG. 4, the side wall of the resist mask 20 is tapered. When the resist mask 20 is thick, a forward taper as shown in FIG. 4 is likely to occur during exposure and development of the resist. However, even if the resist mask 20 is thin, for example, the effect of the present embodiment can be obtained even if it is not tapered.

  That is, when the thickness of the Cu wiring electrode is increased, the thickness of the resist mask 20 is increased, and the side wall of the resist mask 20 is easily tapered in the process. When the side wall of the resist mask 20 is tapered in the forward direction, the side surface of the Cu wiring electrode is also tapered in the reverse direction, and the filling of the organic resin film in the bottom portion 17 is likely to occur. Therefore, the effect of using this embodiment is greater as the Cu wiring electrode is thicker.

  Next, the second Cu layer 11 is formed by plating. The Cu plating film is formed on the upper surface of the first Cu layer 10 in a region where the resist mask 20 is not formed, and the shape is shaped along the side wall of the resist mask 20.

  Since Cu is deposited isotropically from the position where the Cu plating film exceeds the height of the resist mask 20, the shape of the upper corner portion of the second Cu layer 11 is rounded, and the surface protection film 12 is formed. No local stress is generated when it is coated.

  If the thickness of the Cu plating film that is the second Cu layer 11 is, for example, about 5 to 100 μm, poor filling of the skirt 17 is likely to occur.

  According to such a method, although the degree of roundness may not be sufficient at the upper surface corner portion of the second Cu layer 11, a certain degree of roundness 16 is provided to suppress poor resin filling at the upper surface corner portion. it can.

  The second Cu layer 11 may be Cu or Cu alloy having a density different from that of the first Cu layer 10, or may be Cu or Cu alloy having the same density.

  FIG. 5 is a cross-sectional view showing the manufacturing method until the removal of the resist mask 20 of the semiconductor device in the present embodiment.

  In FIG. 5, the resist mask 20 in FIG. 4 is removed by an organic solvent or oxygen plasma treatment.

  FIG. 6 is a cross-sectional view showing the manufacturing method until the surface protective film 12 of the semiconductor device in this embodiment is formed.

  First, wet etching is performed on the first Cu layer 10 using an acid solution such as sulfuric acid, hydrochloric acid, acetic acid, phosphoric acid, nitric acid, hydrofluoric acid, or a mixed solution thereof, or a solution obtained by adding hydrogen peroxide to these solutions as an etching solution. To do. Here, it is necessary to etch all of the first Cu layer 10 on the drift layer 2.

  When the first Cu layer 10 on the drift layer 2 is wet-etched, the exposed regions of the first Cu layer 10 and the second Cu layer 11 on the surface barrier metal layer 7 are also exposed to the wet etching solution. Therefore, in the structure shown in FIG. 5, the portion where the first Cu layer 10 and the second Cu layer 11 are exposed to the wet etching solution is etched to some extent.

  Here, when the selection ratio during the etching of the first Cu layer 10 and the second Cu layer 11 is 1, that is, when the densities of the first Cu layer 10 and the second Cu layer 11 are equal, The etching depths of the etched regions of the first Cu layer 10 and the second Cu layer 11 in FIG. 5 are the same distance from the surface exposed to the wet etching solution.

  FIG. 7A is a cross-sectional view for explaining before and after etching when the etching depth is equal to the thickness of the first Cu layer 10. The first Cu layer 10 and the second Cu layer 11 are etched in the direction of the arrow from the surface exposed to the etching solution in FIG.

  In this case, it can be seen that the protrusion 15 of the first Cu layer 10 is formed at the skirt 17 of the Cu wiring electrode. That is, the side surface of the first Cu layer 10 protrudes from the side surface 18 at the bottom of the second Cu layer 11.

  Next, when the etching ratio of the second Cu layer 11 is larger than 1 with respect to the first Cu layer 10, that is, when the density of the first Cu layer 10 and the second Cu layer 11 is different. To do. In this case, the etching depths of the etched regions of the first Cu layer 10 and the second Cu layer 11 in FIG. 5 are different distances from the surface exposed to the wet etching solution. In this case, for example, etching as shown in FIG. 7B can be performed on FIG. 7A.

  That is, when the density of the first Cu layer 10 and the second Cu layer 11 is different, the etching rate is changed.

  In addition, since the density of the 1st Cu layer 10 and the 2nd Cu layer 11 is dependent on the process conditions of each formation process, each density can be changed by changing each process condition.

  Further, in order to change the etching rate, there is a method in which impurities other than Cu are included in the first Cu layer 10. Specifically, a selectivity ratio of 1.1 or more can be realized by including in the first Cu layer 10 impurities other than 0.1% or more of Cu.

  When the selection ratio is greater than 1, the shape of the protrusion 15 can be changed to a desired shape depending on the selection ratio and etching conditions.

  For example, the shape of the protrusion 15 can be increased by increasing the selection ratio. If the selection ratio is 1.1 or more, it is easy to increase the shape of the protrusion 15.

  For example, the shape of the protrusion 15 can be increased by increasing the etching time.

  Furthermore, by increasing the thickness of the first Cu layer 10, the shape of the protrusion 15 can be increased.

  By combining these conditions, the protrusion 15 having a desired shape can be formed.

  Next, the third metal layer 9 is removed by hydrofluoric acid using the first Cu layer 10 and the second Cu layer 11 as a mask.

  Further, the surface shape of the second Cu layer 11 is modified by CMP (Chemical Mechanical Polishing) for the purpose of surface planarization.

  FIG. 8 is a cross-sectional view showing a manufacturing method up to the formation of the surface protective film 12 of the semiconductor device in the present embodiment.

  The surface of the drift layer 2 in which the Schottky electrode 6, the surface barrier metal layer 7, the third metal layer 9, the first Cu layer 10, and the second Cu layer 11 are stacked is a polyimide film, for example. The surface protective film 12 is formed by spin coating or the like so as to be covered with the surface protective film 12.

  At this time, filling failure tends to occur at the skirt portion of the Cu wiring electrode. In the skirt portion of the Cu wiring electrode, it is necessary to fill the shape of the corner formed by the surface barrier metal layer 7 and the side surface of the Cu wiring electrode with the surface protective film 12 as shown in FIG. When the surface protective film 12 is formed by coating, it is difficult to apply sufficiently to the skirt portion of the Cu wiring electrode that becomes the corner. Further, for example, when the surface protective film 12 is formed by a vapor deposition method or the like, if the side surface of the Cu wiring electrode is reversely tapered, the surface protective film 12 is not deposited on the skirt of the Cu wiring electrode. As described above, when the Cu wiring electrode is covered with the surface protective film 12, a filling defect tends to occur in the skirt portion of the Cu wiring electrode.

  FIG. 9 shows an enlarged cross-sectional view of the skirt portion of the Cu wiring electrode for explaining that filling failure can be improved by using this embodiment. In FIG. 9, the taper of the Cu wiring electrode and the third metal layer 9 are omitted for simplicity.

First, when the skirt portion of the Cu wiring electrode does not protrude, the corner between the Cu wiring electrode made of the first Cu layer 10 and the second Cu layer 11 and the surface barrier metal layer 7 as shown in FIG. the part P _1, cavities such as the region surrounded by a dotted line in the figure is generated. As the volume of the hole portion increases, the amount of charge accumulated in the hole portion increases, and the reliability of the semiconductor device decreases.

  Using this embodiment, as shown in FIG. 9B, the protruding portion 15 having a smaller volume than the hole portion (the region surrounded by the dotted line in FIG. 9B) in the case of FIG. 9A is formed. Suppose it is made. In this case, since the protrusion 15 occupies a part of the volume of the hole part in the case of FIG. 9A, the volume of the hole part in FIG. 9B is the hole of FIG. The volume is obtained by subtracting the volume of the protrusion 15 from the volume of the part. Therefore, the volume of the hole portion can be made smaller by the protrusion 15 than in the case of FIG. 9A in which this embodiment is not used, and the amount of charge accumulated in the hole portion can be reduced. Deterioration can be suppressed.

  In the case of FIG. 9B, the effect of reducing the volume of the hole is obtained regardless of the shape of the protrusion 15.

Next, as shown in FIG. 9C, the case where the protruding portion 15 having a larger volume than the hole portion without the protruding portion 15 is formed will be described. In this case, the projecting portion 15, since that is all occupy a structure in which the cavity surrounded by the dotted line, cavity for generating the corners P ₁ can be completely eliminated. However, depending on the shape of the protrusion 15, the corner portion P ₂ composed of the surface of the first Cu layer 10 and the side surface of the second Cu layer 11, or the side surface of the first Cu layer 10 and the surface barrier metal layer 7. as such, a new corner occurs corners P ₃ comprising a surface. Therefore, even if the filling failure of the corner portion P ₁ can be prevented, the filling failure of the organic resin may occur in the corner portion P ₂ or the corner portion P ₃ .

FIG. 9D shows a cross-sectional shape when an organic resin is applied. Since the organic resin is viscous, the liquid level of the organic resin as shown by the one-dot chain line in FIG. Become. In FIG. 9D, the organic resin is on the upper side of the alternate long and short dash line. The organic resin in the applied state as shown in FIG. 9D is filled up to the bottom of the Cu wiring electrode by spin coating. Here, the corner P ₁ , the corner P ₂ , and the corner P Consider the ease of filling in _{3 with} an organic resin.

One of the parameters of the ease of filling with the organic resin is the distance from the organic resin at the coating stage. The distances from the corner portion P ₁ , the corner portion P ₂ , and the corner portion P ₃ to the organic resin are distances indicated by h ₁ , h ₂ , and h ₃ in FIG. 9D, respectively. As can be seen from FIG. 9 (d), h ₁ is larger than h ₂ and h ₃ . That is, the corners P ₂ and P ₃ are closer to the organic resin than the corners P ₁ . Therefore, it can be said that the corner portion P ₂ and the corner portion P ₃ are more easily filled with the organic resin than the corner portion P ₁ . Therefore, if this embodiment is used, the organic resin filling failure in the case of FIG. 9A is less likely to occur, the organic resin filling failure in the conventional case (in FIG. 9A) is suppressed, and the semiconductor device The effect which suppresses the reliability fall of this is acquired.

Further, even if the corner portion P ₂ is defective filling of the organic resin produced in the present embodiment, the distance from the semiconductor device for farther than the corner portions P _1, the influence on the semiconductor device of the charge accumulated prior Low compared to

Further, one of the parameters for ease of filling with the organic resin is the angle of the corner. Angle of the corner P ₂ and corners P ₃ is greater than the angle of the corner portions P _1, consisting of the corners P ₁ easily fill the organic resin.

  Thus, if this Embodiment is used, the filling defect of the organic resin in the skirt part of Cu wiring electrode can be suppressed. Even if a vacancy portion is generated in the case where this embodiment is used, the volume of the vacancies can be reduced as compared with the case where this embodiment is not used, and the amount of accumulated charge can be reduced. Can be suppressed.

  In the present embodiment, the filling defect of the surface protection film 12 is caused because the protrusion 15 of the first Cu layer 10 is provided at the skirt of the Cu wiring electrode which is likely to cause a filling defect and easily becomes a hole. Can be suppressed. That is, since the skirt portion of the Cu wiring electrode that is likely to be poorly filled is filled in advance by the protruding portion of the first Cu layer 10, sufficient coverage of the surface protective film 12 is obtained, and the first Cu layer 10 and The filling failure of the skirt portion 17 of the Cu wiring electrode made of the second Cu layer 11 can be suppressed.

  In FIG. 8, a part of the surface of the second Cu layer 11 excluding the upper surface corner is opened by etching using a resist pattern by photolithography as a mask. Then, the surface protection film 12 made of an organic resin film is formed by baking at a temperature of about 300 to 400 ° C.

  FIG. 10 is a cross-sectional view showing the manufacturing method up to the formation of the backside external output electrode 13 of the semiconductor device in the present embodiment.

  The back external output electrode 13 is provided on the back surface of the back barrier metal layer 8, and is formed of a laminated film of metallized film including Ti and Cu, Ti and Cu, or the like. Since Ti is provided for improving the adhesive strength of the laminated film, it can be omitted. Further, the surface shape of the rear surface external output electrode 13 is modified by CMP for the purpose of surface planarization.

  Through the above steps, the semiconductor device shown in FIG. 1 in the present embodiment is obtained.

  FIG. 11 shows an SEM photographic image of a cross section near the skirt portion 17 of the Cu wiring electrode of the semiconductor device manufactured using this embodiment. The first Cu layer 10 was made of Cu containing Al. That is, the first Cu layer 10 and the second Cu layer 11 have a selection ratio at the time of etching so that the etching rates are different.

  From FIG. 11, it can be seen that the protrusion 15 of the first Cu layer 10 is provided at the skirt portion 17 of the Cu wiring electrode composed of the first Cu layer 10 and the second Cu layer 11. That is, the side surface of the first Cu layer 10 protrudes from the side surface 18 at the bottom of the second Cu layer 11.

  According to the present embodiment, since the projecting portion 15 is provided at the skirt portion 17 of the Cu wiring electrode composed of the first Cu layer 10 and the second Cu layer 11, the filling failure of the organic resin film at the skirt portion 17 is prevented. Can be suppressed. If a hole portion which is a poorly filled region is formed in the skirt portion 17 of the Cu wiring electrode, charges accumulate in the hole portion and lead to destruction of the semiconductor element, so that the reliability of the semiconductor device is lowered. In the present embodiment, a phenomenon in which a hole is formed in the skirt portion 17 and charge does not accumulate, or even if it occurs, the amount of charge is small, so that the reliability of the semiconductor device can be improved.

  According to the present embodiment, since the skirt portion 17 of the Cu wiring electrode is made of the first Cu layer 10, a process for forming a P-SiN film or the like is not required, and thus a simple manufacturing process and cost-saving method Thus, a highly reliable semiconductor device in which the filling failure of the organic resin film in the skirt portion 17 of the Cu wiring electrode is suppressed can be obtained.

  In this embodiment, the method for manufacturing a semiconductor device is not limited to the above method. In other words, this embodiment mode is merely an example of a method for manufacturing the structure shown in FIG. 1, and if the structure shown in FIG. 1 is finally obtained, a method other than that described in the description of this embodiment mode is obtained. May be used.

  In the present embodiment, the roundness 16 is formed also in the upper corner portion of the second Cu layer 11, but the roundness 16 may not be formed in the upper corner portion. That is, even if filling failure occurs in the upper surface corner portion and charge is generated in the hole portion of the upper surface corner portion, the distance from the drift layer 2 that is the silicon carbide layer is farther than that of the skirt portion 17, so The decrease in reliability due to is small. Therefore, if the filling failure of the skirt portion 17 is suppressed, a certain effect can be obtained by the present embodiment.

  Therefore, the second Cu layer 11 may be formed by a PVD method, a CVD method, or the like, instead of the plating method.

  In this embodiment, the semiconductor element is an n-type silicon carbide Schottky barrier diode, but it goes without saying that it may be p-type.

  Further, although silicon carbide is used as a semiconductor material in this embodiment mode, other semiconductor materials may be used.

  In particular, wide band gap semiconductors that require high-temperature operation require the use of Cu wiring electrodes that can operate under high-temperature environments. It is further desired to improve the filling failure.

  Silicon carbide is attracting attention as a material for next-generation high voltage power devices, and operation under high voltage is required. The electric charge at the skirt portion 17 of the Cu wiring electrode lowers or makes the breakdown voltage of the semiconductor device low. However, under a high breakdown voltage, the electric field applied to the skirt portion 17 of the Cu wiring electrode also increases, causing device breakdown and instability. It becomes easy to be connected to an operation. Therefore, the effect of using this embodiment in order to realize a stable high breakdown voltage operation using silicon carbide is great.

  In this embodiment mode, a Schottky barrier diode is used as a semiconductor element. It goes without saying that other devices such as a diode may be used. As long as there is a structure in which Cu is used as a wiring electrode material and is covered with an organic resin film, the present embodiment can be used for any semiconductor element.

  1 substrate 2 drift layer 3 guard ring region 4 JTE region 5 ohmic electrode layer 6 Schottky electrode 7 surface barrier metal layer 8 back barrier metal layer 9 third metal layer 10 first Cu Layer, 11 second Cu layer, 12 surface protective film, 13 back external output electrode, 14 etching mask, 15 protrusion, 16 rounded, 17 skirt, 18 bottom side, 20 resist mask.

Claims (11)

A semiconductor element;
A first metal layer mainly composed of Cu provided on a part of the semiconductor element;
A second metal layer mainly composed of Cu provided on the upper surface of the first metal layer;
An organic resin covering the side surface of the first metal layer and the side surface of the second metal layer;
With
The side surface of the first metal layer protrudes from the side surface of the bottom of the second metal layer ;
The semiconductor device , wherein the density of the first metal layer is different from the density of the second metal layer . The semiconductor device according to claim 1, wherein the first metal layer includes an impurity of 0.1% or more. The semiconductor device according to claim 2, wherein the impurity is at least one of Ni, Al, Mn, Zn, Sn, Pb, Fe, and Mg. The semiconductor device, the semiconductor device according to any one of claims 1 to 3, characterized in that a wide band gap semiconductor element. The semiconductor device includes a semiconductor device according to any one of claims 1 to 4, characterized in that a silicon carbide device. The semiconductor device, the semiconductor device according to any one of claims 1 to 5, characterized in that a carbide Schottky barrier diode. Forming a first metal layer mainly composed of Cu on the semiconductor element;
Forming a resist pattern having an open center on the first metal layer on top surfaces of the semiconductor element and the first metal layer;
Forming a second metal layer mainly composed of Cu in the opened region of the resist pattern;
Removing the resist pattern;
Wet etching each exposed region of the first metal layer and the second metal layer;
Coating the side surface of the first metal layer and the side surface of the second metal layer with an organic resin;
A method for manufacturing a semiconductor device comprising: The method for manufacturing a semiconductor device according to claim 7 , wherein the etching rates of the first metal layer and the second metal layer are different. The wet etching phosphoric acid, sulfuric acid, nitric acid, a method of manufacturing a semiconductor device according to claim 7 or 8, characterized by using any one or more etchant acetate. The first metal layer, a method of manufacturing a semiconductor device according to any one of claims 7 to 9, characterized in that it is formed by PVD or CVD. The method of manufacturing a semiconductor device according to any one of claims 7 to 10, wherein the second metal layer is formed by plating.

Images