JP5810972B2 - Semiconductor device, analog / digital conversion circuit test method - Google Patents

Description

  The present invention relates to a test method for a semiconductor device and an analog / digital conversion circuit.

  An operation test of an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit) is performed based on a digital signal (output code) supplied from the A / D conversion circuit by supplying an analog signal to the A / D conversion circuit. (For example, refer to Patent Documents 1 to 3). For example, a test apparatus (tester) in which an A / D conversion circuit is connected as a device under test (DUT) uses a voltage value of an analog signal supplied to the A / D conversion circuit. The input voltage range is changed from the minimum value Vmin to the maximum value Vmax. The A / D conversion circuit outputs a digital signal corresponding to the voltage value of the analog signal. The test apparatus stores a digital signal output from the A / D conversion circuit in a memory inside the apparatus. When storing the digital signal corresponding to the input voltage range in the memory, the test apparatus reads all the digital signals from the memory, calculates an error from the ideal value based on the digital signal, and calculates A / The quality of the D conversion circuit is determined.

JP-A-2-218222 JP 2001-77691 A JP 2001-339304 A

  By the way, the amount of data (output code) to be stored is limited in the capacity of the memory installed in the test apparatus. This limitation on the amount of data becomes a factor that limits the test of the highly accurate A / D conversion circuit. For example, in a semiconductor device in which a plurality of A / D conversion circuits are formed, the number of A / D conversion circuits that are simultaneously measured is limited by the memory capacity.

  According to one aspect of the present invention, a first analog / digital conversion circuit that performs analog / digital conversion on a first analog signal and outputs a first digital signal, and a second analog signal that is different from the first analog signal. A result of comparison between a second analog / digital conversion circuit that performs analog / digital conversion of an analog signal and outputs a second digital signal, a difference between the first digital signal and the second digital signal, and a reference value And a determination circuit for generating a determination signal according to the above.

  According to one aspect of the present invention, it is possible to easily test a plurality of A / D conversion circuits.

It is a schematic block diagram of a test system. It is a partial block circuit diagram of a semiconductor device. It is a circuit diagram of a determination circuit. It is explanatory drawing of a test. (A), (b) is explanatory drawing which shows the outline | summary of a test. (A), (b) is explanatory drawing which shows the outline | summary of a test. (A), (b) is explanatory drawing which shows the outline | summary of a test. It is a flowchart of a test. It is a partial block circuit diagram of another semiconductor device.

Hereinafter, an embodiment will be described with reference to FIGS.
As shown in FIG. 1, a semiconductor device 10 includes a first analog / digital conversion circuit (hereinafter referred to as A / D conversion circuit) 11 and a second analog / digital conversion circuit (hereinafter referred to as A / D conversion circuit) 12. Have. The A / D conversion circuits 11 and 12 each convert an analog signal into a multi-bit digital signal and output it. The A / D conversion circuit 11 outputs a digital signal Da corresponding to an analog signal supplied via the external terminal T1. The A / D conversion circuit 12 outputs a digital signal Db corresponding to an analog signal supplied via the external terminal T2. The internal circuit 13 includes a processing circuit such as a CPU, for example, and executes predetermined processing based on the digital signals Da and Db output from the A / D conversion circuits 11 and 12.

  Further, the semiconductor device 10 has a determination circuit 14 connected to the A / D conversion circuits 11 and 12. The determination circuit 14 outputs a determination signal ST having a level corresponding to the digital signals Da and Db output from the A / D conversion circuits 11 and 12. The determination signal ST is output to the outside of the semiconductor device 10 through, for example, the external terminal T3.

The semiconductor device 10 is connected to the test apparatus 100 for testing the A / D conversion circuits 11 and 12. The test apparatus 100 is connected to the terminals T1 to T3 of the semiconductor device 10.
The test apparatus 100 outputs analog signals A1 and A2 in the input voltage range of the A / D conversion circuits 11 and 12, respectively. The minimum value of the input voltage range of the A / D conversion circuits 11 and 12 is Vmin, and the maximum value is Vmax. In order to simplify the description, the minimum value Vmin is set to 0 V (zero volt). The test apparatus 100 outputs an analog signal A1 having a minimum value Vmin in the input voltage range of the A / D conversion circuits 11 and 12. Further, the test apparatus 100 outputs an analog signal A2 having an intermediate voltage Vc (= Vmax / 2) in the input voltage range of the A / D conversion circuits 11 and 12.

  Then, the test apparatus 100 sequentially changes (for example, increases) the voltage values of the analog signals A1 and A2 in the input voltage range of the A / D conversion circuits 11 and 12. Further, the test apparatus 100 keeps the difference between the voltage values of the analog signals A1 and A2 (difference voltage) at 1/2 (or -1/2) in the input voltage range of the A / D conversion circuits 11 and 12. The voltage values of both analog signals A1 and A2 are changed.

The determination circuit 14 calculates the difference between the digital signal Da output from the A / D conversion circuit 11 and the digital signal Db output from the A / D conversion circuit 12. Then, the determination circuit 14 compares the difference value with the reference value, and outputs a determination signal ST having a level corresponding to the comparison result. For example, the determination circuit 14 outputs an H level determination signal ST when the difference value matches the reference value, and outputs an L level determination signal ST when the difference value does not match.

  The test apparatus 100 receives the determination signal ST output via the external terminal T3, and determines the characteristics (linearity) of the A / D conversion circuits 11 and 12 according to the level of the determination signal ST. For example, the test apparatus 100 determines that the linearity of the A / D conversion circuits 11 and 12 is good (“OK”) according to the determination signal ST at the H level, and is defective (“ NG ").

  Note that the test apparatus 100 performs A / D conversion on the voltage values of the analog signals A1 and A2 so that quantization errors in the digital signals Da and Db of the A / D conversion circuits 11 and 12 do not affect the determination of linearity. It is preferable to change in accordance with the quantization unit (digit) of the circuits 11 and 12. The test apparatus 100 changes the voltage values of the analog signals A1 and A2 so that the least significant bit (or least quantization bit) (LSB: Least Significant Bit) of the digital signals Da and Db changes. This voltage value is 1LSB. Therefore, the intermediate voltage Vc is a voltage value obtained when the analog signals A1 and A2 are changed by 1 LSB in the middle of the input voltage range of the A / D conversion circuits 11 and 12.

  For example, in the case of 4-bit A / D conversion circuits 11 and 12, the digital signals Da and Db take code values from [0000] to [1111]. This code value is expressed in binary. The test apparatus 100 sets the voltage value of the intermediate voltage Vc to a value whose code value corresponds to [1000].

  Accordingly, the A / D conversion circuits 11 and 12 respectively output digital signals Da and Db corresponding to different voltage ranges in the input voltage range. For example, when the A / D conversion circuit 11 outputs the digital signal Da corresponding to the characteristics in the voltage range from the minimum voltage Vmin to the intermediate voltage (= Vmax / 2), the A / D conversion circuit 12 outputs the intermediate voltage To the maximum voltage Vmax, the digital signal Db corresponding to the characteristics in the voltage range is output.

  The determination circuit 14 generates a determination signal ST based on the digital signals Da and Db generated in the A / D conversion circuits 11 and 12 according to the characteristics of different voltage ranges. As described above, the determination circuit 14 calculates the difference between the digital signals Da and Db, and compares the difference value with the reference value. That is, the determination circuit 14 compares the digital signals Da and Db according to characteristics in different voltage ranges in the A / D conversion circuits 11 and 12.

  For example, when the A / D conversion circuit 11 outputs the digital signal Da of [0000] to [0111] according to the change of the analog signal A1, the A / D conversion circuit 12 [1000] according to the change of the analog signal A2. ] To [1111] digital signal Db is output. The difference between the two digital signals Da and Db is constant [1000] regardless of the analog signals A1 and A2.

  The difference between the digital signals output from the two A / D conversion circuits with good linearity corresponds to the difference between the voltage values of the analog signals supplied to the two A / D conversion circuits. In this embodiment, the value is constant (= [1000]) in the input voltage range of the two A / D conversion circuits.

On the other hand, when the linearity is not good in at least one of the two A / D conversion circuits, the difference between the digital signals output from the two A / D conversion circuits is not a constant value.
The characteristics of the two A / D conversion circuits formed on one chip are the same. For this reason, when analog signals with the same voltage value are supplied to two A / D conversion circuits, the difference between the digital signals output from each of them may be a constant value. However, the difference between the digital signals output from the two A / D conversion circuits by analog signals in different voltage ranges is not a constant value.

  The determination circuit 14 compares the difference X between the digital signals Da and Db output from the two A / D conversion circuits 11 and 12 with the analog signals A1 and A2 in different voltage ranges, respectively, and a constant value (reference value). A determination signal ST is generated according to the result. The level of the determination signal ST corresponds to the characteristics (good / bad linearity) of the two A / D conversion circuits 11 and 12. Therefore, the characteristics (linearity) of the two A / D conversion circuits 11 and 12 can be determined based on the level of the determination signal ST.

Next, the configuration of the determination circuit 14 will be described.
As illustrated in FIG. 2, the determination circuit 14 includes a subtracter 21, a comparator 22, and an output circuit 23.

  The A / D conversion circuit (noted as “ADC”) 11 outputs, for example, 4-bit digital signals Da3 to Da0. The digital signal Da3 is the most significant bit (MSB), and the digital signal Da0 is the least significant bit (LSB). Similarly, the A / D conversion circuit 12 outputs, for example, 4-bit digital signals Db3 to Db0.

  The subtracter 21 subtracts the digital signals Da3 to Da0 output from the A / D conversion circuit 11 from the digital signals Db3 to Db0 output from the A / D conversion circuit 12, and the subtraction result digital signals X3 to X0. Is output.

  The comparator 22 is connected to the register 24. The register 24 is supplied with the reference digital signals R3 to R0 from the number of bits equal to the number of bits of the digital signals X3 to X0 output from the subtractor 21. The register 24 generates a reference digital signal having a value of “1” or “0” by connecting a node to the wiring of the high potential voltage VDD level or the low potential voltage GND, for example, directly or via a resistance element.

  The comparator 22 compares the digital signals X3 to X0 output from the subtractor 21 with the reference digital signals R3 to R0 generated by the register 24, and outputs a 1-bit signal S1 corresponding to the comparison result. .

  The output circuit 23 outputs a determination signal ST corresponding to the output signal S1 of the comparator 22. For example, the output circuit 23 outputs a determination signal ST having a level obtained by logically inverting the output signal S1 of the comparator 22.

As shown in FIG. 3, the subtractor 21 includes inverter circuits 310 to 313 and adders 320 to 323 corresponding to the number of bits of the digital signals Da and Db.
The inverter circuit 310 outputs a signal S10 having a level obtained by logically inverting the digital signal Da0. Similarly, the inverter circuits 311 to 313 output signals S11 to S13 having levels obtained by logically inverting the digital signals Da1 to Da3, respectively.

The first adder 320 is supplied with the least significant bit digital signal Db0 and the output signal S10 of the inverter circuit 310 corresponding to the least significant bit digital signal Da0.
The first adder 320 is a full adder and includes exclusive OR circuits (XOR gates or ExOR gates) 41 and 42, AND circuits (AND gates) 43 and 44, and an OR circuit (OR gate) 45. doing. The XOR gate 41 outputs a signal S21 corresponding to the exclusive OR operation result of the digital signal Db0 and the signal S10. The XOR gate 42 outputs a digital signal X0 corresponding to the exclusive OR operation result of the signal S21 and the carry-in signal CI. The carry-in signal CI for the first adder 320 is set to a logical value “1”. The AND gate 43 outputs a signal S22 corresponding to the logical product operation result of the digital signal Db0 and the signal S10. The AND gate 44 outputs a signal S23 corresponding to the logical product operation result of the signal S21 and the carry-in signal CI. The OR gate 45 outputs a carry-out signal CO corresponding to the logical sum operation result of the signals S22 and S23.

  The second and third adders 321 and 322 are configured in the same manner as the first adder 320. For this reason, the same reference numerals as those of the first adder 320 are assigned to the second and third adders 321 and 322. The carry-out signal output from the first adder 320 corresponding to the lower bits is supplied to the second adder 321 as a carry-in signal. The second adder 321 outputs a digital signal X1 and a carry-out signal corresponding to the corresponding digital signal Db1, the signal S11, and the carry-in signal. The carry-out signal output from the second adder 321 corresponding to the lower bits is supplied to the third adder 322 as a carry-in signal. The third adder 322 outputs a digital signal X2 and a carry-out signal corresponding to the corresponding digital signal Db2, the signal S12, and the carry-in signal.

  The fourth adder 323 has XOR gates 46 and 47. The XOR gate 46 outputs a signal S24 corresponding to the exclusive OR operation result of the digital signal Db3 and the signal S13. The XOR gate 47 outputs a digital signal X3 corresponding to the exclusive OR operation result of the signal S24 and the carry-in signal (carry-out signal output from the third adder 322). That is, the XOR gates 46 and 47 function in the same manner as the XOR gates 41 and 42 of the first to third adders 320 to 322. And the 4th adder 323 is a structure which does not contain an AND gate and an OR gate compared with the 1st-3rd adders 320-322. Therefore, the adder 323 corresponding to the uppermost digital signals Da3 and Db3 is an adder circuit that has a carry-in and does not have a carry-out.

  Accordingly, the subtractor 21 adds the complement (2's complement) of the digital signals Da3 to Da0 to the digital signals Db3 to Db0, thereby obtaining a result obtained by subtracting the digital signals Da3 to Da0 from the digital signals Db3 to Db0. The subtracter 21 outputs digital signals X3 to X0 as a subtraction result.

  The comparator 22 includes four exclusive OR circuits (XOR gates or ExOR gates) 51 to 54 corresponding to the number of bits of the digital signals X3 to X0 of the subtractor 21, and one OR circuit (OR gate) 55. Have. Each XOR gate 51 to 54 is supplied with a digital signal of a corresponding bit. The XOR gates 51 to 54 output signals S30 to S33 corresponding to the exclusive OR operation results of the digital signals X0 to X3 and the reference digital signals R0 to R3. The OR gate 55 outputs a signal S1 corresponding to the logical sum operation result of the signals S30 to S32.

The output circuit 23 is an inverter circuit, for example. The output circuit 23 outputs a determination signal ST having a level obtained by logically inverting the output signal S1 of the comparator 22.
Next, the overall flow of the test for the semiconductor device 10 (A / D conversion circuits 11 and 12) will be described with reference to FIG.

First, in step 61, the voltage value AV1 of the analog signal A1 is set to the minimum voltage Vmin, and the voltage value AV2 of the analog signal A2 is set to the intermediate voltage Vc (= 1/2 Vmax).
Next, in step 62, a subtraction process is performed. In this processing, the digital signal X corresponding to the result of subtracting the digital signal Da of the A / D conversion circuit 11 supplied with the analog signal A1 from the digital signal Db of the A / D conversion circuit 12 supplied with the analog signal A2. Is generated.

  Next, at step 63, it is determined whether or not the value of the digital signal X is equal to ½ Vmax, that is, whether or not the digital signal X is equal to the reference digital signal R. If not equal, in step 64, the A / D conversion circuits 11 and 12 are determined to be defective (FAIL), and the test is terminated.

  If the value of the digital signal X is equal to ½ Vmax in step 63, the voltage values AV1 and AV2 of the analog signals A1 and A2 are increased by 1LSB in step 65, respectively.

  Next, at step 66, it is determined whether or not the voltage value AV2 of the analog signal A2 exceeds the maximum voltage Vmax. If so, in step 67, the voltage value AV2 of the analog signal A2 is set to the minimum voltage Vmin.

  Next, at step 68, it is determined whether or not the voltage value AV1 of the analog signal A1 is equal to or lower than the maximum voltage Vmax. If the voltage value AV1 is less than or equal to the maximum voltage Vmax, the routine proceeds to step 62. That is, the processes in steps 62 to 68 are repeatedly executed until the voltage value AV1 of the analog signal A1 exceeds the maximum voltage Vmax.

When the voltage value AV1 of the analog signal A1 exceeds the maximum voltage Vmax, the A / D conversion circuits 11 and 12 are determined to be good (PASS) in step 69, and the test is terminated.
Next, the operation of the semiconductor device 10 will be described.

For example, the input voltage range of the A / D conversion circuits 11 and 12 shown in FIG. 1 is set to 0 to 15 [V]. That is, the minimum voltage Vmin = 0 [V] and the maximum voltage Vmax = 15 [V].
First, the test apparatus 100 outputs an analog signal A1 having a minimum voltage Vmin (= 0). The test apparatus 100 outputs an analog signal A2 having an intermediate voltage Vc (= Vmax / 2). In the above input voltage range (0 to 15), the intermediate voltage Vc (= Vmax / 2) is calculated to be 7.5 [V]. However, the test apparatus 100 changes the voltage values of the generated analog signals A1 and A2 by 1 LSB of the A / D conversion circuits 11 and 12 in order to test the linearity of the A / D conversion circuits 11 and 12. In this input voltage range, 1LSB becomes 1 [V]. For this reason, the test apparatus 100 outputs 8 [V] as the intermediate voltage Vc.

  At this time, as shown in FIG. 4, the digital signals Db3 to Db0 of the A / D conversion circuit 12 are [1000], and the digital signals Da3 to Da0 of the A / D conversion circuit 11 are [0000]. Accordingly, the digital signals X3 to X0 that are the difference between the two digital signals Da3 to Da0 and Db3 to Db0 are [1000]. The digital signals X3 to X0 coincide with the reference digital signals R3 to R0 ([1000]). For this reason, the determination circuit 14 outputs an H level determination signal ST. The test apparatus 100 determines that the linearity of the A / D conversion circuits 11 and 12 is good (“OK”) based on the determination signal ST at the H level.

  Next, the test apparatus 100 increases 1 LSB, and outputs an analog signal A1 of 1 [V] and an analog signal A2 of 9 [V]. At this time, the digital signals Db3 to Db0 of the A / D conversion circuit 12 are [1001], and the digital signals Da3 to Da0 of the A / D conversion circuit 11 are [0001]. Accordingly, the digital signals X3 to X0 that are the difference between the two digital signals Da3 to Da0 and Db3 to Db0 are [1000]. The digital signals X3 to X0 coincide with the reference digital signals R3 to R0 ([1000]). For this reason, the determination circuit 14 outputs an H level determination signal ST. The test apparatus 100 determines that the linearity of the A / D conversion circuits 11 and 12 is good (“OK”) based on the determination signal ST at the H level.

  Similarly, the test apparatus 100 changes the analog signal A1 from 2 [V] to 7 [V], and changes the analog signal A2 from 10 [V] to 15 [V]. The determination circuit 14 outputs a determination signal ST based on the digital signals Da3 to Da0 and Db3 to Db0.

  When changing the analog signal A2 to the maximum voltage Vmax (= 15), the test apparatus 100 next sets the analog signal A2 to the minimum voltage Vmin (= 0). Then, the test apparatus 100 outputs an analog signal A1 of 8 [V]. At this time, the digital signals Db3 to Db0 of the A / D conversion circuit 12 are [0000], and the digital signals Da3 to Da0 of the A / D conversion circuit 11 are [1000]. Accordingly, the digital signals X3 to X0 that are the difference between the two digital signals Da3 to Da0 and Db3 to Db0 are [1000]. That is, the digital signals X3 to X0 that are the difference between the digital signals output from the two A / D conversion circuits having good linearity are constant values regardless of the magnitudes of the voltage values of both analog signals A1 and A2. It becomes.

  For example, when the linearity of one A / D conversion circuit is not good, the values of the digital signals X3 to X0 do not match the values of the reference digital signals R3 to R0. For example, as shown in the lowermost stage of FIG. 4, the A / D conversion circuit 11 of FIG. 1 outputs digital signals Da3 to Da0 of code [1111] with respect to the analog signal A1 of 15 [V]. On the other hand, the A / D conversion circuit 12 outputs the digital signals Db3 to Db0 of the code [0110] with respect to the analog signal A2 of 7 [V]. At this time, the digital signals X3 to X0 that are the difference between the two digital signals Da3 to Da0 and Db3 to Db0 are [0111]. The digital signals X3 to X0 do not coincide with the reference digital signals R3 to R0 ([1000]). Therefore, the determination circuit 14 outputs an L level determination signal ST. The test apparatus 100 determines that the linearity of the A / D conversion circuits 11 and 12 is defective (“NG”) based on the determination signal ST at the L level.

  As shown in FIG. 1, the two A / D conversion circuits 11 and 12 formed on one chip often have the same characteristics. A test for these A / D conversion circuits 11 and 12 will be described.

  FIG. 5A is a characteristic diagram of the A / D conversion circuit, and FIG. 5B is an explanatory diagram showing changes in the output code. As shown in FIG. 5A, in the A / D conversion circuits 11 and 12, the change in the output code has a linear characteristic with respect to the change in the input voltage. In this case, the codes of the digital signals Da and Db output from the two A / D conversion circuits 11 and 12 change linearly with respect to changes in the analog signals A1 and A2, as shown in FIG. To do. In FIG. 5B, the horizontal axis is a step of changing the analog signals A1 and A2 by the test apparatus 100 (a test step shown in the leftmost column of FIG. 4). In this case, the digital signal X, which is the difference between the digital signals Da and Db output from both A / D conversion circuits 11 and 12, takes a constant value with respect to changes in the digital signals Da and Db. Since the digital signal X coincides with the reference digital signal R, the determination circuit 14 shown in FIG. 1 outputs an H level determination signal ST.

  FIG. 6A is a characteristic diagram of the A / D conversion circuit, and FIG. 6B is an explanatory diagram showing changes in the output code. As indicated by the solid line in FIG. 6A, the characteristics of the A / D conversion circuits 11 and 12 are deviated from the ideal characteristics indicated by the one-dot chain line. The A / D conversion circuits 11 and 12 having this characteristic output a code lower than the linear characteristic at a low input voltage, and output a code higher than the linear characteristic at a high input voltage. In this case, the codes of the digital signals Da and Db output from the two A / D conversion circuits 11 and 12 change as indicated by solid lines in FIG. The digital signal X, which is the difference between the digital signals Da and Db output from both A / D conversion circuits 11 and 12, increases or decreases according to changes in the digital signals Da and Db. In the case of the characteristic change shown in FIG. 6B, the determination circuit 14 outputs an L-level determination signal ST as indicated by the up and down arrows in the figure.

  FIG. 7A is a characteristic diagram of the A / D conversion circuit, and FIG. 7B is an explanatory diagram showing changes in the output code. As indicated by the solid line in FIG. 7A, the characteristics of the A / D conversion circuits 11 and 12 are deviated from the ideal characteristics indicated by the one-dot chain line. The A / D conversion circuits 11 and 12 having this characteristic output a code higher than the linear characteristic in the input voltage range. In this case, the codes of the digital signals Da and Db output from the two A / D conversion circuits 11 and 12 change as indicated by solid lines in FIG. The digital signal X, which is the difference between the digital signals Da and Db output from both A / D conversion circuits 11 and 12, increases or decreases according to changes in the digital signals Da and Db. In the case of the characteristic change shown in FIG. 7B, the determination circuit 14 outputs an L-level determination signal ST as indicated by the up and down arrows in the figure.

  Then, the test apparatus 100 determines the quality of the A / D conversion circuits 11 and 12 based on the level of the determination signal ST. That is, the test apparatus 100 can determine the linearity of the two A / D conversion circuits 11 and 12 by monitoring the 1-bit determination signal ST output from the determination circuit 14.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The A / D conversion circuits 11 and 12 of the semiconductor device 10 perform analog / digital conversion on the analog signals A1 and A2 and output digital signals Da and Db. The determination circuit 14 outputs a determination signal ST corresponding to the result of comparing the signal X corresponding to the difference between the first digital signal Da and the second digital signal Db with the reference digital signal R.

  The test apparatus 100 to which the semiconductor device 10 is connected supplies the first and second analog signals A1 and A2 having a voltage difference corresponding to the value of the reference digital signal R to the A / D conversion circuits 11 and 12. Further, the test apparatus 100 increases the first and second analog signals A1 and A2 by 1 LSB of the A / D conversion circuits 11 and 12, respectively.

  The A / D conversion circuits 11 and 12 output digital signals Da and Db corresponding to different voltage ranges in the input voltage range, respectively. The determination circuit 14 generates a determination signal ST based on the digital signals Da and Db generated in the A / D conversion circuits 11 and 12 according to the characteristics of different voltage ranges.

  The difference between the digital signals output from the two A / D conversion circuits with good linearity corresponds to the difference between the voltage values of the analog signals supplied to the two A / D conversion circuits. In this embodiment, the value is constant (= [1000]) in the input voltage range of the two A / D conversion circuits. On the other hand, when the linearity is not good in at least one of the two A / D conversion circuits, the difference between the digital signals output from the two A / D conversion circuits is not a constant value.

  Accordingly, analog signals A1 and A2 having different voltage values are supplied to the two A / D conversion circuits 11 and 12, and the difference X between the digital signals Da and Db of each A / D conversion circuit 11 and 12 and the reference digital signal R The linearity of the two A / D conversion circuits 11 and 12 can be easily determined by the determination signal ST corresponding to the result of comparing the two.

  (2) The determination circuit 14 includes a subtractor 21 that subtracts the digital signal Da from the digital signal Db, and a comparator 22 that compares the output signal X of the subtractor 21 and the reference digital signal R. Then, the determination circuit 14 outputs a determination signal ST based on the signal S1 output from the comparator 22. Therefore, the test can be performed in a shorter time compared to the case where the linearity is obtained by calculation based on the digital signal output from the A / D conversion circuit.

  (3) Analog signals A1 and A2 having different voltage values are supplied to the A / D conversion circuits 11 and 12, respectively. The determination circuit 14 compares the digital signals Da and Db corresponding to the analog signals A1 and A2 having different voltage values in the two A / D conversion circuits 11 and 12, and generates a determination signal ST. Therefore, in the input voltage ranges of the two A / D conversion circuits 11 and 12, the conversion results in different ranges are compared.

  The characteristics of the two A / D conversion circuits 11 and 12 formed in the semiconductor device 10 are often equal to each other. Therefore, even if an analog signal having the same voltage value is supplied to two A / D conversion circuits, the respective digital signals change in the same manner. Therefore, the linearity is determined by comparing the two digital signals. It ’s difficult.

  On the other hand, in the present embodiment, the conversion results in different ranges are compared. Therefore, even if the characteristics of the two A / D conversion circuits 11 and 12 are the same, the digital signals Da and Db generated by different voltage ranges have values corresponding to the characteristics of the respective voltage ranges. The difference between the digital signals Da and Db is unlikely to be a constant value. Therefore, the linearity can be easily determined by comparing the difference X between the digital signals Da and Db with the constant reference digital signal R.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the test for the two A / D conversion circuits 11 and 12 included in the semiconductor device 10 has been described. A test can be similarly performed on three or more A / D conversion circuits.

  For example, as illustrated in FIG. 9, the semiconductor device 70 includes four A / D conversion circuits 71 a to 71 d and one determination circuit 72. Each A / D conversion circuit 71a to 71d is supplied with an analog signal having a different voltage value to an adjacent A / D conversion circuit at the time of testing. That is, the first analog signal A1 is supplied to the first A / D conversion circuit 71a and the third A / D conversion circuit 71c, and the second A / D conversion circuit 71b and the fourth A / D conversion are supplied. The circuit 71d is supplied with the second analog signal A2.

  The determination circuit 72 is configured to determine digital signals output from two A / D conversion circuits to which analog signals having different voltage values are supplied. That is, the determination circuit 72 has subtracters 73a to 73c and comparators 74a to 74c. The subtractor 73a includes a digital signal Da output from the first A / D conversion circuit 71a in response to the first analog signal A1 and a second A / D conversion circuit 71b in response to the second analog signal A2. The digital signal Xa corresponding to the difference of the digital signal Db output from the is output. The comparator 74a outputs a determination signal STa corresponding to the result of comparing the digital signal Xa with the reference digital signal R from the register 75. For example, the comparator 74a outputs an H level determination signal STa when the digital signal Xa and the reference digital signal R match each other, and outputs an L level determination signal STa when they do not match.

  Similarly, the subtractor 73b outputs a digital signal Db output from the second A / D conversion circuit 71b in response to the second analog signal A2 and a third A / D in response to the first analog signal A1. A digital signal Xb corresponding to the difference between the digital signals Dc output from the conversion circuit 71c is output. The comparator 74b outputs a determination signal STb corresponding to the result of comparing the digital signal Xb with the reference digital signal R from the register 75. The subtractor 73c includes a digital signal Dc output from the third A / D conversion circuit 71c in response to the first analog signal A1, and a fourth A / D conversion circuit 71d in response to the second analog signal A2. The digital signal Xc corresponding to the difference of the digital signal Dd output from the is output. The comparator 74c outputs a determination signal STc corresponding to the result of comparing the digital signal Xc with the reference digital signal R from the register 75.

  Therefore, the test apparatus can determine the linearity in the first A / D conversion circuit 71a and the second A / D conversion circuit 71b based on the level of the determination signal STa. Similarly, the test apparatus can determine the linearity in the second A / D conversion circuit 71b and the third A / D conversion circuit 71c based on the level of the determination signal STb. In addition, the test apparatus can determine the linearity in the third A / D conversion circuit 71c and the fourth A / D conversion circuit 71d based on the level of the determination signal STc.

  Note that the determination signals STa to STc may be combined and output to the outside of the semiconductor device 70. For example, each of the comparators 74a to 74c outputs H level determination signals STa to STc when the digital signals Xa to Xc match the reference digital signal R, and outputs L level determination signals STa to STc when they do not match. Output. Therefore, an AND gate that supplies determination signals STa to STc is provided, and an output signal of the AND gate is used as a determination signal. If linearity is not obtained even in one of the four A / D conversion circuits 71a to 71d, the semiconductor device 10 becomes defective. Therefore, the quality of the semiconductor device 10 can be determined by a 1-bit determination signal. The logic gate that supplies the determination signals STa to STc is set according to the logic level of each of the signals STa to STc.

  In the semiconductor device 70 shown in FIG. 9, the configuration may be appropriately changed as long as the linearity of each of the A / D conversion circuits 71 a to 71 d can be determined. For example, the subtractor 73b and the comparator 74b may be omitted.

  A test analog signal for each A / D conversion circuit may be supplied to each A / D conversion circuit by a device other than the test apparatus 100. For example, a D / A conversion circuit (Digital to Analog Converter) may be used. For example, the D / A conversion circuit is mounted on the semiconductor device 10 illustrated in FIG. 1 or is externally connected to the semiconductor device 10.

As the register 24, a circuit including a nonvolatile memory cell, a circuit including a fuse element, or the like can be used.
Further, the reference digital signals R3 to R0 may be supplied from, for example, the internal circuit 13 or the test apparatus 100.

The output circuit 23 may output a determination signal ST having a level equal to the output signal S1 of the comparator 22.
The present invention may be embodied in a semiconductor device having a plurality of A / D conversion circuits having different numbers of bits of digital signals to be output. For example, in the case of a 6-bit A / D conversion circuit and a 4-bit A / D conversion circuit, the upper 4 bits of the digital signal output from the 6-bit A / D conversion circuit are supplied to the subtracter. The lower 4 bits of the digital signal output from the 6-bit A / D conversion circuit may be supplied to the subtracter.

  Further, the present invention may be embodied in a semiconductor device having a plurality of A / D conversion circuits having different input voltage ranges. In this case, the analog signal supplied to each A / D conversion circuit is set according to the input voltage range of the corresponding A / D conversion circuit. For example, when the input voltage ranges of the A / D conversion circuits 11 and 12 shown in FIG. 1 are different from each other, the test apparatus 100 changes the analog signal A1 from the minimum voltage to the maximum voltage in the input voltage range of the A / D conversion circuit 11. Change. Further, the test apparatus 100 changes the analog signal A2 from an intermediate voltage in the input voltage range of the A / D conversion circuit 12 to a maximum voltage and from a minimum voltage to an intermediate voltage.

Further, the present invention may be embodied in a semiconductor device having a plurality of A / D conversion circuits having different input voltage ranges and different numbers of bits of output digital signals.
The difference between the analog signals A1 and A2 supplied to the two A / D conversion circuits 11 and 12 may be changed as appropriate. For example, the first analog signal A1 is changed from the minimum voltage Vmin to the maximum voltage Vmax, and the second analog signal A2 is changed from Vmax / 4 to the maximum voltage Vmax and from the minimum voltage Vmin to Vmax / 4. The value of the reference digital signal R is set to [0100] while the second analog signal A2 is changed from Vmax / 4 to Vmax, and is set to [1100] while the value is changed from the minimum voltage Vmin to Vmax / 4. In this way, by switching the value of the reference digital signal R, the determination signal ST corresponding to the two A / D conversion circuits can be generated by the subtractor and the comparator as in the above embodiment.

  In each of the above embodiments, the voltage values of the analog signals A1 and A2 are increased by 1 LSB, but may be decreased by 1 LSB. For example, the analog signal A1 is changed from the maximum voltage Vmax to the minimum voltage Vmin, and the analog signal A2 is changed from the intermediate voltage to the minimum voltage Vmin and from the maximum voltage Vmax to the intermediate voltage.

11, 12 A / D conversion circuit 14 Judgment circuit 21 Subtractor 22 Comparator 23 Output circuit 24 Register 100 Test device A1, A2 Analog signal Da, Db Digital signal R Reference digital signal (reference value)
ST determination signal Xa. Xb digital signal

Claims (7)

A first analog / digital conversion circuit that performs analog / digital conversion on the first analog signal and outputs the first digital signal;
A second analog / digital conversion circuit for analog / digital conversion of a second analog signal different from the first analog signal and outputting a second digital signal;
A determination circuit that generates a determination signal according to a result of comparing a difference between the first digital signal and the second digital signal and a reference value;
A semiconductor device comprising:   2. The reference value is set to a value that is one half of a maximum value of a digital signal having a small number of bits of the first digital signal and the second digital signal. The semiconductor device described. The determination circuit includes:
A subtractor for outputting a result obtained by subtracting the first digital signal from the second digital signal;
A comparator that generates the determination signal in accordance with a result of matching the value output from the subtractor with the reference value;
The semiconductor device according to claim 1, further comprising: A test method for an analog / digital conversion circuit in which a test apparatus executes a test of a plurality of analog / digital conversion circuits,
It said semiconductor device to be connected to the test apparatus, according to the result of comparing the at least two analog / digital converting circuit, and a difference between the reference value of the digital signals respectively output from the two analog / digital converter Including a determination circuit for generating a determination signal;
The test apparatus supplies two analog signals having a voltage difference corresponding to the reference value to the two analog / digital conversion circuits, respectively, and based on the determination signal, the straight line of the two analog / digital conversion circuits. Judging gender,
A test method for an analog / digital conversion circuit characterized by the above. The test apparatus sets the voltage value of the analog signal corresponding to the minimum quantization bit of the analog / digital conversion circuit having the least number of bits among the digital signals output from the plurality of analog / digital conversion circuits. Each time the analog signal is increased or decreased, and the determination is made based on the determination signal.
5. The method for testing an analog / digital conversion circuit according to claim 4. The reference value is set to one half of the maximum value of the digital signal having the smallest number of bits among the digital signals output from the plurality of analog / digital conversion circuits;
6. The method for testing an analog / digital conversion circuit according to claim 4 or 5. The test apparatus supplies two analog signals having different voltage values to two analog / digital conversion circuits formed adjacent to each other,
The method for testing an analog / digital conversion circuit according to any one of claims 4 to 6.