JP5802488B2 - Receiver - Google Patents

Description

  The present invention relates to a receiving apparatus that receives serial data (serial pattern) including a known bit pattern (specific pattern) and detects that serial data including the specific pattern has been received.

  Many communication protocols (rules) adopted in high-speed serial communication technology are premised on a specific pattern detection process. As shown in FIG. 22, the most common serial pattern configuration is preamble + start delimiter + payload + end of burst (EOB) (or end delimiter). Other than the payload, which is the data storage area, each communication protocol defines a specific pattern with a specific number of bits.

  FIG. 23 is a conceptual diagram illustrating an example of a configuration of a conventional receiving apparatus. The receiving device 80 shown in the figure represents only a serial / parallel conversion circuit 82 and a reception pattern storage register 84 that convert received serial data into parallel data having a predetermined bit width.

  In the receiving device 80, for example, the received 10 Gbps high-speed serial data is synchronized with a parallel clock obtained by dividing the serial clock reproduced from the received serial data by the serial-parallel conversion circuit 82, 312.5 MHz, 32 bits. Converted to parallel data. The serial-parallel conversion circuit 82 outputs the converted 32-bit width parallel data DATAn and the parallel clock.

  The reception pattern storage register 84 is configured by connecting three 32-bit flip-flops (FF) 86 in series. The reception pattern storage register 84 sequentially shifts the 32-bit width parallel data DATAn input from the parallel-serial conversion circuit 82 to the subsequent FF 86 in synchronization with the parallel clock. The reception pattern storage register 84 always outputs the latest (last) predetermined period of parallel data DATA1 to n.

  Here, the receiving apparatus receives not only valid serial data but also various noises. Therefore, in order to distinguish valid data, as described above, a portion having a known bit pattern (specific pattern) called a preamble is added to the head of serial data. By detecting the preamble by the receiving device, it is possible to receive effective serial data separately from noise.

  A general method for detecting a specific pattern is as follows. That is, as shown in FIG. 24, for example, when the bit length of the specific pattern is 64 bits and the parallel data converted by the serial / parallel conversion circuit 82 has a bit width of 32 bits, The specific pattern is detected by comparing each of the 32 stored patterns in which the specific pattern may appear with the specific pattern.

  Here, the 32 patterns in which the specific pattern may appear are a range of 32 bits that are consecutive in the order received in the serial data of the bits constituting the parallel data DATA1 to 3 stored in the reception pattern storage register 84. (In the example of FIG. 24, it is a 64-bit portion (32 storage patterns) starting from each bit of the parallel data DATA1 of 32 bits from 0 to 31).

  In the arrangement of the bits of the parallel data DATA1 to DATA3 in the figure, the leftmost bit is the least significant bit (bit 0), which is the first bit of the serial data. The same applies to other figures.

The reason why the specific pattern is detected as described above is as follows. That is,
(1) Since the specific pattern is longer than the bit width of parallel data, one cycle (cycle) of data is insufficient. In FIG. 24, the specific pattern is 64 bits while the parallel data is 32 bits. Therefore, it is necessary to hold data for at least two cycles, and also for three cycles considering the following reason (2). There is.
(2) Since it is unclear which storage pattern at which the head position is detected in the continuous 32-bit range, it is necessary to detect a match with the specific pattern for all 32 storage patterns. .

  Next, a specific example of the receiving device will be described.

  FIG. 25 is a circuit diagram illustrating an example of a configuration of a conventional receiving apparatus. The receiver 90 shown in the figure represents the configuration when the bit length of the specific pattern is 64 bits and the bit width of the parallel data converted by the serial / parallel converter circuit is 32 bits as described above. In addition, a serial-parallel conversion circuit 82, a reception pattern storage register 84A, and a pattern comparison circuit 88A are provided.

  In order to compare each of the 32 storage patterns included in the parallel data DATA1 to 3 cycles of the three periods with the specific pattern at a time, the reception pattern storage register 84A has two stages of 32 bits connected in series. FF86A is provided.

  Also, 32 comparators (comparators 0 to 31) 92A for comparing the two are provided. Each of the storage patterns and specific patterns are input to each comparator 92A, and 32 pattern matching flags [31: 0], which are the comparison results of both, are output from the comparator 92A. Is done.

  FIG. 26 is a circuit diagram illustrating an example of the configuration of the comparator. The comparator 92A shown in the figure is composed of 64 EXOR (exclusive OR) circuits 94A and one NOR circuit 96A.

  Each EXOR circuit 94A compares the corresponding bits of the storage pattern and the specific pattern, and as a result of the comparison, “0” is output when the two match, and “1” is output when they do not match. As a result, from the NOR circuit 96A, when all the bits match as the pattern match flag, that is, when the storage pattern and the specific pattern match, “1”, even if one bit does not match. "0" is output in the.

  In high-speed communication, it is necessary to detect a specific pattern while allowing a certain amount of communication error (the number of bits that do not match between the storage pattern and the specific pattern).

  FIG. 27 is a circuit diagram of another example showing the configuration of a conventional receiving apparatus. The receiving apparatus 100 shown in the figure has a function that allows a predetermined number of communication errors. The maximum number of allowable mismatch bits is input to each comparator 92B constituting the pattern comparison circuit 88B.

  FIG. 28 is a circuit diagram illustrating an example of the configuration of the comparator. The comparator 92B shown in the figure is composed of 64 EXOR circuits 94A, an adder 98B, and a magnitude comparison circuit 102B.

  In the comparator 92B, the comparison results from the 64 EXOR circuits 94A are added by the adder 98B. The adder 98B is a 4-bit adder that outputs the addition result as it is if the addition result is less than 15, and outputs 15 if it is 15 or more. That is, the adder 98B corresponds to the case where the number of communication errors is up to 14. If the addition result, that is, the number of communication errors is less than the maximum allowable mismatch bit number 15, it is considered that a match is detected by the magnitude comparison circuit 102B, and the pattern match flag is set to “1”.

  Here, Patent Documents 1 to 3 are related to prior art documents relevant to the present invention.

  In Patent Document 1, serial data is converted into n-bit parallel data, n-bit parallel data is received, and n + m−1 bits (m is a bit length of a specific pattern) is stored in a register. The M bit comparator shifts the start bit of the n + m-1 bit data stored in the register by 1 bit, and detects the coincidence between each of the N consecutive m bit data and the m bit specific pattern. Are described in parallel.

  In Patent Documents 2 and 3, parallel data and a specific pattern are compared for each bit, and even if a bit error in which the bit value does not match between both is included due to the influence of the transmission line, the number is defined. It is described that if it is less than or equal to the number, it is determined that the pattern matches the specific pattern.

JP-A-7-202865 JP 2005-260500 A JP-A-8-65294

  In the conventional receiving apparatus, even when a communication error is not allowed when a specific pattern is detected, the pattern comparison circuit is composed of 64 × 32 = 2048 EXOR circuits, and it can be said that the comparison circuit is too large. In addition, if such a large-scale circuit is configured with only combinational circuits, problems such as difficulty in wiring during layout and difficulty in timing convergence may occur.

  An object of the present invention is to provide a receiving apparatus capable of reducing the circuit scale of a pattern detection circuit and reducing the cost.

In order to achieve the above object, the present invention provides a receiving apparatus for receiving serial data including a detection target portion having a known bit pattern having an M bit length,
A serial-parallel conversion circuit that generates parallel data of N bits (N <M) width by arranging the data of each bit constituting the received serial data in the order of reception;
A first register storing N-bit parallel data generated by the serial-parallel conversion circuit, and the parallel data stored in the first register are sequentially shifted and stored in synchronization with a parallel clock. A group of registers comprising one or more second registers to be
Each bit in the range of N bits consecutive in the order received as the serial data of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers is set as the head. A comparison circuit for comparing a portion of L bits (N ≦ L <M) to be compared with a corresponding portion of the known bit pattern;
The comparison circuit, the Oite the first cycle of the parallel clock, said bits forming the parallel data stored in said first register and said one or more second register at that time A match between an L-bit portion starting from the K-th bit (K = 0 to N−1) from the beginning of a range of consecutive N bits and an L-bit portion from the beginning of the known bit pattern is detected; Furthermore, the quotient of L / N q, the remainder as r, K, N, q, Oite within a particular period of the parallel clock determined by r, the first register and the one or more at that time the two bits constituting the parallel data stored in the register, the range of N bits, wherein the successive and K, N, J bits (J ≦ M to start a specific bit determined by r of L) and a detection circuit for detecting reception of the serial data on condition that a match between the L + 1 bit and the J bit portion from the (L + 1) th bit of the known bit pattern is detected. A device is provided.

Here, the specific cycle is a cycle after q cycles from the first cycle of the parallel clock, and the specific bit is:
(1A) If K <N−r, it is the K + rth bit from the beginning of the range of consecutive N bits,
(2B) If N−r ≦ K, the K + r−N-th bit from the beginning of the r-bit range immediately after the continuous N-bit range.
Or
The specific period is a period after q + 1 period from the first period of the parallel clock, and the specific bit is:
(1B) If K <N−r, it is the Kth bit from the beginning of the range of Nr bits immediately before the range of consecutive N bits,
(2A) When N−r ≦ K, it is preferable that the bit is the (K + r−N) th bit from the beginning of the range of the consecutive N bits.

Further, the comparison circuit includes:
A portion starting from each bit in the range of the consecutive N bits of the bits constituting a plurality of parallel data stored in the first register and the one or more second registers and the known bit Comprising N first comparators for comparison with corresponding parts of the pattern;
Each bit in the range of r bits immediately after the range of consecutive N bits of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers is set as the head. R second comparators for comparing a portion to be matched with a corresponding portion of the known bit pattern, and a plurality of parallels stored in the first register and the one or more second registers N-r comparisons are made between a portion starting with each bit in the range of Nr bits immediately before the range of consecutive N bits of the bits constituting the data and a corresponding portion of the known bit pattern. And at least one of the third comparator,
The detection circuit comprises:
The specific cycle is a cycle after q cycles from the first cycle,
(1A) If K <N−r, the portion of the first comparator starting with the K + r-th bit from the beginning of the continuous N-bit range and the known bit pattern Comparing with a corresponding portion of the J bit portion starting from the K + r bit and the L + 1 bit to J bit portion of the known bit pattern,
(2B) If N−r ≦ K, the K + r−N-th bit from the beginning of the r-bit range immediately after the continuous N-bit range in the second comparator And a comparator that compares the corresponding portion of the known bit pattern with the J bit portion starting from the K-th bit and the L + 1 bit to J bit portion of the known bit pattern. With,
Detecting reception of the serial data on condition that a match is detected,
Or
The specific period is a period after q + 1 period from the first period,
(1B) When K <N−r, the Kth bit from the beginning of the Nr bit range immediately before the continuous N bit range in the third comparator And a comparator for comparing the corresponding portion of the known bit pattern with the J bit portion starting from the K bit and the (L + 1) th bit of the known bit pattern With part,
(2A) When N−r ≦ K, the portion of the first comparator starting from the head of the K + r−N bits from the head of the continuous N-bit range and the known A comparator that performs a comparison with a corresponding portion of the bit pattern includes a J bit portion starting from the K + r-N bit and a L bit from the L + 1 bit to the J bit portion of the known bit pattern.
It is preferable to detect reception of the serial data on condition that a match is detected.

If (1A) K <N−r, the specific period is a period after q periods from the first period of the parallel clock, and the specific bits are in a range of the consecutive N bits. The K + rth bit from the beginning of
(2A) When N−r ≦ K, the specific cycle is a cycle after q + 1 cycles from the first cycle of the parallel clock, and the specific bit is the head of the range of the consecutive N bits. To the (K + r−N) th bit.

Further, the comparison circuit starts with each bit in the range of the consecutive N bits of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers. N comparators for comparing a portion to be matched with a corresponding portion of the known bit pattern,
The detection circuit comprises:
(1A) When K <N−r, a portion of the N comparators beginning with the K + r-th bit from the head of the continuous N-bit range and the known bit pattern Comparing with a corresponding portion of the J bit portion starting from the K + r bit and the L + 1 bit to J bit portion of the known bit pattern,
(2A) If N−r ≦ K, a portion of the N comparators starting from the head of the K + r−N-th bit from the head of the continuous N-bit range and the known A comparator that performs a comparison with a corresponding portion of the bit pattern includes a J bit portion starting from the K + r-N bit and a L bit from the L + 1 bit to the J bit portion of the known bit pattern.
It is preferable to detect reception of the serial data on condition that a match is detected.

  Further, it is preferable that M = I · L (I is an integer of 2 or more), and J = L.

  Further, it is preferable that the comparison circuit detects a match by allowing a predetermined number of bits to be mismatched.

  In the present invention, since the number of EXOR circuits constituting the comparator can be reduced, the circuit scale of the receiving apparatus can be reduced. Thus, according to the present invention, effects such as chip cost reduction and layout easiness improvement can be obtained by reducing the circuit scale.

It is a circuit diagram of a 1st embodiment showing composition of a receiving device of the present invention. It is an example circuit diagram showing the composition of a comparator. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is an example timing diagram showing operation | movement of a receiver. It is a circuit diagram of 2nd Embodiment showing the structure of the receiver of this invention. It is an example circuit diagram showing the composition of a pattern detection circuit. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a circuit diagram of 3rd Embodiment showing the structure of the receiver of this invention. It is an example circuit diagram showing the composition of a comparator. It is an example circuit diagram showing the composition of a comparison pattern selection part. It is an example circuit diagram showing the composition of a pattern detection circuit. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a circuit diagram of 4th Embodiment showing the structure of the receiver of this invention. It is an example circuit diagram showing the composition of a comparator. It is a circuit diagram of a 5th embodiment showing the composition of the receiving device of the present invention. It is an example circuit diagram showing the composition of a comparator. It is an example circuit diagram showing the composition of a pattern detection circuit. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is a conceptual diagram of an example showing the structure of a serial pattern. It is a conceptual diagram of an example showing the structure of the conventional receiver. It is a conceptual diagram of an example showing the relationship between a storage pattern and a specific pattern. It is an example circuit diagram showing the structure of the conventional receiver. It is an example circuit diagram showing the composition of a comparator. It is a circuit diagram of another example showing the structure of the conventional receiver. It is an example circuit diagram showing the composition of a comparator. It is an example circuit diagram showing the structure of the conventional receiver. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern. It is an example circuit diagram showing the structure of the conventional receiver. It is a conceptual diagram of an example showing the relationship between a storage pattern and a comparison pattern.

  Hereinafter, a receiving apparatus of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a circuit diagram of a first embodiment showing a configuration of a receiving apparatus of the present invention. The receiving apparatus 10 shown in the figure receives serial data including a detection target portion having a known bit pattern (specific pattern) having an M bit length, and detects that serial data including the specific pattern has been received. The serial-parallel conversion circuit 12, the reception pattern storage register 14, the pattern comparison circuit 16, and the pattern detection circuit 18 are configured.

  The receiving apparatus of the present invention does not compare each of the N (N <M) M-bit length storage patterns with the M-bit specific pattern at a time, but in a plurality of times. Compare multiple cycles. The receiving apparatus 10 is an example in the case of M = 64 and N = 32, and as shown in FIG. 2, each of 32 (N) 64 bit length (M bit length) storage patterns described later. And the specific pattern of 64 bits length (M bit length) is divided into two parts, 32 bits (L bit (N ≦ L <M) and J bit (J ≦ ML)) in the first half and the second half. Compare in two cycles.

  As shown in FIG. 22, the serial data is input to the receiving apparatus 10 in the order of preamble + start delimiter + payload + end of burst. The preamble has the specific pattern having the M bit length described above.

  The serial-parallel conversion circuit 12 is configured by, for example, a 32-bit (N-bit) register, and arranges the data of each bit constituting serial data received continuously in the register in the order received in synchronization with the serial clock. Parallel data having a 32-bit width (N-bit width) is generated. The serial / parallel conversion circuit 12 outputs parallel data DATA2 having a 32-bit width and a parallel clock obtained by dividing the serial clock recovered from the received serial data.

  Note that the serial-parallel conversion circuit 12 may generate parallel data by arranging the data of each bit constituting the serial data from the least significant bit side to the most significant bit side of the register, or in the opposite direction. Parallel data may be generated.

  Subsequently, the reception pattern storage register 14 shifts the 32-bit width parallel data DATA2 input from the serial-parallel conversion circuit 12 in units of 32 bits (N bits) in synchronization with the parallel clock, and always updates the latest ( The last parallel data for a predetermined period is stored.

  The reception pattern storage register 14 includes, for example, a first register that stores 32-bit width parallel data generated by the serial-parallel conversion circuit 12, and parallel data stored in the first register in parallel, And a register group having a pipeline structure including one or a plurality of second registers that are shifted and stored in synchronization with each other.

  The reception pattern storage register 14 may include a first register separately from the register constituting the serial / parallel conversion circuit 12, or the register constituting the serial / parallel conversion circuit 12 may be used as the first register. You can also

  The reception pattern storage register 14 shown in FIG. 1 uses the register of the serial / parallel conversion circuit 12 as the first register, and converts the parallel data DATA2 having a 32-bit width input from the serial / parallel conversion circuit 12 into a parallel clock. It is configured by one 32-bit FF (second register) 20 that holds the data in synchronization and outputs it as parallel data DATA1. That is, the parallel data DATA2 stored in the register of the serial / parallel conversion circuit 12 is sequentially shifted to the FF20. The serial / parallel conversion circuit 12 outputs the latest (last) parallel data DATA2 generated from the received serial data, and the FF 20 outputs the previous parallel data DATA1.

  Here, the storage state of a specific pattern having a 64-bit length in the reception pattern storage register 14 will be described.

  On the upper side of FIG. 3, the 32-bit width parallel data DATA1 stored in the second register 20 of the reception pattern storage register 14 and the serial-parallel conversion circuit 12 used as the first register of the reception pattern storage register 14 are shown. The 32-bit width parallel data DATA2 stored in the first register indicates the 32 states in which the 32-bit portion of the first half of the specific pattern of 64-bit length (M-bit length) is stored. The left end of each parallel data DATA1, DATA2 is the least significant bit, and the right end is the most significant bit. Therefore, when parallel data is generated by arranging the serial data bits received by the serial / parallel conversion circuit 12 from the least significant bit to the most significant bit, the parallel data is configured from the left end of DATA1 to the right end of DATA2. Are arranged in the order received as serial data.

  There is a possibility that the first 32 bits (L bits) of the 64-bit specific pattern of serial data is stored in any position in DATA1 and DATA2. However, when the parallel data has a width of 32 bits (N bits), 32 types (N types) of storage positions starting from each bit in the range of consecutive 32 bits (N bits) may be considered. The upper side of FIG. 3 shows the 0th, 1st, 2nd,..., In which the first 32 bits of a 64-bit specific pattern may be stored. . . The thirty-second and thirty-first thirty-two storage positions are indicated by horizontally long rectangles. In the illustrated example, 32 types of storage positions starting from the respective bits in the range of 32 bits continuous from the 0th bit to the 31st bit of DATA1 are shown. For example, at storage position 0, the first half of the 32 bits of the specific pattern is stored from the 0th bit to the 31st bit of DATA1. In the storage location 31, data is stored from the 31st bit of DATA1 to the 30th bit of DATA2.

  In addition to these 32 types of storage positions, the 32-bit portion of the first half of the specific pattern may be stored, for example, at the next position after the storage position 31, that is, from the 0th bit to the 31st bit of DATA2. Conceivable. However, the first 32 bits stored in this position are shifted to the storage position 0 and stored in the next clock cycle of the parallel clock. Therefore, as the positions at which 32-bit length patterns are stored in two registers having a 32-bit width, 32 types of storage positions starting from each bit in a continuous 32-bit range, for example, as shown in FIG. It is only necessary to consider 32 storage positions from 0 to 31. Here, a 32-bit storage pattern #n (n = 0 to 31) starting from the K-th bit (K = 0 to N−1) from the beginning of a continuous 32-bit range is represented by # n = K is defined.

  Subsequently, the pattern comparison circuit 16 stores each of the 32 (N) 32-bit (L-bit length) storage patterns described above and a specific pattern having a preset 64-bit length (M-bit length). The corresponding 32-bit portion (L-bit comparison pattern) is compared for each corresponding bit, and 32 (N) pattern match flags [31: 0] are output as the comparison result. .

  Here, if N> L, that is, if the bit width to be compared at one time is narrower than the bit width of the parallel data, it may be necessary to perform the comparison twice within one parallel clock cycle. In order to avoid this, it is necessary to satisfy N ≦ L. In this embodiment, as described above, N ≦ L <M.

  The pattern comparison circuit 16 in the illustrated example includes 32 (N) comparators (comparators 0 to 31) 22 and 32 (N) multiplexers 24 serving as comparison pattern selection units. Each of the comparators 0 to 31 receives the respective bits of the storage pattern stored in the corresponding storage position of the reception pattern storage register 14, and the comparison pattern to be compared with this storage pattern is sent from the multiplexer 24. Entered.

  The multiplexer 24 outputs a comparison pattern of the first 32-bit length (L-bit length) or the second-half 32-bit length (J-bit length) from the specific pattern of 64-bit length in response to a comparison pattern selection signal described later. To do.

  Here, when the multiplexers corresponding to the comparators 0 to 31 are expressed as multiplexers 0 to 31, a specific pattern [31: 0] is input to the input terminal 0 of the multiplexers 0 to 31, and the input terminal 1 is connected to the input terminal 1. The specific pattern [63:32] is commonly input, and each bit of the comparison pattern selection signal [0:31] is input to the selection terminal. Each multiplexer outputs a specific pattern [31: 0] that is the first half comparison pattern when the comparison pattern selection signal is “0”, and the second half comparison when the comparison pattern selection signal is “1”. A specific pattern [63:32] as a pattern is output.

  As shown in FIG. 2, each comparator 22 includes 32 EXOR circuits 26 and one NOR circuit 28.

  The storage pattern [31: 0] input from the reception pattern storage register 14 and the comparison pattern [31: 0] input from the multiplexer 24 are compared by the EXOR circuit 26 for each corresponding bit. The comparison result, which is an output signal of the EXOR circuit 26, is “0” when the corresponding bits match each other and “1” when they do not match. When all the comparison results [31: 0] are “0”, that is, when the storage pattern matches the comparison pattern, the pattern match flag that is the output signal of the NOR circuit 28 becomes “1”. Then, the pattern match flags generated by the 32 comparators 0 to 31 are collected and output as the pattern match flag [31: 0] of the comparator 22.

  As shown in this figure, the comparator 22 only needs to be able to compare 32-bit data, so the number of EXOR circuits 26 is 32, which can be reduced compared to the conventional comparator 92A shown in FIG. it can. In this embodiment, the number of bits of data to be compared at a time is 32 bits. However, by reducing the number of bits of data to be compared at a time, for example, 16 bits or 8 bits, the EXOR circuit 26 It is also possible to further reduce the number.

  Subsequently, the pattern detection circuit 18 includes 32 consecutive bits (N bits) of the bits constituting the parallel data stored in the reception pattern storage register 14 within the first period of the parallel clock by the pattern comparison circuit 16. Storage pattern of 32 bits (L bits) starting from the Kth bit (K = 0 to N-1) from the beginning of the range and 32 bits (L from the beginning of a specific pattern of 64 bits (M bits)) Bit) and a comparison pattern is detected, and the quotient of L / N is q and the remainder is r (q = 1, r = 0 in the example of FIG. 3), and K, N, q, r Within a specific period of the determined parallel clock, it is determined by the range of consecutive 32 bits (N bits) and K, N, and r constituting the parallel data stored in the reception pattern storage register 14. Detecting a match between a 32-bit (J-bit) storage pattern starting from a specific bit and a comparison pattern from the 33rd bit (L + 1 bit) to the 32-bit (J bit) of the 64-bit specific pattern As a condition, reception of serial data including a specific pattern having a 64-bit length is detected.

  The pattern detection circuit 18 in the illustrated example includes an AND circuit 30, an FF 32, and an AND circuit 34. Although not shown, the AND circuit 30, the FF 32, and the AND circuit 34 are provided with 32 sets of circuits corresponding to 32 pattern matching flags [31: 0].

  In the corresponding comparators 0 to 31, when the coincidence between the storage pattern and the comparison pattern is not detected, that is, when the pattern coincidence flag is “0”, the output signal of the AND circuit 30 becomes “0”. Since the output signal of the AND circuit 30 is held in the FF 32 in synchronization with the parallel clock, the comparison pattern selection signal that is the output signal of the FF 32 becomes “0” in the next cycle. Therefore, the detection signal which is the output signal of the AND circuit 34 is also “0”.

  When a match is detected in the corresponding comparators 0 to 31 and the pattern match flag becomes “1”, the output signal of the AND circuit 30 becomes “1”, and the comparison pattern selection signal is synchronized with the parallel clock in the next cycle. Becomes “1”. When the output signal of the FF 32 becomes “1”, the output signal of the AND circuit 30 becomes “0”, so that the comparison pattern selection signal returns to “0” in the next cycle in synchronization with the parallel clock.

  That is, the comparison pattern selection signal becomes “1” in the next cycle when the pattern match flag becomes “1”, that is, when a match between the stored pattern and the first half comparison pattern is detected. The one-shot signal returns to “0”. Further, the detection signal becomes “1” in two consecutive periods of the pattern matching flag, that is, “1” when the coincidence between the storage pattern and the comparison pattern in the first half and the second half is detected in succession. It becomes a one-shot signal that returns to “0” in the period of

  As described above, the comparison pattern selection signal becomes “1” when the pattern matching flag becomes “1”, that is, when a match between the storage pattern and the comparison pattern is detected. Therefore, when a match between the storage pattern and the first half comparison pattern is detected, the second half comparison pattern is output from the above-described multiplexer 24 in the next cycle, and the comparator 22 compares the storage pattern with the second half comparison pattern. A comparison is made.

  When the comparison between the storage pattern and the latter half comparison pattern is performed, the comparison between the storage pattern and the first half comparison pattern is performed in the next cycle regardless of whether or not a match between them is detected. As a result, when no match is detected by comparing the storage pattern with the latter half comparison pattern, the comparison between the storage pattern and the first half comparison pattern can be resumed from the next cycle.

  Next, the operation of the receiving device 10 will be described.

  In the receiving device 10, each bit data of the received serial data is arranged in a register in the order of reception in synchronization with the serial clock by the serial / parallel conversion circuit 12, and parallel data DATA 2 having a 32-bit width (N-bit width). Is generated.

  The parallel data DATA2 having a 32-bit width is shifted to the reception pattern storage register 14 in units of 32 bits (N bits) in synchronization with the parallel clock, and stored as parallel data DATA1 having a 32-bit width (N bits). The Thereby, as shown in FIG. 3, the latest two cycles of data consisting of parallel data DATA1 and DATA2 are always stored in the reception pattern storage register 14 in synchronization with the parallel clock.

  A corresponding storage pattern is input from the reception pattern storage register 14 to each of the comparators 22 (comparators 0 to 31) of the pattern comparison circuit 16. That is, the bits in the range corresponding to DATA1 and DATA2 are input. A comparison pattern is further input to each comparator 22 from the corresponding multiplexer 24. When no serial data is received by the receiving device 10, none of the comparators 22 detects a match and outputs a match flag of “0”. For this reason, all the comparison pattern selection signals are set to “0”, and the comparison data of the first 32 bits length (L bit length) of the specific pattern of 64 bits length (M bit length) is sent from all the multiplexers 24. Entered. Then, the comparator 22 compares each of the 32 storage patterns with the first half comparison pattern for each corresponding bit. As a result, when serial data is received, the pattern match flag corresponding to the storage pattern in which a match with the comparison pattern in the first half is detected becomes “1”.

  Here, as shown in the upper side of FIG. 3, for example, of the 32 storage patterns, the storage pattern 2 starting from the second bit (K bit) from the top of the parallel data DATA1, and the first comparison pattern Is detected in a certain cycle. At this time, the 32-bit portion of the latter half following the 32-bit portion of the first half of the 64-bit specific pattern in which a match with the comparison pattern of the first half is detected is the second bit of DATA1, which is the storage position of the storage pattern 2. To the first bit of DATA2, and is expected to be stored in the storage position from the second bit of DATA2. However, in this cycle, the last 2 bits of the 32 bits in the latter half are not stored in DATA2.

  The lower side of FIG. 3 shows a comparison between the storage pattern and the comparison pattern performed within the next period of the period in which the coincidence between the storage pattern 2 and the first half comparison pattern is detected in this way. In the upper part of FIG. 3, the latter 32-bit portion following the 32-bit portion of storage pattern 2 in which a match with the first-half comparison pattern is detected is shifted to storage location 2 and stored within the next cycle. Expected to be. Therefore, in order to detect the latter half in the next cycle, the pattern detection circuit 18 detects the comparison pattern selection signal corresponding to the storage pattern 2 when the pattern matching flag [2] corresponding to the storage pattern 2 becomes “1”. Only [2] becomes “1” in the next cycle.

  When the comparison pattern selection signal [2] becomes “1”, the pattern comparison circuit 16 outputs the comparison data of the latter half 32 bits (J bits) from the multiplexer 2 corresponding to the storage pattern 2. Thereby, the comparator 2 corresponding to the storage pattern 2 of the pattern comparison circuit 16 is expected to store the latter 32 bits of the specific pattern and the latter 32 bits of comparison data. And compare. When a match is detected, the corresponding pattern match flag [2] becomes “1”.

  In the pattern detection circuit 18, when the pattern match flag [2] corresponding to the storage pattern 2 in which a match with the latter comparison pattern is detected becomes “1”, that is, a match with the first comparison pattern is detected in a certain cycle. Then, when a match with the latter half comparison pattern is detected in the next cycle, only the detection signal [2] corresponding to the storage pattern 2 becomes “1” in the next cycle, and the position of the storage pattern 2 It is detected that serial data including a specific pattern has been received.

  On the other hand, when the comparator 2 does not detect a match with the latter half, the pattern match flag [2] is not “1”, and the detection signal is not “1”. That is, detection of coincidence with the first half part in the previous cycle is considered to be erroneous detection due to noise or the like, so it is not determined that serial data has been received. In the period in which the comparator 2 performs comparison with the latter comparison pattern, the first half comparison pattern is input to the comparators 0 to 1 and 3 to 31 except the comparator 2, and the comparison patterns with the respective storage patterns. A comparison is made. Therefore, when a match between any storage pattern and the first half is detected, the comparison with the second half is performed within the next cycle. Thus, even when serial data is received immediately after the first half of the storage pattern 2 is erroneously detected, it can be detected if the first half of the specific pattern can be stored with a storage pattern other than 2.

  Similarly, when a match between a storage pattern other than 2 and the comparison pattern in the first half is detected, the second half of the specific pattern can be detected in the next cycle to detect the reception of serial data.

  As shown in FIG. 3, when a specific pattern is detected in 32 bits, that is, divided into portions equal to the parallel data width, the storage pattern matches the comparison pattern in the first half within the first period of the parallel clock. Next, the second half of the specific pattern that needs to be matched with the latter comparison pattern is detected with the first comparison pattern within the next period of the parallel clock. Stored in the same storage location as the storage pattern.

  When a match between a storage pattern and the first half comparison pattern is detected, a match between the second half comparison pattern and the first half comparison pattern needs to be detected next. The number of periods from the detection to the next parallel clock period where it is necessary to detect the coincidence with the comparison pattern in the latter half changes according to the range of consecutive N bits, K, N, q, r. .

  That is, when a storage pattern that matches the comparison pattern in the first half is detected, the storage state of the storage pattern that needs to be detected as a match with the comparison pattern in the second half is regular, and there are consecutive N It is determined in one way by the bit range, K, N, r. Further, the number of cycles from when a storage pattern that matches a specific pattern is detected until the next storage pattern that needs to be detected to match the specific pattern is stored in the reception pattern storage register 14 is also regulated. And is uniquely determined by K, N, q, and r.

  This will be specifically described below with reference to the timing chart of FIG.

  In the timing chart shown in the figure, first, the comparator 2 detects the coincidence between the storage pattern 2 and the first half comparison pattern in the third period, and the pattern coincidence flag [2] is “1”. Therefore, the comparison pattern selection signal [2] becomes “1” in the subsequent fourth period. In addition, the coincidence between the next storage pattern and the latter comparison pattern is continuously detected in the same fourth period, and the pattern coincidence flag 2 maintains “1” for two consecutive periods. Therefore, the detection signal [2] becomes “1” in the same fourth period. Thereby, it is detected that serial data including the specific pattern is received.

  Next, the comparator 29 detects a match between the storage pattern 29 and the first half comparison pattern in the tenth cycle, and the pattern match flag [29] is “1”. The selection signal [29] becomes “1”. However, since the coincidence between the next storage pattern and the latter comparison pattern is not detected in the same 11th cycle, the pattern match flag [29] is not maintained at “1” for 2 consecutive cycles. Accordingly, the comparison result [29] corresponding to the storage pattern [29] returns to “0” in the same eleventh cycle.

  Next, the comparator 0 detects the coincidence between the storage pattern 0 and the first half comparison pattern in the 12th cycle, but the next 13th cycle detects the coincidence between the next storage pattern and the second half comparison pattern. Not. Therefore, the comparison pattern selection signal [0] is “1” in the thirteenth period, but the detection result [0] remains “0” in the same thirteenth period.

  Finally, the comparator 31 detects a match between the storage pattern 31 and the first half comparison pattern in the thirteenth cycle, and continuously detects a match between the next storage pattern 31 and the second half comparison pattern in the fourteenth cycle. Has been. Therefore, the detection result [31] is “1”.

  As described above, even in the same cycle, all the comparators 0 to 31 do not compare each of the 32 stored patterns with the first half comparison pattern or the second half comparison pattern. Depending on the result, each comparator compares each of the 32 stored patterns with the first half comparison pattern or the second half comparison pattern.

  Hereinafter, it will be described that the receiving apparatus of the present invention is applicable regardless of the value of the bit length M of the specific pattern and the bit width N of the parallel data.

  First, a case where the bit length M of the specific pattern is not an integral multiple of the bit width N of the parallel data, for example, a case where M = 66 and N = 32 will be described.

  FIG. 29 is a circuit diagram illustrating an example of a configuration of a conventional receiving apparatus. The receiving apparatus 110 shown in the figure is different from the conventional receiving apparatus 90 shown in FIG. 25 except that the reception pattern storage register 84C is configured by three stages of 32-bit FFs 86C connected in series. The same configuration is provided.

  The reception pattern storage register 84 </ b> C of the reception device 110 always stores the latest four cycles of parallel data DATA <b> 1 to 4 using the register of the serial / parallel conversion circuit 82 as the first register. In the reception pattern storage register 84C, as shown in FIG. 30, there are 32 types of 66 bits starting from the least significant bit of the parallel data DATA1 in the range of 32 bits consecutive in the order received as serial data. There is a possibility that a specific pattern is stored in the bit storage position.

  In this receiving apparatus 110, 32 comparators (comparators 0 to 31) 92A each of 66-bit length storage patterns stored in 32 storage positions in the parallel data DATA1 to 4 for four cycles. And a 66-bit specific pattern are compared at a time.

  Next, FIG. 5 is a circuit diagram of the second embodiment showing the configuration of the receiving apparatus of the present invention. Similarly, the receiving apparatus 40 shown in FIG. 1 includes a serial / parallel conversion circuit 12, a reception pattern storage register 14A, a pattern comparison circuit 16A, and a pattern detection circuit 18A.

  The serial-parallel conversion circuit 12 is the same as the receiving device 10 shown in FIG.

  The reception pattern storage register 14A uses the register of the serial-parallel conversion circuit 12 as a first register, and has two stages of 32-bit (N-bit) FFs 20A1 and 20A2 connected in series as the second register. ing. The reception pattern storage register 14 always stores the latest three periods of parallel data DATA1 to DATA3. As shown in FIG. 7, each bit in the range from the least significant bit (DATA [0]) of the parallel data DATA1 to 32 bits (N bits) consecutive in the order received as serial data is received from the reception pattern storage register 14A. 33-bit (L-bit) storage patterns 0-31 stored in 32 (N-way) storage positions 0-31 starting from the top are output. In addition, the reception pattern storage register 14A also outputs a 33-bit storage pattern 32 stored in the storage position 32 starting from the 32nd bit following the continuous 32-bit range.

  The pattern comparison circuit 16 </ b> A includes 33 (N + 1) comparators (comparators 0 to 32) 22 and 31 (N−1) multiplexers 24.

  The configurations of the comparators 0 to 32 of the comparator 22 are the same as those shown in FIG. 2 except that the number of EXOR circuits is 33.

  Here, when the multiplexers corresponding to the comparators 1 to 31 are expressed as multiplexers 1 to 31, the multiplexers 1 to 31 each have 66 bits according to the corresponding bits of the comparison pattern selection signal [1:31]. From the long specific pattern [65: 0], the first half 33-bit length (L-bit length) comparison pattern or the second half 33-bit length (J-bit length) comparison pattern is output.

  The specific pattern [32: 0] is input to the input terminals 0 of the multiplexers 1 to 31 and the specific pattern [65:33] is input to the input terminals 1 in common to all the multiplexers 1 to 31 and the selection terminals are connected to the selection terminals. The respective bits of the comparison pattern selection signal [1:31] are input to the corresponding multiplexers 1 to 31. Each of the multiplexers 1 to 31 outputs a specific pattern [32: 0] that is the first comparison pattern [32: 0] when the comparison pattern selection signal is “0”. In the case of “1”, the specific pattern [65:33] that is the latter comparison pattern [32: 0] is output.

  The comparator 0 always receives the specific pattern [32: 0] as the first half comparison pattern [32: 0], and the comparator 32 always receives the second half comparison pattern [32: 0]. The specific pattern [65:33] is input.

  As shown in FIG. 6, the pattern detection circuit 18 </ b> A includes 32 sets of AND circuits 30, FFs 32, and AND circuits 34 corresponding to the comparators 0 to 31 as shown in FIG. 1. . Note that a circuit corresponding to the comparator 32 is not provided (unnecessary). The AND circuit 34 that outputs the detection signal [n] receives the comparison pattern selection signal [n + 1] and the pattern match flag [n + 1].

  The comparator 0 always compares the storage pattern 0 with the first half comparison pattern, and the comparator 32 always compares the storage pattern 32 with the second half comparison pattern. Therefore, the comparison pattern selection signals [0] and [32] are not necessary as selection signals for the multiplexer 24. However, the comparison pattern selection signal [0] is not generated, but the comparison pattern selection signal [32] is generated and is used inside the pattern detection circuit 18A.

  In the detection signal [n], the comparison pattern selection signal [n + 1] is “1”, that is, the comparison result between the storage pattern one cycle before and the first half comparison pattern is coincident, and the pattern coincidence flag [n + 1] is set. “1”, that is, when the comparison result between the storage pattern of the current period and the comparison pattern of the second half is coincident, that is, coincidence in two consecutive periods, that is, “1” when the entire specific pattern is detected It becomes.

  Next, the operation of the receiving device 40 will be described.

  The operation until the latest three cycles of parallel data DATA1 to DATA3 are stored in the reception pattern storage register 14 is the same.

  In the pattern comparison circuit 16A, all comparison pattern selection signals are first set to “0”, and the first half comparison data is output from all the multiplexers 24. Then, the comparator 22 compares each of the storage patterns 0 to 31 with the first half comparison pattern for each corresponding bit. As a result, when the serial data is received, the pattern match flag [n] corresponding to the storage pattern #n where the match is detected becomes “1”.

  Here, as shown in the upper side of FIG. 7, the storage pattern 2 stored in the storage position starting from the second bit (K bit) from the head of the parallel data DATA1 in a certain cycle and the comparison pattern of the first half Assume that a match is detected and the pattern match flag [2] becomes “1”. Storage position 2 is a range from the second bit of DATA1 to the second bit of DATA2. The 33 bits of the latter half following the 33 bits of the first half of the specific pattern stored in this storage range are stored in the range from the third bit of DATA2 to the third bit of DATA3 within the same parallel clock period. Yes. In the next cycle of the parallel clock, it is expected to be stored in the storage position from the third bit of DATA1 to the third bit of DATA2, that is, storage position 3. In this way, since the bit length 33 of the first half part of the specific pattern stored in each storage position is one larger than the bit width 32 of the parallel data, the second half part is stored in the storage position with a number larger by one. Is done.

  In order to detect the latter half, in the pattern detection circuit 18A, when the pattern match flag [2] becomes “1”, only the comparison pattern selection signal [3] is set to “1” in the next cycle.

  When the comparison pattern selection signal [3] becomes “1”, in the pattern comparison circuit 16A, the latter half 32-bit length (J-bit length) comparison data is output from the multiplexer 3, and the other multiplexers 1-2, 4- From 31, the first half comparison pattern is output.

  Then, the storage pattern 3 is compared with the comparison pattern of the latter half by the comparator 3 as shown in the lower side of the figure after one cycle from the upper side of the figure. On the other hand, for the storage patterns 0 to 2 and 4 to 31 other than the storage pattern 3, the comparison with the comparison pattern of the first half is continued by the comparators 0 to 2 and 4 to 31.

  In the pattern detection circuit 18A, when the pattern match flag [3] corresponding to the storage pattern 3 becomes “1”, that is, a match with the comparison pattern in the first half is detected in a certain cycle, and then the latter half in the next cycle. When a match with the comparison pattern is detected, only the detection signal [2] becomes “1” in the next cycle, and it is detected that serial data including the specific pattern is received from the position of the storage pattern 2. Similarly, when a match between a storage pattern other than 2 and the comparison pattern in the first half is detected, the second half of the specific pattern can be detected in the next cycle to detect the reception of serial data.

  On the other hand, as shown in the upper side of FIG. 8, a match between the storage pattern 31 starting from the 31st bit (Kth bit) from the top of the parallel data DATA1 and the first half comparison pattern is detected in a certain cycle, and the pattern match Assume that the flag [31] becomes “1”. When 33 bits of the first half part of the specific pattern are stored in the storage position 31 from the 31st bit of DATA1 to the 31st bit of DATA2, the 33 bits of the latter half part are transferred to DATA3 within the same parallel clock period. From the 0th bit. This second half is expected to be stored in the storage location 32 from the 0th bit of DATA2 to the 1st bit of DATA3 within the next period of the parallel clock.

  In the pattern detection circuit 18A, when the pattern match flag [31] becomes “1”, only the comparison pattern selection signal [32] becomes “1” in the next cycle. The pattern selection signal [32] is not used for controlling the multiplexers 1 to 31 of the pattern comparison circuit 16A. For this reason, the first half of the specific pattern is supplied to the comparators 0 to 31 as a comparison pattern. However, the comparator 32 always supplies the 33 bits of the latter half of the specific pattern as a comparison pattern.

  Then, the storage pattern 32 is compared with the comparison pattern in the latter half by the comparator 32 as shown in the lower side of the figure after a state one cycle after the upper side of the figure.

  In the pattern detection circuit 18A, when the pattern match flag [32] corresponding to the storage pattern 32 becomes “1”, that is, a match with the first half comparison pattern is detected in a certain cycle, and then the second half in the next cycle. When a match with the comparison pattern is detected, only the detection signal [31] becomes “1” in the next cycle, and it is detected that serial data including the specific pattern is received at the position of the storage pattern 31.

  In the receiving apparatus 40 of FIG. 5, when a match between the storage pattern 31 and the first half comparison pattern is detected in a certain cycle of the parallel clock, in order to detect a match with the second half comparison pattern in the next cycle, The 33rd comparator 32 is provided. This is because when the coincidence between the storage pattern 31 and the first half comparison pattern is detected, the second half of the specific pattern is expected to be stored in the storage position 32 within the next period of the parallel clock. . Therefore, it is necessary to provide the comparator 32 separately from the comparators 0 to 31 provided for comparing the storage patterns 0 to 31 with the comparison pattern. Further, the reception pattern storage register 14A includes two FFs 20A1 and 20A2 as the second storage register so that the entire second half of the 33-bit length stored in the storage location 32 can be stored. did.

  Note that the latter half portion expected to be stored in the storage location 32 within the next cycle is expected to be stored at storage location 0 within the next cycle. Therefore, when a match between the storage pattern 31 and the first comparison pattern is detected, the comparison between the storage pattern 0 and the second comparison pattern is performed using the comparator 0 after two cycles of the parallel clock. It is possible to detect a match with a part. However, when a match between the storage patterns 0 to 30 and the comparison pattern in the first half is detected, a match with the latter half is detected within the next cycle of the parallel clock using the comparators 1 to 31. On the other hand, only when the coincidence with the first half part is detected at the storage position 31, in order to detect the coincidence with the second half part in different periods, complicated control is required. In order to avoid this, in the receiving apparatus 40 of FIG. 5, by adding the comparator 32, when a match between any of the 32 types of storage patterns 0 to 31 and the comparison pattern of the first half is detected, In the same period, that is, in the next period, it is possible to detect a coincidence with the latter half.

  As described above, the receiving apparatus of the present invention is not limited to the case of M = 66 and N = 32, and the bit length M of the specific pattern is an integer multiple of the bit width N of the parallel data or any integer multiple. Even in such a combination, it operates correctly.

  Next, a case where the bit width N of the parallel data is not 32 bits, for example, a case where M = 64 and N = 16 will be described.

  When the bit width N of the parallel data is 16 bits as in the receiving device 120 shown in FIG. 31, for example, the received serial data of 10 Gbps is converted into 625 MHz, 16-bit parallel data by the serial / parallel conversion circuit 82D. The

  The reception pattern storage register 84D always stores the latest five cycles of parallel data DATA1 to DATA5. In the reception pattern storage register 84D, as shown in FIG. 32, a 64-bit specific pattern includes, for example, each bit in a 16-bit range that is consecutive in the order received as serial data from the least significant bit of the parallel data DATA1. There is a possibility that the data is stored in 16 storage positions, which are the head.

  In this receiving apparatus, each of 16 types of 64-bit width storage patterns included in parallel data DATA1 to 5 for five cycles and a specific pattern of 64-bit length are compared at a time by 16 comparators. Is done.

  Next, FIG. 9 is a circuit diagram of a third embodiment showing the configuration of the receiving apparatus of the present invention. Similarly, the receiving device 50 shown in FIG. 1 includes a serial / parallel conversion circuit 12B, a reception pattern storage register 14B, a pattern comparison circuit 16B, and a pattern detection circuit 18B. The receiving apparatus 50 according to the third embodiment includes 16 (N), 64-bit (M-bit width) storage patterns, and a 64-bit (M-bit length) specific pattern, 16 bits. Compare (L bit or J bit) in 4 cycles in 4 cycles.

  The serial-parallel conversion circuit 12B is the same as the receiving apparatus 10 shown in FIG. 1, and generates parallel data DATA2 having a 16-bit width (N-bit width).

  The reception pattern storage register 14B is the same as the reception device 14 shown in FIG. 1, and uses the register of the serial / parallel conversion circuit 12B as the first register and 16 bits (N bits) as the second register. FF20B is provided.

  The pattern comparison circuit 16 </ b> B includes 16 (N) comparators (comparators 0 to 15) 22 </ b> B and a comparison pattern selection unit 36.

  Each comparator 0-15 of the comparator 22 is the same as the comparator shown in FIG. 2, and as shown in FIG. 10, there are 16 EXOR circuits 26B for comparing the storage pattern and the comparison pattern. And a NOR circuit 28B.

  The comparison pattern selection unit 36 includes 16 multiplexers 24B shown in FIG. Each multiplexer 24B, in response to the comparison pattern selection signal [n], selects a 16-bit specific pattern (L-bit length) as a first comparison pattern from the 64-bit specific pattern [63: 0]. [15: 0], 16-bit specific pattern [31:16] as the second comparison pattern, 16-bit specific pattern (J-bit length) as the third comparison pattern [47 : 32] or a specific pattern [63:48] having a 16-bit length (J-bit length) to be the fourth comparison pattern.

  As shown in FIG. 12, the pattern detection circuit 18B includes 16 sets of multiplexers 38, FFs 32, an adder (+1) 42, a comparator (= 3) 44, an AND corresponding to the comparators 0 to 15. Circuit 34.

  In the pattern detection circuit 18B, when the pattern match flag [n] is “0”, the output signal of the multiplexer 38 becomes “0”, and this is held in the FF 32 in synchronization with the parallel clock. Therefore, the comparison pattern selection signal [n] that is the output signal of the FF 32 is “0”, and the output signal of the adder 42 is “1”. Further, since the pattern match flag [n] is “0”, the detection signal [n] that is the output signal of the AND circuit 34 is also “0”.

  When the pattern match flag [n] becomes “1”, the output signal of the multiplexer 38 becomes “1”, and this is held in the FF 32 in the next cycle, so that the comparison pattern selection signal [n] becomes “1” and the addition is performed. The output signal of the device 42 is “2”. The comparator 44 detects whether or not the comparison pattern selection signal [n] is “3”. At this time, since the output signal of the comparator 44 is “0”, the detection signal [n] is It becomes “0”.

  Similarly, when the pattern match flag [n] is continuously “1” for four periods, the comparison pattern selection signal [n] is “3” and the output signal of the comparator 44 is “1”. Thus, the detection signal [n] is “1”. When the pattern match flag [n] becomes “0” even once during the four cycles, the output signal of the multiplexer 38 becomes “0”, and this is held in the FF 32 in the next cycle, and the comparison pattern selection signal [ n] and the detection signal [n] are “0”.

  The comparison pattern selection signal [n] is a 2-bit signal, and the pattern match flag [n] is continuously set to “1” i times (i = 1 to 4), that is, the storage pattern and the comparison pattern are different. When the i circuits continuously match, “i” is obtained in the next cycle. Further, the detection signal [n] becomes “1” when the pattern matching flag [n] is continuously “4” four times, that is, when the storage pattern and the comparison pattern are continuously matched four times.

  Next, the operation of the receiving device 50 will be described.

  The operation until the latest two cycles of parallel data DATA1-2 are stored in the reception pattern storage register 14 is the same.

  In the pattern comparison circuit 16B, all the comparison pattern selection signals are first set to “0”, and the first comparison pattern is output from all the multiplexers 24B of the comparison pattern selection unit 36. Then, the comparator 22 compares each of the storage patterns 0 to 15 with the first comparison pattern for each corresponding bit. As a result, when the serial data is received, the pattern match flag [n] corresponding to the storage pattern #n where the match is detected becomes “1”.

  Here, as shown on the upper side of FIG. 13, 16 storage positions 0 to 15 starting from each bit in a range of 16 bits continuous from 0 bits of DATA1 are considered. Then, in a certain cycle, the storage pattern 2 and the first comparison pattern (in FIG. 13, the first to fourth comparison patterns) starting from the second bit (K bit) from the top of the parallel data DATA1, Comparison pattern 1/4, comparison pattern 2/4, comparison pattern 3/4, and comparison pattern 4/4) are detected, and the pattern match flag [2] is set to “1”. To do.

  In this case, in the pattern detection circuit 18B, when the pattern matching flag [2] becomes “1”, the comparison pattern selection signal [2] becomes “1” in the next cycle.

  When the comparison pattern selection signal [2] becomes “1”, the second comparison data is input to the comparator 2 from the multiplexer 24B in the pattern comparison circuit 16B. The first comparison pattern is input to the other comparators 0 to 1 and 3 to 15.

  Then, the storage pattern 2 is compared with the second comparison pattern by the comparator 22 for the storage pattern 2 as shown in the lower side of the figure after the state on the upper side of the figure. On the other hand, for the storage patterns 0 to 1 to 3 to 15 other than the storage pattern 2, the comparator 22 continues to compare with the first comparison pattern.

  In the following order, when the pattern match flag [2] becomes “1” for two consecutive cycles, the comparison pattern selection signal [2] further becomes “2” in the next cycle, and the third comparison data is sent from the multiplexer 24B. The stored pattern 2 is compared with the third comparison pattern as shown in the upper side of FIG. 14 after one cycle from the lower side of the figure. When the pattern match flag [2] becomes “1” for three consecutive cycles, the comparison pattern selection signal [2] becomes “3” in the next cycle, and the fourth comparison data is output from the multiplexer 24B. Then, the storage pattern 2 is compared with the fourth comparison pattern, as shown in the lower side of the figure after one cycle from the upper side of the figure.

  When the pattern match flag [2] becomes “1” for 4 consecutive cycles, that is, a match between the storage pattern 2 and the first comparison pattern is detected in a certain cycle, and then stored for 3 consecutive cycles. When a match between the pattern 2 and the second to fourth comparison patterns is detected, the detection signal [2] becomes “1” in the next cycle, and it is detected that serial data including the specific pattern has been received. .

  When the pattern match flag [n] corresponding to the storage patterns 0 to 1, 3 to 15 is “1”, the comparison pattern selection signal [n] corresponding to the pattern match flag [n] of “1” is stored. ] Becomes “1” in the next cycle, and then the above-described operation is repeated.

  As described above, the receiving apparatus of the present invention is not limited to the case where M = 64 and N = 16, and operates correctly regardless of the value of the bit width N of parallel data.

  Next, a case where a communication error is allowed will be described.

  In the conventional receiving apparatus, the configuration for allowing a communication error is as shown in FIGS. 27 and 28 as described above.

  That is, in this receiving apparatus 100, in each comparator 92B (comparators 0 to 31), the adder 98B adds the comparison results from 64 EXOR circuits 94A. The result is output as it is, and if it is 15 or more, 15 is output. When the number of communication errors as a result of addition is less than the maximum allowable mismatch bit number 15, it is considered that a match is detected by the magnitude comparison circuit 102B, and the pattern match flag becomes “1”.

  Next, FIG. 15 is a circuit diagram of the fourth embodiment showing the configuration of the receiving apparatus of the present invention. The receiving device 60 shown in the figure is compared with the receiving device 10 of the first embodiment shown in FIG. 1 in each comparator (comparators 0 to 31) 22C of the pattern comparison circuit 16C with the maximum allowable number of mismatch bits. The configuration is the same except that (the maximum number of communication errors allowed while detecting a specific pattern of one block) is input.

  Each of the comparators 22C is the same as the comparator 92B shown in FIG. 28 except that it includes 32 EXOR circuits 26 and a 1-bit right shift circuit 46 as shown in FIG. Of the configuration. In this comparator 22C, the maximum allowable mismatch bit number is shifted by 1 bit to the right (the least significant bit side) by the 1-bit right shift circuit 46, the value is halved, and the magnitude comparison circuit 52 A comparison is made between the number of communication errors, which is the output signal of the adder 48, and a value that is ½ of the maximum allowable mismatch bit number.

  In this receiving device 60, each of 32 types of 64-bit width storage patterns and a 64-bit specific pattern are compared in two cycles, divided into two parts, 32 bits for the first half and the second half. Therefore, the maximum allowable mismatch bit number is halved and communication errors up to half of the maximum allowable mismatch bit number are allowed in one comparison. As a result, if the number of communication errors is less than or equal to the maximum allowable mismatch bit number in two comparisons, it is guaranteed that a match with a specific pattern is detected.

  As described above, the receiving apparatus of the present invention is not limited to the case where the comparison is performed in two cycles divided into two times, and the maximum allowable mismatch bit number is 1 / n even when the comparison is performed in n cycles divided into n times. Will work correctly.

  Note that in the receiving device 60 of the fourth embodiment, the inspection of the maximum allowable mismatch bit number may be too strict. That is, when the comparison is made in n cycles divided into n times, the number of communication errors in each cycle varies. For example, the number of communication errors exceeds 1/2 of the maximum allowable mismatch bit number in the first comparison, but the number of communication errors is zero in the second comparison. In this case, the total number of communication errors in the two comparisons is less than the maximum allowable mismatch bit number, but it is determined that the specific pattern has not been detected.

  The fifth embodiment corresponds to this problem. The fifth embodiment will be described below.

  FIG. 17 is a circuit diagram of the fifth embodiment showing the configuration of the receiving apparatus of the present invention. Compared with the receiving apparatus 10 of the first embodiment shown in FIG. 1, the receiving apparatus 70 shown in FIG. 1 includes each of the comparators 22D (comparators 0 to 31) of the pattern comparison circuit 16D and the pattern detection circuit 18D. The configuration is the same except that the configuration is different.

  As shown in FIG. 18, each comparator 22D includes an adder 48 instead of the NOR circuit 28 as compared with the comparator 22 shown in FIG. The adder 48 adds the output signals of all the EXOR circuits 26, and the adder 48 outputs a 4-bit communication error number as a result of the addition.

  As shown in FIG. 19, the pattern detection circuit 18D includes an FF 54, an adder 56, a first magnitude comparison circuit 58, an AND circuit 30, an FF 32, and a second magnitude comparison circuit 62. . Although not shown, these are provided with 32 sets of circuits corresponding to 32 pattern matching flags [31: 0].

  First, in the pattern comparison circuit 16D, the comparator 22D compares each of the 32 stored patterns with the first half comparison pattern (first comparison). As a result, the first communication error number is output from each comparator 22D.

  In the pattern detection circuit 22D, the first size comparison circuit 58 compares the first communication error number with the maximum allowable mismatch bit number. As a result, if the first communication error number is less than the maximum allowable mismatch bit number, it is considered that a match has been detected in the first comparison, and the output signal of the first magnitude comparison circuit 58 becomes “1”. In synchronization with the parallel clock, the comparison pattern selection signal, which is the output signal of the FF 32, becomes “1” in the next cycle.

  Subsequently, in the pattern comparison circuit 16D, the comparison pattern in the latter half is output from the multiplexer 24 in which the comparison pattern selection signal is “1” as a result of the first comparison. Then, the comparator 22D to which the latter half comparison pattern is inputted compares the stored pattern with the latter half comparison pattern. As a result, the second communication error number is output from the comparator 22D to which the latter comparison pattern is input.

  Similarly, in the pattern detection circuit 18D, the first magnitude comparison circuit 58 compares the second communication error number with the maximum allowable mismatch bit number. However, as described above, since the comparison pattern selection signal is a one-shot signal, the comparison pattern selection signal that is “1” as a result of the first comparison is the output signal of the first magnitude comparison circuit 58, that is, Regardless of the value of the second comparison result, it returns to “0” in the next cycle.

  In the pattern detection circuit 18D, when the first communication error number is output from the comparator 22D, the first communication error number is held in the FF 54 in the next cycle. When the second communication error number is output from the comparator 22D in the same next cycle, the adder 56 outputs the first communication error number that is the output signal of the FF 54 and the comparator 22D. The second communication error number is added and the adder 56 outputs the total communication error number for the first and second times. Note that the output signal of the adder 56 is a 5-bit signal in consideration of the occurrence of a carry when the numbers of 4-bit communication errors are added.

  Then, the second magnitude comparison circuit 62 compares the total number of first and second communication errors, which is the output signal of the adder 56, with the maximum allowable mismatch bit number. As a result, if the total number of communication errors for the first time and the second time is less than the maximum allowable number of mismatch bits, it is considered that a match has been detected in the second comparison, that is, both the first and second comparisons. The detection signal that is the output signal of the second magnitude comparison circuit 62 becomes “1”.

  As described above, in the case of the receiving device 70 of the fifth embodiment, when the comparison is performed in n cycles divided into n times, even if the number of communication errors in each cycle varies, the first and second times. If the total number of communication errors is below the maximum allowable number of mismatch bits, it is considered that a match has been detected. Therefore, even when a communication error is allowed, the specific pattern can be detected while correctly determining the number of communication errors.

  As described above, according to the present invention, the number of EXOR circuits of the comparator can be reduced, so that the circuit scale of the receiving apparatus can be reduced. For example, even when a communication error is not allowed in detection of a specific pattern, when the receiving apparatus of the present invention is compared with a conventional receiving apparatus, for example, when M = 64, N = 32, L = 32, and J = 32, In the receiving apparatus of the present invention, about 1000 EXOR circuits can be reduced. Thus, according to the present invention, there are effects such as chip cost reduction and layout easiness improvement by reducing the circuit scale.

  In the receiving apparatus of the present invention, it is necessary to add a circuit such as a multiplexer in order to switch between the first half comparison pattern and the second half comparison pattern, but the effect of reducing the EXOR circuit is greater.

  Note that the bit width of the parallel data stored in the reception pattern storage register 14, the range of consecutive N bits, the allowable number of bit errors, and the like are not particularly limited.

  In each of the above embodiments, L = J in the first and second comparisons or the first to fourth comparisons. That is, M = I · L (I is an integer of 2 or more). However, this is not limited. For example, when the bit length M of the entire specific pattern is an odd number, both values may be different. In addition, the case where the comparison is completed by the second time is the same as the case where the third and subsequent comparisons are necessary. When the third and subsequent comparisons are necessary, for example, L and J are set at the time of the last comparison. It may be set differently.

  The receiving apparatus of the present invention can detect a specific pattern from serial data including a specific pattern having a predetermined bit length set in advance, such as an end of burst, as well as a preamble.

  Further, in the case of the receiving apparatus of the second embodiment, when a match with any of the storage patterns is detected when a match with the comparison pattern in the first half is detected, in the next cycle, Although the coincidence with the comparison pattern in the latter half is detected, this is not limited.

  For example, when M = 66, N = 32, L = 33, q = 1, and r = 1, as shown in the upper side of FIG. 20, each bit in the range of consecutive 32 bits (N bits) is set as the head. When a match with the first half comparison pattern is detected in each of the storage patterns 0 to 31 to be performed, the latter 33 bits of the specific pattern following the first 33 bits (L bits) In this period, as shown on the lower side of FIG. Among these, the storage patterns 1 to 31 are detected by using the comparators 1 to 31 used for comparing the storage patterns 1 to 31 and the comparison pattern of the first half in the first half of the match detection. Is possible. On the other hand, the storage pattern 32 cannot detect the coincidence with the comparison pattern in the second half, regardless of which of the comparators 0 to 31 used for the coincidence detection in the first half.

  However, when one more cycle is waited, the storage pattern 32 shifts to the storage position 0 as shown by the broken line at the bottom of FIG. Within this period, it is possible to detect a match with the latter comparison pattern by using the comparator 0 used for comparing the storage pattern 0 and the first comparison pattern in the first half match detection. This makes it necessary to control the period for detecting the second half match according to the storage pattern in which the first half match is detected, but the addition of the comparator 33 is not necessary.

  When M = 120, N = 32, L = 60, q = 1, and r = 28, as shown on the upper side of FIG. 21, each bit in the range of 32 bits continuous from the fourth bit of DATA1 is set. The first 60-bit part is set as storage positions 4 to 35, and the storage patterns 4 to 35 stored in the respective storage positions can be compared with the first 60-bit comparison pattern of the 120-bit specific pattern. it can. In this case, when a match between each of the storage patterns 4 to 35 and the comparison pattern of the first half is detected, the latter half of the 60 bits of the specific pattern is moved to the lower side of FIG. 21 after two cycles of the parallel clock. As indicated by the solid line, the data is expected to be stored in storage positions 0 to 31 starting from each bit in the range of 32 bits continuous from the 0th bit of DATA1.

  Among these, the storage patterns 4 to 31 can detect a match with the latter comparison pattern by using the comparators 4 to 31 used for the match detection with the first comparison pattern. However, the stored patterns 0 to 3 cannot detect a match with the comparison pattern in the latter half even if any of the comparators 4 to 35 used for the match detection in the first half is used. Therefore, four comparators 0 to 3 can be added in order to detect coincidence between these storage patterns 0 to 4 and the comparison pattern.

  However, from two cycles after the cycle in which the first-half match is detected, as shown by a broken line at the lower side of FIG. 21, one cycle before the cycle in which the first-half match is detected, The 60-bit portion of the latter half of the specific pattern is expected to be stored in storage locations 32-35. The storage patterns stored in the storage positions 32 to 35 are obtained by using the comparators 32 to 35 used for detecting the coincidence between the storage patterns 32 to 35 and the first comparison pattern in the first half detection. A match can be detected. This makes it necessary to control the period for detecting the second half match according to the storage pattern in which the first half match is detected, but does not require the addition of the comparators 0 to 3.

  In general, a larger number of comparators than the parallel clock bit width N are prepared, and the clock cycle for comparing the latter half is the same regardless of the head position (K value) of the storage pattern where the first half match is detected. It is possible to That is, within the first period of the parallel clock, the L bit part starting from the Kth bit (K = 0 to N−1) from the beginning of the range of consecutive N bits and the L bit from the beginning of the specific pattern When a coincidence with the portion is detected, the quotient of L / N is q, and too much is r, and within the cycle after q cycles from the first cycle, It is possible to detect a match. Specifically, when K <N−r, a J bit portion starting from the K + r bit from the beginning of the range of consecutive N bits, a J bit portion from the L + 1 bit of the specific pattern, and Find a match. When N−r ≦ K, the J bit portion starting from the K + r−N bit from the beginning of the r bit range immediately after the continuous N bit range and the L + 1 bit from the L + 1 bit of the specific pattern Detects a match with the bit part. For this purpose, the pattern comparison circuit 16 includes N first comparators for comparing the comparison pattern with the storage pattern starting with each bit in the range of consecutive N bits, and the consecutive N bits. R second comparators for comparing the storage pattern starting with each bit in the r-bit range immediately after the range and the comparison pattern. Then, following the detection of coincidence within the first period, the pattern detection circuit 18 performs the first comparison when K <N−r within the period after q periods from the first period. Serial data including a specific pattern on the condition that the comparator for comparing the comparison pattern with the storage pattern starting with the K + rth bit from the beginning of the range of consecutive N bits in the range has detected a match. Detect receipt of data. If N−r ≦ K, the storage pattern of the second comparator starting with the K + r−N-th bit from the beginning of the r-bit range immediately after the continuous N-bit range; The reception of serial data including the specific pattern is detected on the condition that the comparator that performs comparison with the comparison pattern has detected a match.

  Alternatively, it is also possible to detect the coincidence with the portion of the J + 1 bit from the (L + 1) th bit of the specific pattern within the cycle after q + 1 cycle from the first cycle. Specifically, when K <N−r, the J-bit portion starting from the K-th bit in the Nr-bit range immediately before the continuous N-bit range and the specific pattern The coincidence with the J bit portion from the (L + 1) th bit is detected. When N−r ≦ K, the J bit portion starting from the K + r−N bit from the beginning of the range of consecutive N bits is matched with the J bit portion from the L + 1 bit of the specific pattern. To detect. For this purpose, the pattern comparison circuit 16 includes N first comparators for comparing the comparison pattern with the storage pattern starting with each bit in the range of consecutive N bits, and the consecutive N bits. Nr third comparators for comparing the storage pattern starting with each bit in the range of Nr bits immediately before the range and the comparison pattern. Then, following the detection of coincidence within the first period, the pattern detection circuit 18, when K <N−r, within the period after q + 1 period, of the third comparator, Identified on the condition that the comparator that compares the comparison pattern with the storage pattern starting with the Kth bit from the beginning of the Nr bit range immediately before the range of consecutive N bits has detected a match Detection of reception of serial data including a pattern. If N−r ≦ K, the comparison pattern is compared with the storage pattern of the first comparator starting with the K + r−Nth bit from the beginning of the range of consecutive N bits. The reception of serial data including a specific pattern is detected on condition that the comparator detects a match.

  Here, in order to reduce the number of second or third comparators to be added, when r is smaller than N / 2 as in the example shown in FIG. It is preferable to detect a match with the J bit portion. On the other hand, when r is larger than N / 2 as in the example shown in FIG. 21, it is preferable to detect the coincidence with the J-bit portion within the period after q + 1 period.

  In general, it is also possible to limit the number of required comparators to N by changing the parallel clock period for performing the latter half comparison as necessary. When a match is detected between the L-bit portion starting from the beginning of the K-th bit in the range of consecutive N bits and the L-bit portion from the beginning of the specific pattern within the first period of the parallel clock , If K <N−r, within the period after q period from the first period, specify the J bit part starting with the K + r bit from the beginning of the range of consecutive N bits A match with the J bit portion from the (L + 1) th bit of the pattern is detected. If N−r ≦ K, within a period after q + 1 period from the first period, a portion of J bits starting from the K + r−Nth bit from the beginning of the range of consecutive N bits, A match with the portion of the J bit from the (L + 1) th bit of the specific pattern is detected. The pattern comparison circuit includes N comparators for comparing the comparison pattern with the storage pattern starting with each bit in the range of consecutive N bits, and the pattern detection circuit includes the first comparator within the first cycle. Following the detection of coincidence, if K <N−r, K + r bits from the beginning of the range of consecutive N bits of the N comparators within a period after q periods from the first period. The reception of serial data including the specific pattern is detected on the condition that the comparator that compares the storage pattern starting with the bit of the eye and the comparison pattern detects a match. If N−r ≦ K, within the period after q + 1 period from the first period, the K + r−Nth bit from the beginning of the range of consecutive N bits of the N comparators The reception of the serial data including the specific pattern is detected on the condition that the comparator that compares the stored pattern and the comparison pattern detects a match.

  In this case, the pattern comparison circuit, for example, compares the storage pattern starting with each bit in the range of consecutive N bits of the bits constituting the parallel data stored in the reception pattern storage register and the specific pattern. N comparators for comparing with the pattern are provided.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 40, 50, 60, 70, 80, 90, 110, 120 Receiving device 12, 12B, 82, 82D Serial to parallel conversion circuit 14, 14A, 14B, 84, 84A, 84C, 84D Reception pattern storage register 16, 16A , 16B, 16C, 16D, 88A, 88B Pattern comparison circuit 18, 18A, 18B, 18D Pattern detection circuit 20, 20A1, 20A2, 20B, 32, 54, 86, 86A, 86C Flip-flop (FF)
22, 22B, 22C, 22D, 44, 92A, 92B Comparator 24, 24B, 38 Multiplexer 26, 26B, 94A EXOR circuit 28, 28B, 96A NOR circuit 30, 34 AND circuit 36 Comparison pattern selection unit 42, 48, 56 , 98B Adder 46 1-bit right shift circuit 52, 58, 62, 102B Size comparison circuit

Claims (7)

A receiving apparatus for receiving serial data including a detection target portion having a known bit pattern having an M bit length,
A serial-parallel conversion circuit that generates parallel data of N bits (N <M) width by arranging the data of each bit constituting the received serial data in the order of reception;
A first register storing N-bit parallel data generated by the serial-parallel conversion circuit, and the parallel data stored in the first register are sequentially shifted and stored in synchronization with a parallel clock. A group of registers comprising one or more second registers to be
Each bit in the range of N bits consecutive in the order received as the serial data of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers is set as the head. A comparison circuit for comparing a portion of L bits (N ≦ L <M) to be compared with a corresponding portion of the known bit pattern;
The comparison circuit, the Oite the first cycle of the parallel clock, said bits forming the parallel data stored in said first register and said one or more second register at that time A match between an L-bit portion starting from the K-th bit (K = 0 to N−1) from the beginning of a range of consecutive N bits and an L-bit portion from the beginning of the known bit pattern is detected; Furthermore, the quotient of L / N q, the remainder as r, K, N, q, Oite within a particular period of the parallel clock determined by r, the first register and the one or more at that time the two bits constituting the parallel data stored in the register, the range of N bits, wherein the successive and K, N, J bits (J ≦ M to start a specific bit determined by r of L) and a detection circuit for detecting reception of the serial data on condition that a match between the L + 1 bit and the J bit portion from the (L + 1) th bit of the known bit pattern is detected. apparatus. The specific cycle is a cycle after q cycles from the first cycle of the parallel clock, and the specific bit is:
(1A) If K <N−r, it is the K + rth bit from the beginning of the range of consecutive N bits,
(2B) If N−r ≦ K, the K + r−N-th bit from the beginning of the r-bit range immediately after the continuous N-bit range.
Or
The specific period is a period after q + 1 period from the first period of the parallel clock, and the specific bit is:
(1B) If K <N−r, it is the Kth bit from the beginning of the range of Nr bits immediately before the range of consecutive N bits,
(2A) If N−r ≦ K, it is the K + r−Nth bit from the beginning of the range of the consecutive N bits.
The receiving apparatus according to claim 1. The comparison circuit is
A portion starting from each bit in the range of the consecutive N bits of the bits constituting a plurality of parallel data stored in the first register and the one or more second registers and the known bit Comprising N first comparators for comparison with corresponding parts of the pattern;
Each bit in the range of r bits immediately after the range of consecutive N bits of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers is set as the head. R second comparators for comparing a portion to be matched with a corresponding portion of the known bit pattern, and a plurality of parallels stored in the first register and the one or more second registers N-r comparisons are made between a portion starting with each bit in the range of Nr bits immediately before the range of consecutive N bits of the bits constituting the data and a corresponding portion of the known bit pattern. And at least one of the third comparator,
The detection circuit comprises:
The specific cycle is a cycle after q cycles from the first cycle,
(1A) If K <N−r, the portion of the first comparator starting with the K + r-th bit from the beginning of the continuous N-bit range and the known bit pattern Comparing with a corresponding portion of the J bit portion starting from the K + r bit and the L + 1 bit to J bit portion of the known bit pattern,
(2B) If N−r ≦ K, the K + r−N-th bit from the beginning of the r-bit range immediately after the continuous N-bit range in the second comparator And a comparator that compares the corresponding portion of the known bit pattern with the J bit portion starting from the K-th bit and the L + 1 bit to J bit portion of the known bit pattern. With,
Detecting reception of the serial data on condition that a match is detected,
Or
The specific period is a period after q + 1 period from the first period,
(1B) When K <N−r, the Kth bit from the beginning of the Nr bit range immediately before the continuous N bit range in the third comparator And a comparator for comparing the corresponding portion of the known bit pattern with the J bit portion starting from the K bit and the (L + 1) th bit of the known bit pattern With part,
(2A) When N−r ≦ K, the portion of the first comparator starting from the head of the K + r−N bits from the head of the continuous N-bit range and the known A comparator that performs a comparison with a corresponding portion of the bit pattern includes a J bit portion starting from the K + r-N bit and a L bit from the L + 1 bit to the J bit portion of the known bit pattern.
The receiving apparatus according to claim 2, wherein reception of the serial data is detected on condition that a match is detected. (1A) When K <N−r, the specific cycle is a cycle after q cycles from the first cycle of the parallel clock, and the specific bit is the head of the continuous N-bit range. To the K + rth bit from
(2A) When N−r ≦ K, the specific cycle is a cycle after q + 1 cycles from the first cycle of the parallel clock, and the specific bit is the head of the range of the consecutive N bits. To (K + r−N) th bit,
The receiving apparatus according to claim 1. A portion in which the comparison circuit starts with each bit in the range of the consecutive N bits of the bits constituting the plurality of parallel data stored in the first register and the one or more second registers. And N comparators for comparing the corresponding portion of the known bit pattern with
The detection circuit comprises:
(1A) When K <N−r, a portion of the N comparators beginning with the K + r-th bit from the head of the continuous N-bit range and the known bit pattern Comparing with a corresponding portion of the J bit portion starting from the K + r bit and the L + 1 bit to J bit portion of the known bit pattern,
(2A) If N−r ≦ K, a portion of the N comparators starting from the head of the K + r−N-th bit from the head of the continuous N-bit range and the known A comparator that performs a comparison with a corresponding portion of the bit pattern includes a J bit portion starting from the K + r-N bit and a L bit from the L + 1 bit to the J bit portion of the known bit pattern.
The receiving apparatus according to claim 4, wherein reception of the serial data is detected on condition that a match is detected.   6. The receiving apparatus according to claim 1, wherein M = I · L (I is an integer of 2 or more) and J = L.   The receiving device according to claim 1, wherein the comparison circuit detects a match by allowing a predetermined number of bits to be mismatched.

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