JP5796627B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5796627B2
JP5796627B2 JP2013272601A JP2013272601A JP5796627B2 JP 5796627 B2 JP5796627 B2 JP 5796627B2 JP 2013272601 A JP2013272601 A JP 2013272601A JP 2013272601 A JP2013272601 A JP 2013272601A JP 5796627 B2 JP5796627 B2 JP 5796627B2
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semiconductor device
metal layer
semiconductor element
melting point
solder
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JP2014060458A (en
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匠 井原
匠 井原
毛利　正美
正美 毛利
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Socionext Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

本発明は、半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

電子機器には様々な半導体装置が搭載される。その半導体装置はパッケージ基板上に半導体素子を搭載してなり、半導体素子で発生した熱は放熱板を伝って外部に逃がされる。   Various semiconductor devices are mounted on electronic devices. The semiconductor device includes a semiconductor element mounted on a package substrate, and heat generated in the semiconductor element is transferred to the outside through a heat sink.

放熱板での放熱効果を高めるには、半導体素子と放熱板とが熱的に良好に接続されているのが好ましい。そのため、ハンダのような熱伝導率の高い合金を介して半導体素子と放熱板とを接続し、半導体素子で発生した熱を放熱板に効率的に伝達する構造が提案されている。   In order to enhance the heat dissipation effect of the heat sink, it is preferable that the semiconductor element and the heat sink are thermally connected. For this reason, a structure has been proposed in which a semiconductor element and a heat sink are connected via an alloy having high thermal conductivity such as solder, and heat generated in the semiconductor element is efficiently transmitted to the heat sink.

そのような構造においては、単に放熱効果を高めるだけでなく、半導体装置の信頼性を向上させるのが好ましい。   In such a structure, it is preferable not only to improve the heat dissipation effect but also to improve the reliability of the semiconductor device.

特開２００７−１７３４１６号公報JP 2007-173416 A 特開平４−２４５６５２号公報Japanese Patent Laid-Open No. 4-245652

半導体装置とその製造方法において、半導体装置の信頼性を高めることを目的とする。   An object of the semiconductor device and the manufacturing method thereof is to improve the reliability of the semiconductor device.

以下の開示の一観点によれば、基板と、前記基板の上方に配設された半導体素子と、前記半導体素子の上方に配設された第１の金属層と、前記第１の金属層の上方に配設された第２の金属層と、前記第２の金属層の上方に配設された放熱部材と、前記第１の金属層と前記第２の金属層とを接続する、In及びAgを含む接続部材とを有し、前記接続部材は、前記第１の金属層の上方に配設され、第１の融点を有する第１の部材と、前記第１の部材の上方に配設され、前記第１の融点よりも高い第２の融点を有し、前記第１の部材よりも広い面積を有する第２の部材と、前記第２の部材の上方に配設され、前記第２の融点よりも低い第３の融点を有し、前記第２の部材よりも狭い面積を有する第３の部材とを有する半導体装置が提供される。 According to one aspect of the following disclosure, a substrate, a semiconductor element disposed above the substrate, a first metal layer disposed above the semiconductor element, and the first metal layer A second metal layer disposed above; a heat dissipating member disposed above the second metal layer; and connecting the first metal layer and the second metal layer to In and have a connection member comprising Ag, the connection member is disposed above the first metal layer, a first member having a first melting point, arranged above the first member A second member having a second melting point higher than the first melting point and having a larger area than the first member; and being disposed above the second member, a third melting point lower than the melting point of the third semiconductor device which have a and member is provided having a smaller area than the second member.

また、その開示の別の観点によれば、基板上に半導体素子を配設する工程と、前記半導体素子の上方に第１の金属層を配設する工程と、前記第1の金属層の上方にIn及びAgを含む接続部材を配設する工程と、放熱部材の一の面に第２の金属層を形成する工程と、前記接続部材の上方に前記第２の金属層が接するように前記放熱部材を加熱押圧しながら接続する工程と、前記放熱部材を押圧しながら、接続部材を加熱することにより、前記半導体素子と前記放熱部材を接続する工程とを有し、前記接続部材は、前記第１の金属層の上方に配設され、第１の融点を有する第１の部材と、前記第１の部材の上方に配設され、前記第１の融点よりも高い第２の融点を有し、前記第１の部材よりも広い面積を有する第２の部材と、前記第２の部材の上方に配設され、前記第２の融点よりも低い第３の融点を有し、前記第２の部材よりも狭い面積を有する第３の部材とを有する半導体装置の製造方法が提供される。 According to another aspect of the disclosure, a step of disposing a semiconductor element on a substrate, a step of disposing a first metal layer above the semiconductor element, and an upper portion of the first metal layer A step of disposing a connection member containing In and Ag, a step of forming a second metal layer on one surface of the heat dissipation member, and the second metal layer in contact with the connection member above the connection member. a step of connecting with heating presses the heat radiation member, while pressing the heat radiating member, by heating the connecting member, possess a step of connecting the heat radiating member and the semiconductor element, wherein the connecting member, the A first member disposed above the first metal layer and having a first melting point; and a first member disposed above the first member and having a second melting point higher than the first melting point. A second member having a larger area than the first member, and above the second member. It is set, a third melting point lower than the second melting point, a method of manufacturing a semiconductor device which have a third member having a smaller area than the second member.

図１は、調査に使用した半導体装置の断面図である。FIG. 1 is a cross-sectional view of the semiconductor device used for the investigation. 図２（ａ）〜（ｃ）は、調査に使用した半導体装置の製造途中の拡大断面図である。2A to 2C are enlarged cross-sectional views in the course of manufacturing the semiconductor device used for the investigation. 図３は、調査に使用した半導体装置が備えるパッケージ基板の顕微鏡像を基にして描いた断面図である。FIG. 3 is a cross-sectional view drawn on the basis of a microscopic image of a package substrate included in the semiconductor device used for the investigation. 図４は、調査に使用した半導体装置が備えるパッケージ基板の顕微鏡像を基にして描いた平面図である。FIG. 4 is a plan view drawn on the basis of a microscopic image of a package substrate included in the semiconductor device used for the investigation. 図５（ａ）、（ｂ）は、実験に使用したサンプルの断面図である。5A and 5B are cross-sectional views of samples used in the experiment. 図６（ａ）〜（ｃ）は、放熱板を取り外した実験サンプルの顕微鏡像を基にして描いた図である。6 (a) to 6 (c) are diagrams drawn on the basis of microscopic images of experimental samples with the heat sink removed. 図７は、接続部材にボイドが形成されることなく、加熱によって溶融した第１の部材と第３の部材が繋がった半導体装置の断面図である。FIG. 7 is a cross-sectional view of the semiconductor device in which the first member and the third member melted by heating are connected without forming voids in the connection member. 図８は、第２の部材が第１の部材と第３の部材によって覆われた半導体装置の顕微鏡像を基にして描いた断面図である。FIG. 8 is a cross-sectional view drawn on the basis of a microscopic image of a semiconductor device in which the second member is covered with the first member and the third member. 図９（ａ）は、第１の部材と第３の部材の厚さを薄くした半導体装置の断面図であり、図９（ｂ）は、接続部材の全体の大きさを小さくした半導体装置の断面図である。FIG. 9A is a cross-sectional view of a semiconductor device in which the thickness of the first member and the third member is reduced, and FIG. 9B is a diagram of the semiconductor device in which the overall size of the connection member is reduced. It is sectional drawing. 図１０は、単層構造の接続部材によって引き起こされる問題について説明するための断面図である。FIG. 10 is a cross-sectional view for explaining a problem caused by a connection member having a single-layer structure. 図１１（ａ）は、放熱板の下面の顕微鏡像を基にして描いた平面図であり、図１１（ｂ）は、放熱板とその周囲の顕微鏡像を基にして描いた断面図である。FIG. 11A is a plan view drawn on the basis of a microscopic image of the lower surface of the heat sink, and FIG. 11B is a cross-sectional view drawn on the basis of the heat sink and the surrounding microscopic image. . 図１２（ａ）〜（ｃ）は、接続部材にボイドが発生する原因について示す断面図である。FIGS. 12A to 12C are cross-sectional views illustrating the cause of voids generated in the connection member. 図１３（ａ）、（ｂ）は、第１実施形態に係る半導体装置の製造途中の断面図（その１）である。13A and 13B are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the first embodiment. 図１４（ａ）、（ｂ）は、第１実施形態に係る半導体装置の製造途中の断面図（その２）である。14A and 14B are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the first embodiment. 図１５（ａ）、（ｂ）は、第１実施形態に係る半導体装置の製造途中の断面図（その３）である。FIGS. 15A and 15B are cross-sectional views (part 3) in the course of manufacturing the semiconductor device according to the first embodiment. 図１６は、第１実施形態に係る半導体装置の製造途中の断面図（その４）である。FIG. 16 is a cross-sectional view (part 4) of the semiconductor device according to the first embodiment in the middle of manufacture. 図１７は、第１実施形態に係る半導体装置の製造途中の断面図（その５）である。FIG. 17 is a cross-sectional view (part 5) in the middle of manufacturing the semiconductor device according to the first embodiment. 図１８は、第１実施形態に係る半導体装置の製造途中の断面図（その６）である。FIG. 18 is a cross-sectional view (No. 6) of the semiconductor device according to the first embodiment in the middle of manufacture. 図１９は、第１実施形態に係る半導体装置の製造途中の断面図（その７）である。FIG. 19 is a sectional view (No. 7) in the middle of manufacturing the semiconductor device according to the first embodiment. 図２０は、第１実施形態で使用する接続部材の斜視図である。FIG. 20 is a perspective view of a connection member used in the first embodiment. 図２１は、第１実施形態に係る半導体装置の上面図である。FIG. 21 is a top view of the semiconductor device according to the first embodiment. 図２２は、第１実施形態に係る半導体装置によって奏される別の効果について説明するための断面図である。FIG. 22 is a cross-sectional view for explaining another effect produced by the semiconductor device according to the first embodiment. 図２３は、第１実施形態に係る半導体装置によって奏される他の効果について説明するための断面図である。FIG. 23 is a cross-sectional view for explaining another effect exhibited by the semiconductor device according to the first embodiment. 図２４（ａ）は、第２実施形態の第１例に係る接続部材の作製方法について説明するための上面図であり、図２４（ｂ）は図２４（ａ）のX2−X2線に沿う断面図である。FIG. 24A is a top view for explaining a manufacturing method of the connection member according to the first example of the second embodiment, and FIG. 24B is along the line X2-X2 in FIG. It is sectional drawing. 図１５は、第２実施形態の第１例によって作製された接続部材の斜視図である。FIG. 15 is a perspective view of a connection member manufactured according to the first example of the second embodiment. 図２６（ａ）は、第２実施形態の第１例に係る半導体装置の平面図であり、図２６（ｂ）は図２６（ａ）のX3−X3線に沿う断面図である。FIG. 26A is a plan view of the semiconductor device according to the first example of the second embodiment, and FIG. 26B is a cross-sectional view taken along the line X3-X3 in FIG. 図２７（ａ）は、第２実施形態の第２例に係る接続部材の作製方法について説明するための上面図であり、図２７（ｂ）は図２７（ａ）のX4−X4線に沿う断面図である。FIG. 27A is a top view for explaining a manufacturing method of the connection member according to the second example of the second embodiment, and FIG. 27B is along the line X4-X4 in FIG. It is sectional drawing. 図２８は、第２実施形態の第２例によって作製された接続部材の斜視図である。FIG. 28 is a perspective view of a connection member manufactured according to the second example of the second embodiment. 図２９（ａ）は、第２実施形態の第２例に係る半導体装置の平面図であり、図２９（ｂ）は図２９（ａ）のX5−X5線に沿う断面図である。FIG. 29A is a plan view of a semiconductor device according to a second example of the second embodiment, and FIG. 29B is a cross-sectional view taken along line X5-X5 in FIG. 図３０（ａ）は、第３実施形態に係る接続部材の作製方法について説明するための上面図であり、図３０（ｂ）は図３０（ａ）のX6−X6線に沿う断面図である。FIG. 30A is a top view for explaining a manufacturing method of the connection member according to the third embodiment, and FIG. 30B is a cross-sectional view taken along line X6-X6 in FIG. . 図３１（ａ）は、第３実施形態に係る接続部材の下側層の斜視図であり、図３１（ｂ）はその接続部材の斜視図である。FIG. 31A is a perspective view of the lower layer of the connection member according to the third embodiment, and FIG. 31B is a perspective view of the connection member. 図３２（ａ）は、第３実施形態に係る半導体装置の平面図であり、図３２（ｂ）は図３２（ａ）のX7−X7線に沿う断面図である。FIG. 32A is a plan view of the semiconductor device according to the third embodiment, and FIG. 32B is a cross-sectional view taken along line X7-X7 in FIG.

本実施形態の説明に先立ち、本願発明者が行った調査結果について説明する。   Prior to the description of the present embodiment, the results of an investigation conducted by the present inventor will be described.

図１は、調査に使用した半導体装置の断面図である。   FIG. 1 is a cross-sectional view of the semiconductor device used for the investigation.

この半導体装置１は、BGA(Ball Grid Array)タイプの半導体装置であって、パッケージ基板２と半導体素子１０とを備える。   The semiconductor device 1 is a BGA (Ball Grid Array) type semiconductor device, and includes a package substrate 2 and a semiconductor element 10.

パッケージ基板２の一方の主面２ａ上には第１の電極パッド３が設けられ、この第１の電極パッド３の上に外部接続端子５として機能するハンダバンプが接合される。   A first electrode pad 3 is provided on one main surface 2 a of the package substrate 2, and a solder bump functioning as an external connection terminal 5 is bonded onto the first electrode pad 3.

一方、パッケージ基板２の他方の主面２ｂ上には第２の電極パッド４が設けられる。その第２の電極パッド４は、ハンダバンプ７を介して半導体素子１０の電極８と電気的かつ機械的に接続される。そして、半導体素子１０とパッケージ基板２との接続信頼性を高めるために、これらの間の隙間にはアンダーフィル樹脂１１が充填される。   On the other hand, a second electrode pad 4 is provided on the other main surface 2 b of the package substrate 2. The second electrode pad 4 is electrically and mechanically connected to the electrode 8 of the semiconductor element 10 via the solder bump 7. In order to increase the connection reliability between the semiconductor element 10 and the package substrate 2, a gap between them is filled with an underfill resin 11.

更に、パッケージ基板２の他方の主面２ｂには、電子部品１４を実装するための第３の電極パッド６が設けられる。電子部品１４は、例えばチップコンデンサであって、第３の電極パッド６にハンダ付けされる。   Furthermore, a third electrode pad 6 for mounting the electronic component 14 is provided on the other main surface 2 b of the package substrate 2. The electronic component 14 is a chip capacitor, for example, and is soldered to the third electrode pad 6.

その電子部品１４は、半導体素子１０と共に、金属製の放熱板１８で覆われる。放熱板１８は、半導体素子１０で発生した熱を外部に逃がす放熱部材としての役割を担うものであり、接着剤１９によってパッケージ基板２に接着される。   The electronic component 14 is covered with a metal heat sink 18 together with the semiconductor element 10. The heat radiating plate 18 serves as a heat radiating member that releases heat generated in the semiconductor element 10 to the outside, and is bonded to the package substrate 2 by an adhesive 19.

ここで、放熱板１８と半導体素子１０との間に隙間があると、その隙間における空気の断熱作用によって半導体素子１０の熱が放熱板１８に伝わり難くなり、放熱板１８による放熱効果が低下する。   Here, if there is a gap between the heat radiating plate 18 and the semiconductor element 10, the heat of the semiconductor element 10 becomes difficult to be transmitted to the heat radiating plate 18 due to the heat insulating action of air in the gap, and the heat radiating effect by the heat radiating plate 18 is reduced. .

そこで、この半導体装置１では、半導体素子１０の上面と放熱板１８の下面とを金属製の接続部材１６で接続することにより、半導体素子１０で発生した熱を速やかに放熱板１８に伝達させ、放熱板１８による放熱効果を高めている。   Therefore, in this semiconductor device 1, by connecting the upper surface of the semiconductor element 10 and the lower surface of the heat radiating plate 18 with a metal connecting member 16, heat generated in the semiconductor element 10 is quickly transmitted to the heat radiating plate 18, The heat dissipation effect by the heat sink 18 is enhanced.

但し、このように接続部材１６により放熱板１８と半導体素子１０とを直接接続すると、放熱板１８が熱膨張したときに、放熱板１８と半導体素子１０との熱膨張率差が原因で半導体素子１０に応力が加わることになる。その応力は、半導体素子１０にクラックを生じさせたり、半導体素子１０とパッケージ基板２との接続信頼性を低下させる原因となる。   However, when the heat radiating plate 18 and the semiconductor element 10 are directly connected by the connecting member 16 in this way, when the heat radiating plate 18 is thermally expanded, the difference in the thermal expansion coefficient between the heat radiating plate 18 and the semiconductor element 10 causes the semiconductor element. 10 is stressed. The stress causes a crack in the semiconductor element 10 and decreases the connection reliability between the semiconductor element 10 and the package substrate 2.

そのため、本例では、接続部材１６を第１〜第３の部材２１〜２３の積層構造にすると共に、第２の部材２２として第１、第３の部材２３よりもヤング率が小さく変形し易い金属材料を使用して、放熱板１８から半導体素子１０に加わる応力を緩和する。そのような第２の部材２２の材料としては、例えば高融点ハンダがある。   Therefore, in this example, the connection member 16 has a laminated structure of the first to third members 21 to 23, and the Young member has a smaller Young's modulus than the first and third members 23 and is easily deformed as the second member 22. A metal material is used to relieve stress applied to the semiconductor element 10 from the heat sink 18. Examples of the material of the second member 22 include high melting point solder.

また、第１の部材２１と第３の部材２３は、上記のように応力緩和の役割を担う第２の部材２２を半導体素子２１や放熱板１８に接合するのに使用され、その材料としては低融点ハンダが使用される。   The first member 21 and the third member 23 are used to join the second member 22, which plays a role of stress relaxation as described above, to the semiconductor element 21 and the heat radiating plate 18. Low melting point solder is used.

このように低融点ハンダを使用することで、接続部材１６を加熱して放熱板１８と半導体素子１０に接合するときに、高融点ハンダを含む第２の部材２２が溶融するのを防ぎながら、第１及び第３の部材２１、２３のみを選択的に溶融することができる。   By using the low melting point solder as described above, the second member 22 including the high melting point solder is prevented from melting when the connection member 16 is heated and joined to the heat sink 18 and the semiconductor element 10. Only the first and third members 21 and 23 can be selectively melted.

以上のように、接続部材１６は、放熱板１８に半導体素子２１の熱を効率的に伝える役割に加え、放熱板１８から半導体素子１０に加わる応力を緩和する役割も担う。   As described above, the connection member 16 plays a role of relieving the stress applied to the semiconductor element 10 from the heat sink 18 in addition to the role of efficiently transferring the heat of the semiconductor element 21 to the heat sink 18.

しかしながら、接続部材１６は、半導体装置１の製造時に以下のような問題を引き起こすことが調査によって明らかとなった。   However, the investigation has revealed that the connection member 16 causes the following problems when the semiconductor device 1 is manufactured.

図２（ａ）〜（ｃ）は、上記の半導体装置１の製造途中の拡大断面図である。   2A to 2C are enlarged cross-sectional views in the course of manufacturing the semiconductor device 1 described above.

半導体装置１を製造するには、図２（ａ）に示すように、半導体素子１０と放熱板１８との間に接続部材１６を配し、押圧力Fにより接続部材１６に放熱板１８を押し付けながら接続部材１６を加熱する。   In order to manufacture the semiconductor device 1, as shown in FIG. 2A, the connection member 16 is disposed between the semiconductor element 10 and the heat dissipation plate 18, and the heat dissipation plate 18 is pressed against the connection member 16 by the pressing force F. Then, the connecting member 16 is heated.

その加熱により、低融点ハンダを含む第１及び第３の部材２１、２３が溶融し、半導体素子１０と放熱板１８の各々の表面に各接続部材２１、２３が濡れ広がる。なお、本工程での加熱温度は高融点ハンダを含む第２の部材２２の融点よりも低くいので、本工程では第２の部材２２は溶融しない。   By the heating, the first and third members 21, 23 including the low melting point solder are melted, and the connection members 21, 23 are spread on the surfaces of the semiconductor element 10 and the heat radiating plate 18. Since the heating temperature in this step is lower than the melting point of the second member 22 including the high melting point solder, the second member 22 is not melted in this step.

また、各接続部材２１、２３の濡れ性を良好にするために、図２（ａ）のように、半導体素子１０の上面にAuメタライズ層２５を形成し、放熱板１８の下面にメッキ膜２６を形成してもよい。そのメッキ膜２６は、例えば、放熱板１８上にNiメッキ膜５１とAuメッキ膜５０をこの順に形成してなる。   Further, in order to improve the wettability of each of the connection members 21 and 23, as shown in FIG. 2A, an Au metallized layer 25 is formed on the upper surface of the semiconductor element 10, and a plating film 26 is formed on the lower surface of the radiator plate 18. May be formed. The plated film 26 is formed, for example, by forming a Ni plated film 51 and an Au plated film 50 in this order on the heat sink 18.

このように各接続部材２１、２３が濡れ広がると、図２（ｂ）に示すように、第２の部材２２の側面２２ａからこれらの接続部材２１、２３がはみ出すようになる。そして、最終的には、側面２２ａの横の空気を巻き込みながら各接続部材２１、２３が接続され、ボイド２９が発生する。   When the connection members 21 and 23 spread out in this manner, the connection members 21 and 23 protrude from the side surface 22a of the second member 22 as shown in FIG. And finally, each connection member 21 and 23 is connected, entraining the air of the side 22a, and the void 29 is generated.

図２（ｃ）に示すように、そのボイド２９は半導体装置１の製造途中に破裂し、それによりハンダ粒３０が飛散する。ボイド２９が破裂する原因としては様々なものが考えられる。   As shown in FIG. 2C, the void 29 is ruptured during the manufacturing of the semiconductor device 1, and the solder particles 30 are scattered. There are various possible causes for the void 29 to burst.

例えば、各接続部材２１、２３が溶融している状態でこれらの部材に加わる押圧力Fが原因でボイド２９が破裂すると考えられる。また、各部材２１、２３が冷えて固化した後に行われる熱工程によりこれらの部材２１、２３に熱が加わり、その熱によってボイド２９内の空気が熱膨張してボイド２９の破裂が発生するとも考えられる。そのような熱工程としては、例えば、半導体装置１をマザーボードに搭載するために行われる外部接続端子５（図１参照）のリフロー工程や、マザーボードに電子部品を搭載する工程がある。   For example, it is considered that the void 29 is ruptured due to the pressing force F applied to these connecting members 21 and 23 in a melted state. In addition, heat is applied to the members 21 and 23 by the heat process performed after the members 21 and 23 are cooled and solidified, and the air in the void 29 is thermally expanded by the heat, and the void 29 is ruptured. Conceivable. Examples of such a thermal process include a reflow process of the external connection terminal 5 (see FIG. 1) performed for mounting the semiconductor device 1 on the motherboard, and a process of mounting electronic components on the motherboard.

図３は、このようにボイド２９が破裂してハンダ粒３０が飛散した状態における半導体装置の顕微鏡像を基にして描いた断面図である。   FIG. 3 is a cross-sectional view drawn on the basis of a microscopic image of the semiconductor device in a state where the void 29 is ruptured and the solder particles 30 are scattered.

図３に示されるように、ボイド２９の破裂によって飛散したハンダ粒３０がアンダーフィル樹脂１１上に点在している。   As shown in FIG. 3, solder particles 30 scattered by the rupture of the voids 29 are scattered on the underfill resin 11.

図４は、ハンダ粒３０が飛散した状態のパッケージ基板２の顕微鏡像を基にして描いた上面図である。   FIG. 4 is a top view drawn based on a microscopic image of the package substrate 2 in a state where the solder grains 30 are scattered.

図４に示されるように、パッケージ基板２の表面上には、飛散したハンダ粒３０が点在している。   As shown in FIG. 4, scattered solder grains 30 are scattered on the surface of the package substrate 2.

そのハンダ粒３０が電子部品１４の端子１４ａ等に付着すると、隣接する端子１４ａ同士がハンダ粒３０によって電気的にショートする等の不具合が発生してし、ひいては半導体装置の信頼性を低下させてしまう。   If the solder particles 30 adhere to the terminals 14a and the like of the electronic component 14, problems such as electrical short-circuiting between the adjacent terminals 14a due to the solder particles 30 occur, and as a result, the reliability of the semiconductor device is reduced. End up.

本願発明者は、そのハンダ粒３０が、実際にボイド２９の破裂によって発生することを確かめるため、次のような実験を行った。   The inventor of the present application conducted the following experiment in order to confirm that the solder grains 30 are actually generated by the burst of the voids 29.

その実験では、断面構造が図５（ａ）のような実験サンプルS1を用意した。   In the experiment, an experimental sample S1 having a sectional structure as shown in FIG.

実験サンプルS1においては、第１の部材２１と第３の部材２３の各々を、第２の部材２２の側面２２ａから張り出すように設けた。このような構造によれば、加熱により溶融した第１の部材２１と第３の部材２３が第２の部材２２の横で空気を取り込み易くなり、上記したボイド２９が形成され易くなると考えられる。   In the experimental sample S1, each of the first member 21 and the third member 23 is provided so as to protrude from the side surface 22a of the second member 22. According to such a structure, it is considered that the first member 21 and the third member 23 melted by heating can easily take in air beside the second member 22 and the above-described void 29 is easily formed.

また、この実験では、比較のために、断面構造が図５（ｂ）のようなレファレンスサンプルS2も用意した。   In this experiment, a reference sample S2 having a sectional structure as shown in FIG. 5B was also prepared for comparison.

リファレンスサンプルS2においては、第１〜第３の部材２１〜２３の各々の側面を揃えることにより、実験サンプルS1と比較してボイド２９が形成され難い構造とした。   In the reference sample S2, the side surfaces of the first to third members 21 to 23 are aligned so that the void 29 is less likely to be formed compared to the experimental sample S1.

上記のサンプルS1、S2をそれぞれ６個作製し、その各々において第１の部材２１と第３の部材２３を加熱して溶融することにより、接続部材１６により半導体素子１０と放熱板１８とを接続した。   Six samples S1 and S2 are prepared, and the first member 21 and the third member 23 are heated and melted in each of them, thereby connecting the semiconductor element 10 and the heat sink 18 by the connecting member 16. did.

その後、各サンプルS1、S2の放熱板１８を取り外し、パッケージ基板２上に飛散しているハンダ粒３０の数を計数した。   Then, the heat sink 18 of each sample S1 and S2 was removed, and the number of solder grains 30 scattered on the package substrate 2 was counted.

その結果、レファレンスサンプルS2では、６個の全てにおいてハンダ粒３０の発生はなかった。   As a result, in the reference sample S2, no solder particles 30 were generated in all six samples.

一方、実験サンプルS1においては、６個のうち５個においてハンダ粒３０の発生が確認され、ハンダ粒３０の発生確率は８３％（＝１００×５／６）であった。   On the other hand, in the experimental sample S1, generation of solder grains 30 was confirmed in 5 out of 6 pieces, and the generation probability of the solder grains 30 was 83% (= 100 × 5/6).

このように、ボイド２９が形成され易い実験サンプルS1においてハンダ粒３０が多く発生したことから、ハンダ粒３０の発生原因がボイド２９の破裂にあることが確認された。   Thus, since many solder particles 30 were generated in the experimental sample S1 in which the voids 29 were easily formed, it was confirmed that the cause of the generation of the solder particles 30 was the burst of the voids 29.

なお、図６（ａ）〜（ｃ）は、放熱板１８を取り外した実験サンプルS1の顕微鏡像を基にして描いた図である。   6A to 6C are diagrams drawn based on the microscopic image of the experimental sample S1 from which the heat radiating plate 18 is removed.

このうち、図６（ａ）は側面図であり、図６（ｂ）は断面図であり、図６（ｃ）は上面図である。   6A is a side view, FIG. 6B is a cross-sectional view, and FIG. 6C is a top view.

図６（ａ）、（ｂ）に示すように、実験サンプルS1の接続部材１６にはボイド２９が形成されている。そして、図６（ｃ）に示すように、実験サンプルS1のパッケージ基板２上にはハンダ粒３０が飛散している。   As shown in FIGS. 6A and 6B, a void 29 is formed in the connection member 16 of the experimental sample S1. Then, as shown in FIG. 6C, solder particles 30 are scattered on the package substrate 2 of the experimental sample S1.

このように、図１の構造の接続部材１６では、ボイド２９が形成されるとハンダ粒３０が飛散するという問題が発生するが、ボイド２９が発生しなくても次のような不具合が生じる。   As described above, in the connection member 16 having the structure shown in FIG. 1, when the void 29 is formed, the problem that the solder particles 30 are scattered occurs. However, even if the void 29 is not generated, the following problem occurs.

図７は、ボイド２９が形成されることなく、加熱によって溶融した第１の部材２１と第３の部材２３が繋がった半導体装置の断面図である。   FIG. 7 is a cross-sectional view of the semiconductor device in which the first member 21 and the third member 23 melted by heating are connected without forming the void 29.

この場合、第２の部材２２は、その表面の全ての部分が第１の部材２１と第３の部材２３によって覆われることになる。   In this case, the entire surface of the second member 22 is covered with the first member 21 and the third member 23.

図８は、このように第２の部材２２が第１の部材２１と第３の部材２３によって覆われた場合の顕微鏡を基にして描いた断面図である。   FIG. 8 is a cross-sectional view drawn on the basis of a microscope when the second member 22 is covered with the first member 21 and the third member 23 as described above.

しかしながら、第２の部材２２は、放熱板１８から半導体素子１０に印加される応力を自身が変形することにより吸収する役割を担うものであるから、その周囲が接続部材２１、２３で囲まれると第２の部材２２の変形が阻害されてしまう。そのため、第２の部材２２による応力緩和の効果が低減し、半導体素子１０とパッケージ基板２との接続信頼性が低下するという不具合が発生してしまう。   However, since the second member 22 plays a role of absorbing the stress applied to the semiconductor element 10 from the heat radiating plate 18 by deformation of the second member 22, the second member 22 is surrounded by the connection members 21 and 23. The deformation of the second member 22 is hindered. Therefore, the effect of stress relaxation by the second member 22 is reduced, resulting in a problem that connection reliability between the semiconductor element 10 and the package substrate 2 is lowered.

このように各接続部材２１、２３同士が繋がるのを防止するために、次のような構造も考えられる。   In order to prevent the connection members 21 and 23 from being connected to each other in this way, the following structure is also conceivable.

図９（ａ）は、第１の部材２１と第３の部材２３の厚さを薄くすることにより、第２の部材２２の横にはみ出る各部材２１、２３の量を低減することを意図した断面構造である。   FIG. 9A is intended to reduce the amount of each of the members 21 and 23 protruding from the side of the second member 22 by reducing the thicknesses of the first member 21 and the third member 23. It is a cross-sectional structure.

但し、この構造では、各部材２１、２３の量が少ないため、図９（ａ）のように半導体素子１０や放熱板１８が反った場合に、その反りに対して各部材２１、２３が追従し難くなる。そのため、接続部材１６と放熱板１８との間や、接続部材１６と半導体素子１０との間に隙間ができ、半導体素子１０で発生した熱を効率的に放熱板１８に伝達するのが難しくなる。   However, in this structure, since the amount of each member 21 and 23 is small, when the semiconductor element 10 and the heat sink 18 warp as shown in FIG. 9A, each member 21 and 23 follows the warp. It becomes difficult to do. Therefore, a gap is formed between the connection member 16 and the heat radiating plate 18 or between the connection member 16 and the semiconductor element 10, and it becomes difficult to efficiently transmit the heat generated in the semiconductor element 10 to the heat radiating plate 18. .

図９（ｂ）は、図２（ａ）におけるよりも接続部材１６の全体の大きさを小さくすることにより、第２の部材２２の横に押し出される接続部材２１、２３の量を低減することを意図した断面構造である。   9B reduces the amount of the connecting members 21 and 23 that are pushed out to the side of the second member 22 by reducing the overall size of the connecting member 16 than in FIG. 2A. This is a cross-sectional structure intended for.

しかしながら、この構造では、接続部材１６を小さくした分だけ接続部材１６の横にAuメタライズ層２５が露出するようになり、溶融した第１の部材２１がそのAuメタライズ層２５上を濡れ広がり易くなる。その結果、かえって第１の部材２１が第２の部材２２の横に押し出されるようになるので、第１の部材２１と第３の部材２３との接続が助長され、ボイド２９が発生する危険性が高くなる。   However, in this structure, the Au metallized layer 25 is exposed to the side of the connecting member 16 as much as the connecting member 16 is reduced, and the melted first member 21 is easily spread over the Au metallized layer 25. . As a result, since the first member 21 is pushed out to the side of the second member 22, the connection between the first member 21 and the third member 23 is promoted, and there is a risk that the void 29 is generated. Becomes higher.

また、ボイド２９の発生を抑制するため、上記のように接続部材１６を三層構造にするのではなく単層構造とすることも考えられる。   Further, in order to suppress the generation of the voids 29, it is conceivable that the connecting member 16 has a single layer structure instead of a three layer structure as described above.

図１０は、単層構造の接続部材１６によって引き起こされる問題について説明するための断面図である。   FIG. 10 is a cross-sectional view for explaining a problem caused by the connection member 16 having a single-layer structure.

図１０に示すように、接続部材１６を単層構造とすると、加熱によって溶融した接続部材１６がAuメッキ膜５０を伝って横方向に流れ出し、最悪の場合には電子部品１４と接触するおそれがある。こうなると、電子部品１４と金属製の放熱板１８とが電気的にショートしてしまい、半導体装置１の信頼性が低下する。   As shown in FIG. 10, when the connecting member 16 has a single layer structure, the connecting member 16 melted by heating flows laterally along the Au plating film 50, and in the worst case, the connecting member 16 may come into contact with the electronic component 14. is there. In this case, the electronic component 14 and the metal heat sink 18 are electrically short-circuited, and the reliability of the semiconductor device 1 is reduced.

図１１（ａ）は、単層構造の接続部材１６によって引き起こされる別の問題について説明するための図であって、放熱板１８の下面の顕微鏡像を基にして描いた平面図である。   FIG. 11A is a diagram for explaining another problem caused by the connection member 16 having a single-layer structure, and is a plan view drawn based on a microscopic image of the lower surface of the heat radiating plate 18.

図１１（ａ）に示されるように、加熱により接続部材１６を溶融した後に、放熱板１８の下面のメッキ膜２６に膨れ２６ａが形成されることがある。膨れ２６ａは、放熱板１８を作製した際に放熱板１８の内部に取り込まれた水分が、接続部材１６を溶融するときの熱によって膨張し、それが放熱板１８とNiメッキ膜５１との間に溜まることで発生すると考えられる。   As shown in FIG. 11A, after the connection member 16 is melted by heating, a bulge 26a may be formed on the plating film 26 on the lower surface of the heat sink 18 in some cases. The swelling 26 a expands due to the heat generated when the heat sink 18 melts the connection member 16 when the heat sink 18 is manufactured, and this expands between the heat sink 18 and the Ni plating film 51. It is thought that it occurs by accumulating in

図１１（ｂ）は、膨れ２６ａが発生したときの放熱板１８とその周囲の顕微鏡像を基にして描いた断面図である。なお、メッキ膜２６は、膜厚が薄いため、図１１（ｂ）では現れていない。   FIG. 11B is a cross-sectional view drawn on the basis of the heat sink 18 and the surrounding microscopic image when the swelling 26a occurs. Note that the plated film 26 does not appear in FIG.

図１１（ｂ）に示されるように、メッキ膜２６に膨れ２６ａがあると、それが原因で接続部材１６にボイド２９が発生する。   As shown in FIG. 11B, when the swell 26a is present in the plating film 26, a void 29 is generated in the connection member 16 due to the swelling 26a.

図１２（ａ）〜（ｃ）は、このボイド２９の発生原因を示す断面図である。   12A to 12C are cross-sectional views showing the cause of the void 29.

図１２（ａ）に示すように、加熱により接続部材１６を溶融する前においては、膨れ２６ａはNiメッキ膜５１と放熱板１８との界面に留まっている。   As shown in FIG. 12A, the bulge 26 a remains at the interface between the Ni plating film 51 and the heat radiating plate 18 before the connection member 16 is melted by heating.

そして、図１２（ｂ）に示すように、接続部材１６を加熱して溶融すると共に、接続部材１６に向けて放熱板１８を押圧すると、その押圧力によってメッキ膜２６が破れる。その結果、膨れ２６ａ内の空気が溶融状態の接続部材１６に移動し、接続部材１６にボイド２９が発生する。   Then, as shown in FIG. 12B, when the connecting member 16 is heated and melted, and when the heat radiating plate 18 is pressed toward the connecting member 16, the plating film 26 is broken by the pressing force. As a result, the air in the bulge 26 a moves to the molten connection member 16, and a void 29 is generated in the connection member 16.

図１２（ｃ）に示すように、そのボイド２９は、既述のようにハンダ粒３０が飛散する原因となる。   As shown in FIG. 12C, the voids 29 cause the solder particles 30 to scatter as described above.

このように、単層の接続部材１６でも、ボイド２９の発生を完全に抑制するのは困難である。   Thus, even with the single-layer connecting member 16, it is difficult to completely suppress the generation of the voids 29.

本願発明者は、このような知見に鑑み、以下に説明するような各実施形態に想到した。   In view of such knowledge, the inventor of the present application has come up with embodiments as described below.

（第１実施形態）
図１３〜図１９は、本実施形態に係る半導体装置の製造途中の断面図である。 (First embodiment)
13 to 19 are cross-sectional views of the semiconductor device according to the present embodiment during manufacture.

以下では、半導体装置としてBGA型の半導体装置を製造する。   In the following, a BGA type semiconductor device is manufactured as a semiconductor device.

この半導体装置を製造するには、まず、図１３（ａ）に示すように、ガラスエポキシ樹脂等の絶縁性材料を主にしてなるパッケージ基板２を用意する。   In order to manufacture this semiconductor device, first, as shown in FIG. 13A, a package substrate 2 mainly comprising an insulating material such as a glass epoxy resin is prepared.

そのパッケージ基板２の一方の主面２ａ上には第１の電極パッド３が複数設けられ、他方の面２ｂ上には第２の電極パッド４と第３の電極パッド６が複数設けられる。これらの電極３、４、６は、例えば、銅メッキ膜をパターニングして形成される。   A plurality of first electrode pads 3 are provided on one main surface 2a of the package substrate 2, and a plurality of second electrode pads 4 and a plurality of third electrode pads 6 are provided on the other surface 2b. These electrodes 3, 4, and 6 are formed by patterning a copper plating film, for example.

次いで、図１３（ｂ）に示すように、第３の電極パッド６上に印刷法によりハンダペースト９を印刷する。   Next, as shown in FIG. 13B, a solder paste 9 is printed on the third electrode pad 6 by a printing method.

そして、図１４（ａ）に示すように、ハンダペースト９の上に電子部品１４としてチップコンデンサを載せ、この状態でハンダペースト９をリフローすることにより、第３の電極パッド６と電子部品１４とを電気的かつ機械的に接続する。   14A, a chip capacitor is placed on the solder paste 9 as the electronic component 14, and the solder paste 9 is reflowed in this state, whereby the third electrode pad 6, the electronic component 14, Are electrically and mechanically connected.

続いて、図１４（ｂ）に示すように、電極８上にハンダバンプ７が接合された半導体素子１０を用意し、そのハンダバンプ７をリフローすることにより、半導体素子１０と第２の電極パッド４とを電気的かつ機械的に接続する。   Subsequently, as shown in FIG. 14B, a semiconductor element 10 having a solder bump 7 bonded on the electrode 8 is prepared, and the solder bump 7 is reflowed, whereby the semiconductor element 10, the second electrode pad 4, and the like. Are electrically and mechanically connected.

なお、その半導体素子１０の上面１０ｂ上には、後述の接続部材の濡れ性を良好にするためのAuメタライズ層２５が０．２１μm程度の厚さに予め形成されている。   Note that an Au metallized layer 25 is formed in advance on the upper surface 10b of the semiconductor element 10 to a thickness of about 0.21 μm for improving the wettability of a connecting member described later.

その後、図１５（ａ）に示すように、パッケージ基板２と半導体素子１０との熱膨張量の違いに起因してこれらの接続信頼性が低下するのを防止するため、これらの間にディスペンサ３３を利用して熱硬化性のアンダーフィル樹脂１１を充填する。   Thereafter, as shown in FIG. 15A, in order to prevent the connection reliability from deteriorating due to the difference in thermal expansion between the package substrate 2 and the semiconductor element 10, the dispenser 33 is interposed between them. Is used to fill the thermosetting underfill resin 11.

そして、図１５（ｂ）に示すように、半導体素子１０の下面全体にアンダーフィル１１を充填した後、加熱によりアンダーフィル樹脂１１を熱硬化させる。   And as shown in FIG.15 (b), after filling the undersurface 11 in the whole lower surface of the semiconductor element 10, the underfill resin 11 is thermoset by heating.

次に、図１６に示す工程について説明する。   Next, the process shown in FIG. 16 will be described.

まず、第１〜第３の部材２１〜２３を積層してなる接続部材１６と放熱板１８とを用意する。このうち、放熱板１８は、半導体素子１０で発生した熱を外部に放熱する放熱部材として機能するものであって、半導体素子１０と接続部材１６とを収容するキャビティ１８ｂを備える。   First, the connection member 16 and the heat sink 18 formed by laminating the first to third members 21 to 23 are prepared. Among these, the heat radiating plate 18 functions as a heat radiating member that radiates heat generated in the semiconductor element 10 to the outside, and includes a cavity 18 b that accommodates the semiconductor element 10 and the connection member 16.

一方、図２０は接続部材１６の斜視図である。   On the other hand, FIG. 20 is a perspective view of the connecting member 16.

図２０に示すように、接続部材２１〜２３の各々は概略矩形の平面形状を有する。   As shown in FIG. 20, each of the connection members 21 to 23 has a substantially rectangular planar shape.

接続部材２１〜２３のうち、第１の部材２１は低融点ハンダペレットであって、その厚さは約０．０８μmmである。   Of the connecting members 21 to 23, the first member 21 is a low melting point solder pellet and has a thickness of about 0.08 μm.

また、第２の部材２２は、第１の部材２１の上面に接して設けられる。そして、第２の部材２２の上面２２ｙは、第１の部材２１の上面２１ｙ（図１６参照）と半導体素子１０の上面１０ｂの各々よりも広い面積を有する。   The second member 22 is provided in contact with the upper surface of the first member 21. The upper surface 22 y of the second member 22 has a larger area than each of the upper surface 21 y (see FIG. 16) of the first member 21 and the upper surface 10 b of the semiconductor element 10.

第２の部材２２の材料は特に限定されない。本実施形態では、第２の部材２２として厚さが約０．１μmの高融点ハンダペレットを使用する。   The material of the second member 22 is not particularly limited. In the present embodiment, a high melting point solder pellet having a thickness of about 0.1 μm is used as the second member 22.

一方、第３の部材２３は、例えば厚さが約０．０８μmの低融点ハンダペレットである。そして、第３の部材２３の上面２３ｙは、第２の部材２２の上面２２ｙよりも狭い面積を有する。   On the other hand, the third member 23 is, for example, a low melting point solder pellet having a thickness of about 0.08 μm. The upper surface 23 y of the third member 23 has a smaller area than the upper surface 22 y of the second member 22.

各接続部材２１〜２３の具体的なサイズは特に限定されないが、第１の部材２１と第３の部材２３は一辺の長さL1が約２０mmの正方形であって、半導体素子１０の平面サイズにほぼ等しい。また、第２の部材２２は、一辺の長さL2が約２４mmの正方形であって、その平面サイズは半導体素子１０よりも大きい。   Although the specific size of each connection member 21-23 is not specifically limited, The 1st member 21 and the 3rd member 23 are the square whose length L1 of one side is about 20 mm, Comprising: It is the planar size of the semiconductor element 10. Almost equal. The second member 22 is a square having a side length L2 of about 24 mm, and its planar size is larger than that of the semiconductor element 10.

なお、本工程の時点では、ペレット状の各部材２１〜２３は互いに固着されておらず、それらが自重によって積み重なった状態となっている。   At the time of this step, the pellet-shaped members 21 to 23 are not fixed to each other, and are in a state of being stacked by their own weight.

次の表１は、第２の部材２２として使用し得る高融点ハンダと、第１及び第３の部材２１、２３として使用し得る低融点ハンダの各々の物性を示すものである。   Table 1 below shows the physical properties of the high melting point solder that can be used as the second member 22 and the low melting point solder that can be used as the first and third members 21 and 23.

Figure 0005796627
Figure 0005796627

表１に示すように、第２の部材２２の材料である高融点ハンダ（Sn-95Pb）は、第１及び第３の部材２１、２３の材料である低融点ハンダ（Sn-37Pb）の融点（１８３℃）よりも高い融点（３００℃）を有すると共に、当該低融点ハンダよりも小さなヤング率を有する。   As shown in Table 1, the high melting point solder (Sn-95Pb) that is the material of the second member 22 is the melting point of the low melting point solder (Sn-37Pb) that is the material of the first and third members 21 and 23. It has a melting point (300 ° C.) higher than (183 ° C.) and a Young's modulus smaller than that of the low melting point solder.

このように第２の部材２２としてヤング率が小さな材料を使用する場合は、第２の部材は外部の応力によって容易に変形するようになる。そのため、この場合は、第２の部材２２は放熱板１８と半導体素子１０との熱膨張率との差が原因で半導体素子１０に加わる応力を緩和する機能を有する。   As described above, when a material having a small Young's modulus is used as the second member 22, the second member is easily deformed by an external stress. Therefore, in this case, the second member 22 has a function of relieving the stress applied to the semiconductor element 10 due to the difference between the thermal expansion coefficients of the heat sink 18 and the semiconductor element 10.

なお、表１のような鉛含有ハンダに代えて鉛フリーハンダを使用してもよい。次の表２〜表４は、各部材２１〜２３の材料として使用し得る鉛非含有の材料の例である。   Note that lead-free solder may be used instead of lead-containing solder as shown in Table 1. The following Tables 2 to 4 are examples of lead-free materials that can be used as materials for the members 21 to 23.

Figure 0005796627
Figure 0005796627

Figure 0005796627
Figure 0005796627

Figure 0005796627
Figure 0005796627

一方、図１６の放熱板１８は例えばCu等の金属を含み、その下面１８ａにはメッキ膜２６が形成される。そのメッキ膜２６は、例えば、厚さが約４μmのNiメッキ膜５１と厚さが約０．１μmのAuメッキ膜５０とをこの順に形成してなる。   On the other hand, the heat radiating plate 18 in FIG. 16 includes a metal such as Cu, and a plating film 26 is formed on the lower surface 18a thereof. The plating film 26 is formed, for example, by forming a Ni plating film 51 having a thickness of about 4 μm and an Au plating film 50 having a thickness of about 0.1 μm in this order.

更に、放熱板１８の縁において、後でパッケージ基板２と当接する部分には、接着剤１９が設けられる。   Further, an adhesive 19 is provided on a portion of the edge of the heat radiating plate 18 that will be in contact with the package substrate 2 later.

次いで、図１７に示すように、半導体素子１０、接続部材１６、及び放熱板１８の各々の位置合わせを行った後、これらを積層する。   Next, as shown in FIG. 17, the semiconductor element 10, the connection member 16, and the radiator plate 18 are aligned and then stacked.

このとき、接続部材１６の各部材２１〜２３はその各々が自重で積み重なった状態であるため、接続部材１６の上に放熱板１８を載せるときには各部材２１〜２３が位置ずれをしないように注意を払うのが好ましい。   At this time, since the members 21 to 23 of the connecting member 16 are stacked with their own weight, care should be taken that the members 21 to 23 are not displaced when the heat sink 18 is placed on the connecting member 16. It is preferable to pay.

そして、図１８に示すように、パッケージ基板２に向けて放熱板１８を押圧しながら、第１の部材２１と第３の部材２３を加熱して溶融することにより、接続部材１６を介して放熱板１８と半導体素子１０とを接続する。   Then, as shown in FIG. 18, the first member 21 and the third member 23 are heated and melted while pressing the heat radiating plate 18 toward the package substrate 2, thereby radiating heat through the connection member 16. The plate 18 and the semiconductor element 10 are connected.

このとき、半導体素子１０の上面にAuメタライズ層２５を形成し、放熱板１８の下面にAuメッキ膜５０を予め形成したことで、溶融した各部材２１、２３の濡れ性が良好となる。そのため、第１の部材２１とAuメタライズ層２５とが良好に金属接合するようになる。同様に、第３の部材２３とAuメッキ膜５０も互いに良好に金属接合するようになる。   At this time, since the Au metallized layer 25 is formed on the upper surface of the semiconductor element 10 and the Au plating film 50 is previously formed on the lower surface of the heat sink 18, the wettability of the melted members 21 and 23 is improved. For this reason, the first member 21 and the Au metallized layer 25 are favorably metal-bonded. Similarly, the third member 23 and the Au plating film 50 are well metal-bonded to each other.

また、上記のように放熱板１８を押圧することで、溶融した各接続部材２１、２３が横方向に広がってその厚みが減少するため、最終的には接着剤１９がパッケージ基板２に当接し、接着剤１９を介してパッケージ基板２に放熱板１８が接着される。   Further, by pressing the heat radiating plate 18 as described above, the melted connecting members 21 and 23 spread in the lateral direction and the thickness thereof decreases, so that the adhesive 19 finally comes into contact with the package substrate 2. The heat sink 18 is bonded to the package substrate 2 through the adhesive 19.

ここで、本工程における接続部材１６の加熱温度は、第１の部材２１と第３の部材２３の各々の融点よりも高く、かつ、第２の部材２２の融点よりも低く設定される。そのため、本工程では、加熱により第２の部材２２は溶融せず、第１及び第３の部材２１、２３のみを選択的に溶融することができる。   Here, the heating temperature of the connection member 16 in this step is set to be higher than the melting points of the first member 21 and the third member 23 and lower than the melting point of the second member 22. Therefore, in this step, the second member 22 is not melted by heating, and only the first and third members 21 and 23 can be selectively melted.

更に、本実施形態では、上記のように第２の部材２２の面積よりも第１及び第３の部材２１、２３の面積を狭くしたので、溶融したこれらの部材２１、２３が第２の部材２２の側面２２ａの横にはみ出るのを抑制できる。   Furthermore, in this embodiment, since the area of the 1st and 3rd members 21 and 23 was made narrower than the area of the 2nd member 22 as mentioned above, these melted members 21 and 23 are the 2nd member. It can suppress that it protrudes to the side of 22 side 22a.

なお、このように各部材２１、２２を溶融した後の接続部材１６の厚さΔTは約０．２mm程度となる。また、パッケージ基板２と放熱板１８とが接着された状態での接着剤１９の厚さΔDは約０．５mm程度となる。   Note that the thickness ΔT of the connecting member 16 after the members 21 and 22 are melted in this way is about 0.2 mm. Further, the thickness ΔD of the adhesive 19 in a state where the package substrate 2 and the heat radiating plate 18 are bonded is about 0.5 mm.

更に、パッケージ基板２の主面から半導体素子１０の上面までの高さHは約０．６１mmである。   Further, the height H from the main surface of the package substrate 2 to the upper surface of the semiconductor element 10 is about 0.61 mm.

その後に、図１９に示すように、第１の電極パッド３上に外部接続端子５としてハンダバンプを搭載し、本実施形態に係る半導体装置４０の基本構造を完成させる。   After that, as shown in FIG. 19, solder bumps are mounted on the first electrode pads 3 as the external connection terminals 5 to complete the basic structure of the semiconductor device 40 according to the present embodiment.

図２１は、半導体装置４０の上面図であって、先の図１９は図２１のX1−X1線に沿う断面図に相当する。   FIG. 21 is a top view of the semiconductor device 40, and FIG. 19 corresponds to a cross-sectional view taken along line X1-X1 of FIG.

図２１に示されるように、第３の部材２３の面積を第２の部材２２のそれよりも狭くしたことで、第３の部材２３の側面２３ａは第２の部材２２の側面２２ａから約１mm程度の後退量ΔLだけ後退する。   As shown in FIG. 21, the side surface 23 a of the third member 23 is about 1 mm from the side surface 22 a of the second member 22 by making the area of the third member 23 smaller than that of the second member 22. Retreat by a certain amount of retraction ΔL.

そして、このように後退した側面２２ａの横であって、パッケージ基板２の上に、電子部品１４が配設される。   Then, the electronic component 14 is disposed on the package substrate 2 next to the side surface 22a thus retracted.

なお、図１９のように外部接続端子５を搭載せずに半導体装置の製造工程を終了することにより、LGA(Land Grid Array)型の半導体装置を製造するようにしてもよい。   In addition, as shown in FIG. 19, an LGA (Land Grid Array) type semiconductor device may be manufactured by ending the manufacturing process of the semiconductor device without mounting the external connection terminal 5.

以上説明した本実施形態によれば、図１８に示したように、第２の部材２２と比較して第１及び第３の部材２１、２３の面積を狭くしたので、加熱により溶融したこれらの部材２１、２３が第２の部材２２の側面２２ａの横にはみ出難くなる。   According to this embodiment described above, as shown in FIG. 18, since the areas of the first and third members 21 and 23 are narrower than those of the second member 22, these melted by heating. The members 21 and 23 are unlikely to protrude from the side surface 22a of the second member 22.

その結果、はみ出た各部材２１、２３によってボイド２９（図２（ｂ）参照）が形成される危険性が低減されるようになり、ボイドの破裂が原因のハンダ粒３０が発生しなくなる。そのため、ハンダ粒３０によって電子部品１４の端子が電気的にショートするのを防止でき、半導体装置４０の信頼性を向上させることができる。   As a result, the risk that voids 29 (see FIG. 2B) are formed by the protruding members 21 and 23 is reduced, and solder particles 30 caused by void bursting are not generated. Therefore, it is possible to prevent the terminals of the electronic component 14 from being electrically short-circuited by the solder grains 30, and to improve the reliability of the semiconductor device 40.

しかも、上記のように第１の部材２１と第３の部材２３のはみ出しが抑制されるので、これらの部材２１、２３によって第２の部材２２が完全に囲まれることがない。   Moreover, since the protrusion of the first member 21 and the third member 23 is suppressed as described above, the second member 22 is not completely surrounded by these members 21 and 23.

既述のように、第２の部材２２は、自身が変形することで放熱板１８から半導体素子１０に加わる応力を緩和するものである。よって、上記のように各部材２１、２３によって第２の部材２２が囲まれないことで、第２の部材２２の動きの自由度が確保され、第２の部材２２による応力緩和の効果を維持することができる。   As described above, the second member 22 relieves the stress applied to the semiconductor element 10 from the heat sink 18 due to its deformation. Therefore, since the second member 22 is not surrounded by the members 21 and 23 as described above, the degree of freedom of movement of the second member 22 is secured, and the stress relaxation effect by the second member 22 is maintained. can do.

図２２は、本実施形態の別の効果について説明するための断面図である。   FIG. 22 is a cross-sectional view for explaining another effect of the present embodiment.

図１０に示したように、接続部材１６を単層構造としたのでは、溶融した接続部材１６が電子部品１４に接触する危険性があった。   As shown in FIG. 10, if the connection member 16 has a single-layer structure, there is a risk that the molten connection member 16 contacts the electronic component 14.

これに対し、本実施形態のように三層構造の接続部材１６のうち第３の部材２３の面積を第２の部材２２のそれよりも狭くすると、第２の部材２２が第３の部材２３から張り出すようになる。しかも、第２の部材２２の融点は第３の部材２３のそれよりも高いので、第３の部材２３溶融時に第２の部材２２は溶融しない。   On the other hand, when the area of the third member 23 of the connection member 16 having the three-layer structure is narrower than that of the second member 22 as in the present embodiment, the second member 22 becomes the third member 23. Overhang from. In addition, since the melting point of the second member 22 is higher than that of the third member 23, the second member 22 does not melt when the third member 23 melts.

これにより、第２の部材２２は、溶融した第３の部材２３が下方に滴下するのを防止する庇として機能するようになる。そのため、溶融した第３の接続部２３が電子部品１４上に滴下するのを防止でき、電子部品１４の端子同士が電気的にショートする危険性を低減できる。   Thereby, the 2nd member 22 comes to function as a cage | basket which prevents that the fuse | melted 3rd member 23 dripped below. Therefore, it is possible to prevent the melted third connection portion 23 from dripping onto the electronic component 14, and to reduce the risk that the terminals of the electronic component 14 are electrically short-circuited.

特に、図２２の点線のように電子部品１４の上方にまで第２の部材２２の側面２２ａを延長すると、溶融した第３の接続部２３が電子部品１４上に滴下する危険性を一層効果的に低減できる。   In particular, when the side surface 22a of the second member 22 is extended above the electronic component 14 as indicated by the dotted line in FIG. 22, the risk of the molten third connecting portion 23 dripping on the electronic component 14 is more effective. Can be reduced.

図２３は、本実施形態により奏される他の効果について説明するための断面図である。   FIG. 23 is a cross-sectional view for explaining another effect achieved by the present embodiment.

図１２（ａ）〜（ｃ）を参照して説明したように、放熱板１８の下面にメッキ膜２６を形成すると、そのメッキ膜２６の膨れ２６ａが原因で接続部材１６にボイド２９が発生することがある。   As described with reference to FIGS. 12A to 12C, when the plating film 26 is formed on the lower surface of the heat radiating plate 18, a void 29 is generated in the connection member 16 due to the swelling 26 a of the plating film 26. Sometimes.

本実施形態では、上記のように第２の部材２２の側面２２ａが第３の部材２３から張り出すので、仮に図２３のようにボイド２９が破裂してハンダ粒３０が飛散しても、第２の部材２２が庇として機能するので、電子部品１４にハンダ粒３０が付着するのを防止できる。   In the present embodiment, since the side surface 22a of the second member 22 protrudes from the third member 23 as described above, even if the void 29 is ruptured and the solder particles 30 are scattered as shown in FIG. Since the second member 22 functions as a ridge, it is possible to prevent the solder particles 30 from adhering to the electronic component 14.

特に、図２３の点線のように電子部品１４の上方にまで第２の部材２２の側面２２ａを延長することで、第２の部材２２の庇としての機能が高められ、電子部品１４上へのハンダ粒３０の飛散をより効果的に抑制することが可能となる。   In particular, by extending the side surface 22a of the second member 22 above the electronic component 14 as shown by the dotted line in FIG. It becomes possible to suppress the scattering of the solder grains 30 more effectively.

（第２実施形態）
第１実施形態では、図２０を参照して説明したように、面積の異なるハンダペレットをそれらの自重で積み重ねて接続部材１６を作製した。 (Second Embodiment)
In the first embodiment, as described with reference to FIG. 20, the connection member 16 is manufactured by stacking solder pellets having different areas with their own weight.

これに対し、本実施形態では、以下の第１例及び第２例のようにハンダシートの圧着により接続部材１６を作製する。   On the other hand, in this embodiment, the connection member 16 is produced by crimping a solder sheet as in the following first and second examples.

・第１例
図２４（ａ）は、第１例に係る接続部材１６の作製方法について説明するための上面図であり、図２４（ｂ）は図２４（ａ）のX2−X2線に沿う断面図である。 First Example FIG. 24A is a top view for explaining a manufacturing method of the connection member 16 according to the first example, and FIG. 24B is along the line X2-X2 in FIG. It is sectional drawing.

図２４（ａ）、（ｂ）に示すように、本実施形態では、第１〜第３のロール４１〜４３に第１〜第３の部材２１〜２３として巻き取られたハンダシートを展開し、加圧ローラ４６、４７により各接続部材２１〜２３を圧着する。このようなハンダシートの圧着体はクラッド材とも呼ばれる。   As shown in FIGS. 24A and 24B, in the present embodiment, the solder sheets wound up as the first to third members 21 to 23 on the first to third rolls 41 to 43 are developed. The connecting members 21 to 23 are pressure-bonded by the pressure rollers 46 and 47. Such a solder sheet crimp is also referred to as a clad material.

また、これらの接続部材２１〜２３のうち、第１の部材２１と第３の部材２３としては、それらの幅W1が第２の部材２２の幅W2よりも狭いハンダシートを使用する。   Of these connecting members 21 to 23, as the first member 21 and the third member 23, solder sheets having a width W1 narrower than a width W2 of the second member 22 are used.

そして、上記のようにして各接続部材２１〜２３のクラッド材を形成した後、カッター４９によってそのクラッド材を切断して個片化し、複数の接続部材１６を製造する。   And after forming the clad material of each connection member 21-23 as mentioned above, the clad material is cut | disconnected and separated into pieces by the cutter 49, and the several connection member 16 is manufactured.

図２５は、このようにして作製された接続部材１６の斜視図である。   FIG. 25 is a perspective view of the connection member 16 manufactured in this manner.

本実施形態では、クラッド材を切断して接続部材１６を製造するので、接続部材１６の切断面１６ｘにおいては各接続部材２１〜２３の各側面は一平面内にある。   In this embodiment, since the connection member 16 is manufactured by cutting the clad material, the side surfaces of the connection members 21 to 23 are within one plane on the cut surface 16x of the connection member 16.

そして、矩形状の第３の部材２３の四辺のうち、切断面１６ｘに現れない対向する二辺のみにおいて、第３の部材２３の側面２３ａが第２の部材２２の側面２２ａから後退する。   Then, of the four sides of the rectangular third member 23, the side surface 23 a of the third member 23 retreats from the side surface 22 a of the second member 22 only on two opposing sides that do not appear on the cut surface 16 x.

図２６（ａ）は、この接続部材１６を備えた半導体装置の平面図であり、図２６（ｂ）は図２６（ａ）のX3−X3線に沿う断面図である。   FIG. 26A is a plan view of a semiconductor device provided with the connection member 16, and FIG. 26B is a cross-sectional view taken along line X3-X3 in FIG.

図２６（ａ）、（ｂ）に示すように、電子部品１４は、第３の部材２３の後退した側面２３ａの横のパッケージ基板２上に設けられる。   As shown in FIGS. 26A and 26B, the electronic component 14 is provided on the package substrate 2 next to the retracted side surface 23 a of the third member 23.

このようにすることで、側面２３ａから張り出した第２の部材２２が、電子部品１４にハンダ粒が付着するのを防止する庇として機能するので、第１実施形態と同様にハンダ粒が原因で電子部品１４の端子が電気的にショートするのを抑制できる。   By doing so, the second member 22 that protrudes from the side surface 23a functions as a ridge that prevents the solder particles from adhering to the electronic component 14, and therefore, due to the solder particles as in the first embodiment. It is possible to suppress electrical shorting of the terminals of the electronic component 14.

更に、接続部材１６の切断面１６ｘの横には電子部品１４を設けないので、切断面１６ｘにおいてボイド２９が形成されてそれが原因でハンダ粒３０が発生しても、そのハンダ粒３０が電子部品１４に付着することがない。   Further, since the electronic component 14 is not provided beside the cut surface 16x of the connection member 16, even if the void 29 is formed on the cut surface 16x and the solder particles 30 are generated due to the voids 29, the solder particles 30 are It does not adhere to the component 14.

以上説明した本例によれば、３層のハンダシートを圧着してなるクラッド材を切断することにより接続部材１６を作製する。これによれば、接続部材１６中の各部材２１〜２３が互いに圧着されているため、各部材２１〜２３をペレット材から作製してその各々が自重だけで積み重ねっている場合のように、各部材２１〜２３同士が作業中に位置ずれすることがない。そのため、半導体素子１０の上に接続部材１６を載せるときに、各部材２１〜２３の各々の位置合わせをする必要がなく、第１実施形態と比較して作業効率が向上する。   According to this example described above, the connecting member 16 is produced by cutting the clad material formed by pressure-bonding the three-layer solder sheet. According to this, since the members 21 to 23 in the connecting member 16 are pressure-bonded to each other, each member 21 to 23 is made from a pellet material, and each of them is stacked only by its own weight, Each member 21-23 does not shift in position during work. Therefore, when mounting the connection member 16 on the semiconductor element 10, it is not necessary to align each of the members 21 to 23, and the working efficiency is improved as compared with the first embodiment.

・第２例
図２７（ａ）は、第２例に係る接続部材１６の作製方法について説明するための上面図であり、図２７（ｂ）は図２７（ａ）のX4−X4線に沿う断面図である。なお、これらの図において第１例で説明したのと同じ要素には第１例と同じ符号を付し、以下ではその説明を省略する。 Second Example FIG. 27A is a top view for explaining a manufacturing method of the connection member 16 according to the second example, and FIG. 27B is along the line X4-X4 in FIG. It is sectional drawing. In these drawings, the same elements as those described in the first example are denoted by the same reference numerals as those in the first example, and description thereof will be omitted below.

本例では、図２７（ａ）に示すように、第１の部材２１と第３の部材２３として、それらの幅W1が第２の部材２２の幅W2よりも狭いハンダシートを使用する。   In this example, as shown in FIG. 27A, as the first member 21 and the third member 23, solder sheets whose width W1 is narrower than the width W2 of the second member 22 are used.

そして、各接続部材２１〜２３の各々の一辺２１ｂ〜２３ｂが揃った状態で、各接続部材２１〜２３を圧着することによりクラッド材を形成し、カッター４９によりそのクラッド材を切断して複数の接続部材１６を作成する。   And in the state where each side 21b-23b of each connection member 21-23 has gathered, a clad material is formed by crimping each connection member 21-23, and the clad material is cut with a cutter 49, and a plurality of the claws are cut. The connecting member 16 is created.

図２８は、このようにして作製された接続部材１６の斜視図である。   FIG. 28 is a perspective view of the connection member 16 manufactured in this manner.

本実施形態では、上記のように各接続部材２１〜２３の各一辺２１ｂ〜２３ｂを揃えた状態でクラッド材の切断を行う。そのため、矩形状の第３の部材２３は、上記の一辺２３ｂに対向する一辺のみにおいて、その側面２３ａが第２の部材２２の側面２２ａから後退する。   In the present embodiment, the clad material is cut in a state in which the sides 21b to 23b of the connection members 21 to 23 are aligned as described above. Therefore, the side surface 23 a of the rectangular third member 23 recedes from the side surface 22 a of the second member 22 only on one side facing the one side 23 b.

図２９（ａ）は、この接続部材１６を備えた半導体装置の平面図であり、図２９（ｂ）は図２９（ａ）のX5−X5線に沿う断面図である。   FIG. 29A is a plan view of a semiconductor device provided with the connection member 16, and FIG. 29B is a cross-sectional view taken along line X5-X5 in FIG.

図２９（ａ）、（ｂ）に示されるように、電子部品１４は、第３の部材２３の後退した側面２３ａの横のパッケージ基板２上に設けられ、これ以外の領域には設けられない。そのため、第２の部材２２を電子部品１４に対する庇として機能させることができ、電子部品１４上にハンダ粒が飛散する危険性を低減できる。   As shown in FIGS. 29A and 29B, the electronic component 14 is provided on the package substrate 2 next to the side surface 23a that the third member 23 has retracted, and is not provided in any other region. . Therefore, the 2nd member 22 can be functioned as a cage | basket with respect to the electronic component 14, and the danger that a solder grain will scatter on the electronic component 14 can be reduced.

以上説明した本例においても、第１例と同様に、クラッド材から接続部材１６を作製するので、各部材２１〜２３の全てをペレット材から作製する場合と比較して作業性が向上する。   Also in this example described above, since the connection member 16 is produced from the clad material as in the first example, the workability is improved as compared with the case where all the members 21 to 23 are produced from the pellet material.

（第３実施形態）
第２実施形態では、三層のハンダシートからなるクラッド材を利用して接続部材１６を製造した。 (Third embodiment)
In the second embodiment, the connection member 16 is manufactured using a clad material made of a three-layer solder sheet.

これに対し、本実施形態では、以下のようにクラッド材とハンダペレットとを併用して接続部材１６を製造する。   On the other hand, in this embodiment, the connection member 16 is manufactured by using a clad material and solder pellets together as follows.

図３０（ａ）は、本実施形態に係る接続部材１６の作製方法について説明するための上面図であり、図３０（ｂ）は図３０（ａ）のX6−X6線に沿う断面図である。なお、これらの図において第２実施形態で説明したのと同じ要素には第２実施形態と同じ符号を付し、以下ではその説明を省略する。   FIG. 30A is a top view for explaining a manufacturing method of the connection member 16 according to the present embodiment, and FIG. 30B is a cross-sectional view taken along line X6-X6 in FIG. . In these drawings, the same elements as those described in the second embodiment are denoted by the same reference numerals as those in the second embodiment, and description thereof will be omitted below.

接続部材１６の製造にあたっては、図３０（ａ）、（ｂ）に示すように、第１及び第２の部材２１、２２としてロール４１、４２に巻き取られたハンダシートを展開し、それらを加圧ローラ４６、４７によって圧着して二層構造のクラッド材を作製する。   In manufacturing the connecting member 16, as shown in FIGS. 30A and 30B, the solder sheets wound around the rolls 41 and 42 as the first and second members 21 and 22 are developed, and they are used. A clad material having a two-layer structure is produced by pressure bonding with pressure rollers 46 and 47.

なお、本実施形態では、これらの接続部材２１、２２は、それぞれ同一の幅W3を有する。   In the present embodiment, these connecting members 21 and 22 each have the same width W3.

そして、カッター４９により上記の二層構造のクラッド材を切断することにより、平面形状が概略矩形の接続部材１６の下側層１６ｂを形成する。   Then, the lower layer 16b of the connection member 16 having a substantially rectangular planar shape is formed by cutting the clad material having the two-layer structure with the cutter 49.

図３１（ａ）は、このようにして作製した下側層１６ｂの斜視図である。   FIG. 31A is a perspective view of the lower layer 16b produced in this manner.

その後、図３１（ｂ）に示すように、下側層１６ｂの中央に第３の部材２３として平面形状が概略矩形の低融点ハンダペレットを積み重ね、接続部材１６を完成させる。   Thereafter, as shown in FIG. 31 (b), low melting point solder pellets having a substantially rectangular planar shape are stacked as the third member 23 in the center of the lower layer 16 b to complete the connection member 16.

その第３の部材２３は、第２の部材２２よりも狭い面積を有しており、矩形の各辺における側面２３ａは第２の部材２２の側面２２ａから後退している。なお、この第３の部材２３は、自重によって第２の部材２２の上に載っているだけであり、クラッド材におけるように各部材２２、２３が圧着されているわけではない。   The third member 23 has a smaller area than the second member 22, and the side surface 23 a on each side of the rectangle is set back from the side surface 22 a of the second member 22. The third member 23 is merely placed on the second member 22 by its own weight, and the members 22 and 23 are not crimped as in the clad material.

図３２（ａ）は、この接続部材１６を備えた半導体装置の平面図であり、図３２（ｂ）は図３２（ａ）のX7−X7線に沿う断面図である。   FIG. 32A is a plan view of a semiconductor device provided with the connection member 16, and FIG. 32B is a cross-sectional view taken along line X7-X7 in FIG.

図３２（ａ）、（ｂ）に示されるように、第１の部材２１と第２の部材２２は、電子部品１４の上方にまで延在して、電子部品１４を覆うように設けられる。   As shown in FIGS. 32A and 32B, the first member 21 and the second member 22 are provided so as to extend above the electronic component 14 and cover the electronic component 14.

以上説明した本実施形態では、接続部材１６の下側層１６ｂについてはクラッド材から作製し、第３の部材２３についてはハンダペレットから作製する。   In the present embodiment described above, the lower layer 16b of the connection member 16 is made of a clad material, and the third member 23 is made of a solder pellet.

よって、接続部材１６の作製に際し、下側層１６ｂと第３の部材２３との位置合わせのみ行えばよく、第１〜第３の部材２１〜２３の全てをハンダペレットから作製する場合のように全ての接続部材２１〜２３の位置合わせをする必要がなく、作業性がよい。   Therefore, when the connection member 16 is manufactured, only the alignment of the lower layer 16b and the third member 23 may be performed, as in the case where all of the first to third members 21 to 23 are manufactured from solder pellets. It is not necessary to align all the connecting members 21 to 23, and workability is good.

更に、図３２（ｂ）に示したように、電子部品１４を覆うように第２の部材２２を設けるので、メッキ膜２６に膨れ２６ａ（図１２（ａ）参照）が存在する場合でも、膨れが破裂したときに発生するハンダ粒が電子部品１４上に飛散するのを防止できる。これにより、電子部品１４の端子同士がハンダ粒で電気的にショートする危険性を低減でき、半導体装置の信頼性を向上させることができる。   Further, as shown in FIG. 32B, since the second member 22 is provided so as to cover the electronic component 14, even if the swelling 26a (see FIG. 12A) exists in the plating film 26, the swelling is caused. It is possible to prevent the solder particles generated when the rupture of the solder is scattered on the electronic component 14. Thereby, the danger that the terminals of the electronic component 14 are electrically short-circuited with solder grains can be reduced, and the reliability of the semiconductor device can be improved.

１、４０…半導体装置、２…パッケージ基板、２ａ…一方の主面、２ｂ…他方の主面、３…第１の電極パッド、４…第２の電極パッド４、５…外部接続端子、６…第３の電極パッド、７…ハンダバンプ、８…電極、１０…半導体素子、１０ａ…側面、１０ｂ…上面、１１…アンダーフィル樹脂、１４…電子部品、１４ａ…端子、１６…接続部材、１６ｂ…下側層、１６ｘ…切断面、１８…放熱板、１８ａ…下面、１９…接着剤、２１〜２３…第１〜第３の部材、２２ａ、２３ａ…側面、２１ｂ〜２３ｂ…一辺、２５…Auメタライズ層、２６…メッキ膜、２６ａ…膨れ、２９…ボイド、３０…ハンダ粒、３３…ディスペンサ、４１〜４３…第１〜第３のロール、４６、４７…加圧ローラ、５０…Auメッキ膜、５１…Niメッキ膜。
DESCRIPTION OF SYMBOLS 1, 40 ... Semiconductor device, 2 ... Package substrate, 2a ... One main surface, 2b ... The other main surface, 3 ... 1st electrode pad, 4 ... 2nd electrode pad 4, 5 ... External connection terminal, 6 3rd electrode pad 7 Solder bump 8 Electrode 10 Semiconductor element 10a Side surface 10b Upper surface 11 Underfill resin 14 Electronic component 14a Terminal 16 Connection member 16b Lower layer, 16x ... cut surface, 18 ... heat sink, 18a ... lower surface, 19 ... adhesive, 21-23 ... first to third members, 22a, 23a ... side, 21b-23b ... one side, 25 ... Au Metallized layer, 26 ... plating film, 26a ... swelling, 29 ... void, 30 ... solder grain, 33 ... dispenser, 41-43 ... first to third rolls, 46, 47 ... pressure roller, 50 ... Au plating film 51 Ni plating film.

Claims (8)

基板と、
前記基板の上方に配設された半導体素子と、
前記半導体素子の上方に配設された第１の金属層と、
前記第１の金属層の上方に配設された第２の金属層と、
前記第２の金属層の上方に配設された放熱部材と、
前記第１の金属層と前記第２の金属層とを接続する、In及びAgを含む接続部材と、
を有し、
前記接続部材は、前記第１の金属層の上方に配設され、第１の融点を有する第１の部材と、
前記第１の部材の上方に配設され、前記第１の融点よりも高い第２の融点を有し、前記第１の部材よりも広い面積を有する第２の部材と、
前記第２の部材の上方に配設され、前記第２の融点よりも低い第３の融点を有し、前記第２の部材よりも狭い面積を有する第３の部材と、
を有することを特徴とする半導体装置。 A substrate,
A semiconductor element disposed above the substrate;
A first metal layer disposed above the semiconductor element;
A second metal layer disposed above the first metal layer;
A heat dissipating member disposed above the second metal layer;
A connection member containing In and Ag that connects the first metal layer and the second metal layer;
I have a,
The connecting member is disposed above the first metal layer and has a first member having a first melting point;
A second member disposed above the first member, having a second melting point higher than the first melting point, and having a larger area than the first member;
A third member disposed above the second member, having a third melting point lower than the second melting point and having a smaller area than the second member;
Wherein a to have a. 前記接続部材はIn-3Agを含むことを特徴とした、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the connection member includes In-3Ag. 前記第１の金属層及び前記第２の金属層は、Auを含んだ層を有することを特徴とした、請求項１又は請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein each of the first metal layer and the second metal layer includes a layer containing Au. 前記第１の部材は、前記第３の部材と同一の材料を含むことを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。The semiconductor device according to claim 1, wherein the first member includes the same material as that of the third member. 基板上に半導体素子を配設する工程と、
前記半導体素子の上方に第１の金属層を配設する工程と、
前記第1の金属層の上方にIn及びAgを含む接続部材を配設する工程と、
放熱部材の一の面に第２の金属層を形成する工程と、
前記接続部材の上方に前記第２の金属層が接するように前記放熱部材を加熱押圧しながら接続する工程と、
前記放熱部材を押圧しながら、接続部材を加熱することにより、前記半導体素子と前記放熱部材を接続する工程と、
を有し、
前記接続部材は、前記第１の金属層の上方に配設され、第１の融点を有する第１の部材と、
前記第１の部材の上方に配設され、前記第１の融点よりも高い第２の融点を有し、前記第１の部材よりも広い面積を有する第２の部材と、
前記第２の部材の上方に配設され、前記第２の融点よりも低い第３の融点を有し、前記第２の部材よりも狭い面積を有する第３の部材と、
を有することを特徴とする半導体装置の製造方法。 Disposing a semiconductor element on a substrate;
Disposing a first metal layer above the semiconductor element;
Disposing a connection member containing In and Ag above the first metal layer;
Forming a second metal layer on one surface of the heat dissipation member;
Connecting the heat radiating member while heating and pressing so that the second metal layer is in contact with the connection member; and
Connecting the semiconductor element and the heat dissipation member by heating the connection member while pressing the heat dissipation member;
I have a,
The connecting member is disposed above the first metal layer and has a first member having a first melting point;
A second member disposed above the first member, having a second melting point higher than the first melting point, and having a larger area than the first member;
A third member disposed above the second member, having a third melting point lower than the second melting point and having a smaller area than the second member;
The method of manufacturing a semiconductor device which is characterized in that have a. 前記In及びAgを含む接続部材は、In-3Agを含むことを特徴とする請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5 , wherein the connection member containing In and Ag contains In-3Ag. 前記第１の金属層及び前記第２の金属層は、Auを含んだ層からなることを特徴とする請求項５又は請求項６に記載の半導体装置の製造方法。 The first metal layer and said second metal layer, a method of manufacturing a semiconductor device according to claim 5 or claim 6, characterized in that it consists of including the Au layer. 前記第２の部材はCuを含み、前記第１の部材及び前記第３の部材はIn-3Agを含むことを特徴とする請求項５乃至７のいずれか１項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5, wherein the second member includes Cu, and the first member and the third member include In-3Ag. .
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