JP5774154B1 - Resistance change memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable resistance memory capable of performing set writing and reset writing with high reliability. A variable resistance memory according to the present invention includes a memory array including a memory element in which a reversible and nonvolatile variable resistance element and a selection transistor are connected in series between a bit line BL and a source line SL. And row selection means for selecting a selection transistor in the row direction, column selection means for selecting a variable resistance element in the column direction, and control means for controlling writing of the variable resistance element. The control means applies a bias voltage for resetting the variable resistance element to the selected bit line and source line, and applies a pulse P2 or P3 that gradually increases the voltage to the gate of the selected selection transistor. Apply. [Selection] Figure 8

Description

  The present invention relates to a resistance change type memory using a variable resistance element, and more particularly to resetting of a resistance change type memory and writing of a set.

As a nonvolatile memory that replaces a flash memory, a resistance change type memory using a variable resistance element has attracted attention. A resistance change type memory is known as a memory that stores data by applying a pulse voltage to a film of metal oxide or the like and reversibly and non-volatilely setting the resistance of the film. Since the resistance change type memory can rewrite data with voltage (a small amount of current), the power consumption is small, and the cell area is about 6F ² (F is The diameter of the wiring is as small as several tens of nanometers) and can be increased in density. Further, there is an advantage that the readout time is about 10 nanoseconds, which is as high as a DRAM (Patent Documents 1 and 2).

  FIG. 1 is a circuit diagram showing a typical configuration of a memory array of a conventional resistance change type memory. One memory element includes a variable resistance element and an access or selection transistor connected in series with the variable resistance element. m × n (m and n are integers greater than or equal to 1) memory elements are formed in a two-dimensional array, a word line WL is connected to the gate of the selection transistor, and one electrode of the selection transistor is a variable resistor One electrode of the element is connected, and the other electrode is connected to the source line SL. The other electrode of the variable resistance element is connected to the bit line BL.

  The variable resistance element is composed of a thin film of metal oxide such as hafnium oxide (HfOx), for example, and the resistance value is reversibly and non-volatile depending on the magnitude and polarity of the applied pulse voltage. Can be set to sex. Setting (writing) the variable resistance element to the high resistance state is referred to as setting (SET), and setting (writing) to the low resistance state is referred to as reset (RESET).

  The memory element can be accessed in bit units by selecting the word line WL, the bit line BL, and the source line SL. For example, when writing to the cell unit M11, a voltage corresponding to the set or reset is applied to the bit line BL1 and the source line SL1, and the transistor is turned on by the word line WL1. As a result, the variable resistance element is set or reset. When reading data from the cell unit M11, a voltage for reading is applied to the bit line BL1 and the source line SL1, and the transistor is turned on by the word line WL1. A voltage or current corresponding to the setting or resetting of the variable resistance element appears on the bit line BL1, and this is detected by the sense circuit.

JP 2012-64286 A JP 2008-41704 A

  When a thin film of metal oxide such as hafnium oxide (HfOx) is used as the material of the variable resistance element, the metal oxide must be formed as an initial setting. Usually, forming is performed by applying a voltage Vf somewhat larger than that when writing a variable resistance element to the thin film, and the polarity of the set and reset is determined by the direction of the current flowing through the thin film when a voltage is applied. Is done. Such forming is performed before shipping the resistance change type memory.

  FIG. 2A shows an example of forming. For example, 0V is applied to the bit line BL, 4V is applied to the source line SL as a forming voltage, and a voltage 6V required to turn on the selection transistor T is applied to the word line WL. As a result, a current flows from the source line SL to the bit line BL in the variable resistance element R, and forming is performed. When the forming is performed, the variable resistance element R is in a high resistance state, that is, in a set state.

  In order to reset the variable resistance element R, that is, to bring it into a low resistance state, as shown in FIG. 2B, for example, a bit line BL = 0V, a source line SL = 2V, and a word line WL = 4V are applied. As a result, a current flows through the variable resistance element R from the source line SL toward the bit line BL, and reset is set in the variable resistance element R. To set the variable resistance element R, as shown in FIG. 2C, for example, a bit line BL = 2V, a source line SL = 0V, and a word line WL = 4V are applied. Thereby, a current flows through the variable resistance element R from the bit line BL to the source line SL, and a set is set in the variable resistance element R. Thus, to reset the variable resistance element R, a bias voltage of SL> BL is applied, and to set, a bias voltage of SL <BL is applied.

  However, when the variable resistance element is reset, that is, when a metal oxide is grown between the electrodes of the variable resistance element R, the growth of the metal oxide is not always performed with good reproducibility. Among the reset variable resistance elements, there is a so-called tail bit that flows a larger current than a normally reset variable resistance element. FIG. 3 shows the current distribution characteristics of the reset variable resistance element. This figure shows a graph when a single layer of hafnium oxide is used as the metal oxide and the film thickness is 7 nm and 5 nm. Here, the reset variable resistance element is a tail bit in which a current of 1 μA or more flows. The normally reset variable resistance elements are within 3σ of the whole, but tail bit variable resistance elements are generated in the remaining 0.3%. A variable resistance element that allows a larger current to flow, such as a tail bit, causes deterioration of the element quickly and easily causes a failure. Furthermore, even if such a variable resistance element is to be set, it may not be able to be set normally by a normal bias voltage. Therefore, it is desirable to suppress the generation of tail bits.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a variable resistance memory capable of performing highly reliable set and reset writing.

  A variable resistance memory according to the present invention includes a memory array including a memory element in which a reversible and nonvolatile variable resistance element and a selection transistor are connected in series between a bit line and a source line; Row selection means for selecting a selection transistor, column selection means for selecting a variable resistance element in the column direction, and control means for controlling writing of the variable resistance element, wherein the control means includes the selected bit line A bias voltage for resetting the variable resistance element is applied to the source line, and a pulse that gradually increases the voltage is applied to the gate of the selection transistor selected by the row selection means.

  Preferably, the pulse is a ramp waveform pulse. Preferably, the pulse is a plurality of pulse trains whose voltage gradually increases. Preferably, the control means includes verify means for verifying pass / fail of the reset variable resistance element, and further applies the pulse to the variable resistance element rejected by the verify means. Preferably, the verifying unit performs individual verification of the plurality of reset variable resistance elements in the selected word line in units of word lines. Preferably, the verifying unit executes a plurality of resets in the selected word line and individual verification of the set variable resistance element in units of word lines.

  In a variable resistance memory including a memory array including a memory element in which a reversible and nonvolatile variable resistance element and a selection transistor are connected in series between a bit line and a source line. Applying a bias voltage for resetting the variable resistance element to the selected bit line and source line, and applying a pulse that gradually increases the voltage to the gate of the selected selection transistor. Apply.

  According to the present invention, when the variable resistance element is reset, a pulse that gradually increases the voltage is applied to the gate of the selection transistor, so that current can be prevented from flowing to the variable resistance element at once. As a result, it is possible to prevent the reset variable resistance element from flowing an excessive current exceeding a predetermined size. By suppressing the excess current of the reset variable resistance element, the speed at which the variable resistance element deteriorates can be suppressed, and the variable resistance element can be easily set.

It is a figure which shows the array structure of the conventional resistance change memory. 2A shows an example of the bias voltage at the time of forming, FIG. 2B shows an example of the bias voltage at the time of resetting, and FIG. 2C shows an example of the bias voltage at the time of setting. It is a graph which shows an example of the generation rate of a tail bit. It is a figure which shows the structure of the resistance change memory based on the Example of this invention. It is a figure which shows the structure of the memory element of a present Example. 6A shows the waveform of a pulse applied to the gate of the selection transistor at the time of conventional resetting, and FIGS. 6B and 6B show the waveform applied to the gate of the selection transistor at the time of resetting in this embodiment. FIG. 4 is a table showing an example of each bias voltage at the time of resetting, setting and reading of the resistance change type memory according to the embodiment of the present invention. It is a figure which shows the voltage waveform example of each part at the time of the reset by the Example of this invention. It is a figure which shows the example of an operation waveform of each part at the time of the read of the Example of this invention. 10 is a flowchart showing verification when a plurality of variable resistance elements according to an embodiment of the present invention are reset. 10 is a flowchart showing verification when a plurality of variable resistance elements according to an embodiment of the present invention are set. It is a figure which shows the other structural example of the memory element by the Example of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. However, it should be noted that in the drawings, each part is highlighted for easy understanding, and is different from an actual device scale.

  FIG. 4 is a block diagram showing the overall configuration of the resistance change memory according to the embodiment of the present invention. The resistance change type memory 100 according to this embodiment includes a memory array 110 in which a plurality of memory elements arranged in a matrix are arranged, and an input / output buffer that is connected to an external input / output terminal I / O and holds input / output data. 120, an address register 130 for receiving address data from the input / output buffer 120, a data register 140 for holding input / output data, a controller 150 for controlling each unit based on command data from the input / output buffer 120, The word line selection circuit 160 that decodes the row address information Ax from the address register 130 and selects and drives the word line based on the decoding result, and the column address information Ay from the address register 130 and decodes the bit line information based on the decoding result. A column selection circuit 170 that performs selection and driving, and a column selection circuit Sense circuit 180 that detects a signal read from the cell unit selected by 170 or holds write data to the selected cell unit, and a bias voltage necessary for the set, reset, and read operations of the variable resistance element And a voltage generation circuit 190 that supplies this to the word line selection circuit 160, the sense circuit 180, and the like.

  As shown in FIG. 1, the memory array 110 includes a plurality of memory elements M11, M12,... Mmn arranged in a matrix direction, and one memory element includes one variable resistance element and one selection transistor. Composed. A variable resistance element and a selection transistor are connected in series between the bit line BL and the source line SL, and the gate of the selection transistor is connected to the word line.

  The state where the variable resistance element is set corresponds to either data “0” or “1”, and the state where the variable resistance element is reset corresponds to either data “1” or “0”. The controller 150 controls writing (set, reset), reading operation, and the like based on an external command. The word line selection circuit 160 selects a word line based on the row address information Ax received from the outside, and the column selection circuit 170 selects a bit line based on the column address information Ay received from the outside. Under the control of the controller 150, a bias voltage corresponding to writing (set, reset) and reading is applied to the selected word line, bit line, and source line.

  FIG. 5 shows a connection relationship between the memory element and the sense circuit 180. One memory element includes a variable resistance element R and a selection transistor T connected in series between the source line SL and the bit line BL. A word line WL is commonly connected to the gates Vg of the selection transistors T. In the example shown in FIG. 5, n-bit memory elements are arranged in the row direction, and bit lines BL 1 to BLn of the n-bit memory elements are connected to the sense circuit 180. When the selected memory element is read, the voltage or current appearing on the bit line of the selected memory element is detected by the sense circuit 180. When writing to the selected memory element is performed, the write data input from the input / output buffer 120 is transferred to the sense circuit 180, and the sense circuit 180 applies the voltage corresponding to the write data, that is, set or reset. It is generated on the selected bit line BL or source line SL.

  Next, writing (reset, setting) to the variable resistance element will be described. The controller 150 starts writing in response to a command or the like obtained from the external input / output terminal, and controls the operation of each unit. The row address Ax obtained from the input / output buffer 120 is provided to the word line selection circuit 160, and the column address Ay is provided to the column selection circuit 170. Write data is held by the sense circuit 180 via the data register 140. Further, the voltage generation circuit 190 supplies a voltage necessary for writing to the word line selection circuit 160, the sense circuit 180, and the like in accordance with an instruction from the controller 150. The sense circuit 180 supplies a voltage corresponding to data “0” or “1” to the bit line BL and the source line SL selected based on the decoding result of the column selection circuit 170.

  In the present embodiment, when the variable resistance element R is reset, the variable resistance element R is controlled so that no current suddenly flows, that is, the current gradually flows through the variable resistance element R. When a current is suddenly applied to the variable resistance element R, that is, when a large amount of energy is applied at once, the metal oxide of the variable resistance element grows at once, and this causes a so-called tail bit to flow an excessive current. It becomes easy to be generated. For this reason, in this embodiment, in order to prevent a large current from flowing through the variable resistance element R at once, control is performed so that the impedance of the selection transistor T gradually decreases.

  In a preferred embodiment, the voltage VSL is applied to the source line SL, the voltage VBL is applied to the bit line BL (VSL> VBL), and a pulse that gradually increases the voltage from 0 V is applied to the gate Vg of the selection transistor T. Apply. FIG. 6A shows the waveform of the pulse P1 applied to the gate of the selection transistor T at the time of conventional resetting, and FIG. 6B shows the pulse applied to the gate of the selection transistor T of this embodiment. It is a waveform of P2. As shown in FIG. 6A, when a rectangular pulse P1 is applied to the gate Vg of the selection transistor T, the selection transistor T is turned on instantaneously, and a large current flows from the source line SL to the variable resistance element R. Will be swept away. As a result, a metal oxide path having a high current density is formed between the electrodes, and a tail bit is easily generated. In contrast, when a ramp-shaped pulse P2 as shown in FIG. 6B is applied to the gate Vg of the selection transistor T, the conductance of the selection transistor T gradually increases so as to be proportional to the voltage of the pulse P2. The drain current supplied to the variable resistance element R gradually increases. For this reason, a large amount of current does not flow through the variable resistance element R at once, and the supply of current to the variable resistance element R can be gradually increased. As a result, the generation of tail bits can be suppressed.

  In another preferred aspect of the present embodiment, a plurality of pulse trains P3 may be applied to the gate of the selection transistor T as shown in FIG. The plurality of pulse trains P3 include a plurality of pulses whose voltage gradually increases. Even when such a series of pulse trains P3 is applied to the selection transistor, the energy of the current supplied to the variable resistance element R is gradually increased, so that a metal oxide path having a high current density is instantaneously formed. The formation is suppressed.

  Next, FIG. 7 shows an example of a specific bias voltage at the time of setting, resetting and reading out the variable resistance element of this embodiment, and FIGS. 8A and 8B show operations when the variable resistance element is reset. An example of a waveform is shown.

  When resetting the variable resistance element, as shown in FIGS. 7 and 8A, VBL = −0.5 V is applied to the bit line BL of the selected memory element, and VSL = 2.6 V is applied to the source line SL. The Next, a ramp pulse P2 as shown in FIG. 6B, whose voltage changes from 0 V to 4 V, is applied to the selected word line (gate Vg) for a period of about 100 ns. Thereby, a current flows from the source line SL to the bit line BL in the variable resistance element R, and reset writing in the low resistance state is performed. When a plurality of pulse trains P3 as shown in FIG. 6C are used, as shown in FIG. 8B, a plurality of pulse trains P3 whose voltage gradually increases are applied in a period of about 100 ns. The

  On the other hand, when setting the variable resistance element, first, VBL = 2.4V is applied to the bit line BL of the selected memory element, and VSL = 0V is applied to the source line SL. Next, a pulse of 2.3 V is applied to the selected word line (gate Vg). As a result, a current flows from the bit line BL toward the source line SL, and the variable resistance element R is set to a high resistance state.

  Next, the reading operation of the cell unit of the resistance change type memory according to this embodiment will be described. The controller 150 starts reading in response to a command from the external input / output terminal, and controls the operation of each unit. In addition, the address data obtained from the input / output buffer 120 is received, the row address Ax is provided to the word line selection circuit 160, and the column address Ay is provided to the column selection circuit 170.

  FIG. 9 shows an example of the waveform of each part during the read operation. The sense circuit 180 applies VBL = 0.2 V to the bit line BL and VSL = 0 V to the source line SL of the memory element selected based on the decoding result of the column selection circuit 170. Preferably, the bit line BL is precharged to 0.2V. If the potential difference between the bit line BL and the source line SL is too large, a large current flows through the variable resistance element. For this reason, it is desirable that the potential difference be as small as possible, that is, the potential difference can be detected by the sense circuit 180. Next, the word line selection circuit 160 applies 3 V to the word line (gate Vg) selected based on the row address Ax. When the variable resistance element R is set, almost no current flows from the bit line BL to the source line SL, and this state is detected by the sense circuit 180. On the other hand, when the variable resistance element R is reset, a current flows from the bit line BL to the source line SL, and this state is detected by the sense circuit 180.

  Next, the further preferable aspect of a present Example is demonstrated. In a preferred aspect of the present embodiment, when the variable resistance element is written (reset, set), write verification is performed to determine whether or not the variable resistance element is acceptable. The variable resistance memory can access a memory element bit by bit and read or write the accessed memory element. Therefore, in one aspect, when writing to one memory element is performed, it is possible to perform write verification to the one memory element. In another aspect, when writing (set, reset) to a plurality of memory elements in one page (one word line) is performed simultaneously or successively, a plurality of memory elements in the page are stored. Individual verifications are performed simultaneously or sequentially. For example, when an external input / output terminal has a data width of × 16 and 16-bit data is written at the same time, or when one page is 2 Kbytes, a plurality of data are continuously included in the page. When writing is performed, write verification to the memory element of the page where writing has been performed is performed.

  FIG. 10 is a flowchart showing verification when a plurality of variable resistance elements in the page is reset, and FIG. 11 is a verification flow when a plurality of variable resistance elements in the page is set. For convenience, FIGS. 10 and 11 individually show reset and set verification flows. However, in reality, when a plurality of variable resistance elements in one page are reset and set, these verifications are performed simultaneously. Can be implemented.

  Based on the write data obtained from the external input / output terminal, the selected variable resistance element is reset and set (S100, S200). The reset and set bias conditions are as shown in FIG.

  When resetting and setting are completed, verification is performed next (S102, S202). Bias conditions at the time of reset and set verification are the same as those at the time of read operation. Next, the pass / fail of each memory element to which writing in the page is performed is determined (S104, S204). When it is determined that the reset is acceptable, the voltage of the bit line BL is changed to VBL = 2.6 (S106). As a result, the bit line BL and the source line SL have the same potential, and no more current flows through the variable resistance element. On the other hand, if it is determined as unacceptable, the same bias condition as in step S100 is maintained, and the lamp pulse P2 or the pulse train P3 is applied once again (S108).

  When it is determined that the set is acceptable, the voltage of the bit line BL is changed to VBL = 0V (S206). As a result, the bit line BL and the source line SL have the same potential, and no more current flows through the variable resistance element. On the other hand, if it is determined as unacceptable, VBL = 2.2 V, whose voltage is set slightly lower than in step S200, is applied to the bit line BL (S208). In this way, verification is performed on all the variable resistance elements written in the page.

  As described above, according to the present embodiment, the rapid supply of current to the variable resistance element to be reset is suppressed, so that a metal oxide path having a high current density is prevented from being formed at once and reset. It is possible to reduce the occurrence of a tail bit in which an excessive current flows through the variable resistance element. Therefore, it becomes easy to set the reset variable resistance element under a normal bias condition, and writing with high reliability can be performed. Furthermore, by suppressing the generation of tail bits, it is possible to suppress the failure of the element and extend the life of the element.

  Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

  In the above embodiment, as shown in FIG. 5, one terminal of the variable resistance element R is connected to the bit line BL, the other terminal is connected to one terminal of the selection transistor T, and the other terminal of the selection transistor T In the example shown in FIG. 12A, one end of the selection transistor T is connected to the bit line according to the polarity of the variable resistance element R. The present invention can also be applied to a configuration in which the other terminal of the variable resistance element R is connected to the source line SL, connected to the line BL.

  Further, in the above embodiment, an example in which the memory element is composed of one transistor + 1 variable resistance element is shown. However, as shown in FIG. 12B, two transistors T1, T2 + 2 variable resistance elements R1, It may be a complementary memory element made of R2. In the complementary memory element, the variable resistance elements R1 and R2 store complementary data (set, reset), and complementary data is output to the bit lines BL and / BL. .

100: resistance change type memory 110: memory array 120: input / output buffer 130: address register 140: data register 150: controller 160: word line selection circuit 170: column selection circuit 180: sense circuit 190: voltage generation circuit R: variable resistance Element T: selection transistors P1, P2, P3: pulse

Claims (12)

A memory array including a memory element in which a reversible and nonvolatile variable resistance element and a selection transistor are connected in series between a bit line and a source line;
A row selection means for selecting a selection transistor in the row direction;
Column selection means for selecting variable resistance elements in the column direction;
Control means for controlling writing of the variable resistance element,
The control means applies a bias voltage for resetting the variable resistance element to a low resistance state or setting it to a high resistance state to the selected bit line and source line, and the selection transistor selected by the row selection means Apply a gate voltage to the gate of
The gate voltage when resetting the variable resistance element is a pulse of a ramp waveform in which the voltage gradually increases or a plurality of pulse trains in which the voltage gradually increases,
The variable resistance memory, wherein the gate voltage when setting the variable resistance element is a pulse having a constant voltage value smaller than the maximum voltage when resetting the variable resistance element. The control means includes verify means for verifying the pass / fail of the reset variable resistance element and the pass / fail of the set variable resistance element, and when the variable resistance element reset by the verify means fails, Writing is performed by further applying a pulse of the ramp waveform or the plurality of pulse trains to the resistance element, and when the variable resistance element set by the verifying unit fails, the constant voltage value is applied to the variable resistance element. The variable resistance memory according to claim 1, wherein writing is performed by further applying a pulse having the same. When the reset variable resistance element is rejected, the first bias voltage is applied to the bit line related to the variable resistance element, and the second bias voltage is applied to the source line. When it is acceptable, a second bias voltage is applied to the bit line and the source line related to the variable resistance element,
When the set variable resistance element is rejected, the third bias voltage is applied to the bit line related to the variable resistance element, and the fourth bias voltage is applied to the source line. 3. The variable resistance memory according to claim 2, wherein when it is acceptable, a fourth bias voltage is applied to a bit line and a source line related to the variable resistance element. 4. The variable resistance memory according to claim 3, wherein the third bias voltage is smaller than a bias voltage applied to a bit line at the time of writing performed before verification by the verifying unit. 5. The variable resistance memory according to claim 2 , wherein the verify unit executes individual verification of a plurality of reset or set variable resistance elements in a selected word line in units of word lines. 6. . 6. The variable resistance memory according to claim 4 or 5, wherein the verify means executes individual verification of a plurality of reset or set variable resistance elements in a selected word line in units of word lines. A variable resistance memory writing method including a memory array including a memory element in which a reversible and nonvolatile variable resistance element and a selection transistor are connected in series between a bit line and a source line,
A bias voltage is applied to the selected bit line and source line to reset or set the variable resistance element to a low resistance state or to a high resistance state, and a gate voltage is applied to the gate of the selected selection transistor.
The gate voltage when resetting the variable resistance element is a pulse of a ramp waveform in which the voltage gradually increases or a plurality of pulse trains in which the voltage gradually increases,
The writing method, wherein the gate voltage when setting the variable resistance element is a pulse having a constant voltage value smaller than the maximum voltage when resetting the variable resistance element. The writing method further includes a verify step for verifying the pass / fail of the reset variable resistance element and the pass / fail of the set variable resistance element, and when the variable resistance element reset by the verify step fails, Writing is performed by further applying the pulse of the ramp waveform or the plurality of pulse trains to the resistance element, and when the variable resistance element set by the verify step fails, the constant voltage value is applied to the variable resistance element. The writing method according to claim 7, wherein writing is performed by further applying a pulse having the same. When the reset variable resistance element is rejected, the first bias voltage is applied to the bit line related to the variable resistance element, and the second bias voltage is applied to the source line. When it is acceptable, a second bias voltage is applied to the bit line and the source line related to the variable resistance element,
When the set variable resistance element is rejected, the third bias voltage is applied to the bit line related to the variable resistance element, and the fourth bias voltage is applied to the source line. 9. The writing method according to claim 8, wherein when it is acceptable, a fourth bias voltage is applied to the bit line and the source line related to the variable resistance element. The write method according to claim 9, wherein the third bias voltage is smaller than a bias voltage applied to a bit line at the time of writing performed before the verification in the verify step . The writing method according to claim 10, wherein the writing method further performs individual verification of a plurality of reset or set variable resistance elements in a selected word line for each word line. 12. The writing method according to claim 10, wherein the writing method further performs individual verification of a plurality of reset or set variable resistance elements in a selected word line in units of word lines.

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