JP5765155B2 - Voltage comparison circuit, A / D converter, and semiconductor device - Google Patents

Description

  The embodiments referred to in this application relate to a voltage comparison circuit, an A / D converter, and a semiconductor device.

  A voltage comparison circuit is a circuit that has a function of determining the level of an analog signal applied to an input terminal, and is one of the important components of an analog circuit such as an A / D (Analog to Digital) converter. is there.

  The basic operation of the voltage comparison circuit is to determine the level of the DC potential of the applied signal. For example, the comparison of the comparison reference voltage and the voltage of the analog input signal is performed in each voltage comparison circuit by DC coupling in parallel. Compare high and low directly.

  However, in this case, the voltage range of the analog input signal that can be converted is limited due to the operation range of the voltage comparison circuit. Furthermore, since each voltage comparison circuit operates with a different determination voltage, the operating point inside each voltage comparison circuit is different. As a result, a difference occurs in the response time of each voltage comparison circuit, resulting in speed limitations.

  Therefore, a method of operating via AC coupling has been proposed. That is, a method of short-circuiting between a capacitor and an input / output terminal of a voltage comparator (comparator) when inputting an analog signal (generally called auto-zero) is known.

  By the way, conventionally, various types of voltage comparison circuits, A / D converters, and semiconductor devices have been proposed.

JP 2010-124405 A JP 2010-252287 A

S. Park et al., "A 3.5 GS / s 5-b Flash ADC in 90 nm CMOS," 2006 IEEE Custom Integrated Circuits Conference, pp. 489-492, September 2006 K. Nagaraj et al., "A 700M Sample / s 6b Read Channel A / D Converter with 7b Servo Mode," IEEE International Solid-State Circuits Conference, vol. XLIII, pp. 426-427, February 2000 D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS," IEEE International Solid-State Circuits Conference, vol. XLVII, pp. 264-265, February 2004 Y. Chen et al., "A 9b 100MS / s 1.46mW SAR ADC in 65nm CMOS," 2009 IEEE Asian Solid-State Circuits Conference, pp. 145-148, Nov. 2009 M. Kijima et al., "A 6b 3GS / s Flash ADC with Background Calibration," 2009 IEEE Custom Integrated Circuits Conference (CICC), pp. 283-286, 2009

  As described above, there is known an auto-zero method for short-circuiting between a capacitor and an input / output terminal of a comparator when an analog signal is input.

  However, since the auto-zero method adds the output impedance of the comparator and the on-resistance of the switch to charge the capacitor, the time constant becomes large and takes time. In addition, since a current flows through the comparator during auto zero, it is not preferable from the viewpoint of power consumption.

  In recent years, a method of biasing the level of about half of the power supply voltage (Vdd / 2) to a common voltage (common-mode voltage) using a latch-type voltage comparator has become mainstream. In this case, since the offset of the comparator is not canceled, for example, an offset cancel function is incorporated in the comparator.

  By the way, in the parallel type (flash type) A / D converter in which the comparators are arranged and operated in parallel, the offset of the comparator directly affects the linearity, and in the worst case, the judgment point of the adjacent comparator is reversed. Therefore, there is a possibility that monotonicity cannot be maintained.

  When a general successive approximation A / D converter is used, for example, when multiple channels are used in a single channel without time interleaving, the offset of the comparator itself is determined by the same comparator. It appears as an offset of the A / D conversion result and does not affect the linearity.

  However, if the common-mode voltage (common voltage Vcm) is not set appropriately, for example, if a large imbalance occurs in the characteristics of the pMOS and nMOS transistors due to manufacturing variations, etc., the voltage is set to half the power supply voltage (Vdd / 2). The resulting Vcm is not necessarily the optimum point.

  That is, if the common-mode voltage is different even if the potential difference of the differential input signal of the comparator is 1 mV, for example, the differential input signals (Vip, Vim) are (0, 1), (100, 101), (200, 201), (300, 301), (400, 401) mV, the operation speed of the comparator is different.

  Furthermore, depending on the setting of the common-mode voltage, not only the response speed of the comparator is reduced, but also the comparator may be erroneously determined in some cases.

  According to an embodiment, there is provided a voltage comparison circuit including a comparator, a determination unit that determines a response speed of the comparator, and a voltage controller.

  The voltage controller controls common-mode voltages at a plurality of inputs of the comparator so as to reduce a delay in response speed of the comparator according to a determination result of the determiner.

  The disclosed voltage comparison circuit, A / D converter, and semiconductor device have an effect that the operation speed can be improved by applying an optimum common-mode voltage to the comparator.

FIG. 1 is a block diagram schematically showing the overall configuration of the voltage comparison circuit according to the present embodiment. FIG. 2 is a circuit diagram showing an example of a comparator in the voltage comparison circuit shown in FIG. FIG. 3 is a block diagram showing a first embodiment of the voltage comparison circuit. FIG. 4 is a timing chart for explaining the operation of the determiner shown in FIG. FIG. 5 is a flowchart for explaining an example of the determination process in the determiner shown in FIG. FIG. 6 is a diagram for explaining the determination process shown in FIG. FIG. 7 is a flowchart for explaining another example of the determination process in the determiner shown in FIG. FIG. 8 is a diagram for explaining the determination process shown in FIG. FIG. 9 is a block diagram illustrating an example of a successive approximation A / D converter to which the voltage comparison circuit according to the present embodiment is applied. FIG. 10 is a timing chart for explaining an example of the operation of the successive approximation A / D converter shown in FIG. FIG. 11 is a timing chart for explaining another example of the operation of the successive approximation A / D converter shown in FIG. FIG. 12 is a block diagram illustrating an example of a flash A / D converter to which the voltage comparison circuit according to the present embodiment is applied. FIG. 13 is a block diagram showing one voltage comparison circuit in the flash A / D converter shown in FIG. FIG. 14 is a block diagram showing a second embodiment of the voltage comparison circuit. FIG. 15 is a block diagram illustrating an example of a semiconductor device to which an A / D converter using the voltage comparison circuit according to the present embodiment is applied.

  Hereinafter, embodiments of a voltage comparison circuit, an A / D converter, and a semiconductor device will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram schematically showing the overall configuration of the voltage comparison circuit according to the present embodiment. In FIG. 1, reference numeral 100 indicates a voltage comparison circuit, and 200 indicates a clock generator.

  As shown in FIG. 1, the voltage comparison circuit 100 includes a voltage comparator (comparator) 1, a determiner 2, and a voltage controller 3. The comparator 1 compares the levels of the differential input signals Vip and Vim, and the determiner 2 determines the slowness of the operation of the comparator 1 and controls the voltage controller 3.

  The voltage controller 3 controls the common-mode voltage (common voltage) of the input signals Vip and Vim according to the output of the determiner 2. The clock generator 200 generates a clock (φC) for the comparator 1 and the determiner 2 in the voltage comparison circuit 100.

  As described above, the voltage comparison circuit 100 according to this embodiment includes the comparator 1 that is the common-mode voltage control target, the determination unit 2 that determines the delay time of the output of the comparator 1, and the determination result based on the determination result of the determination unit 2. Is fed back to the common-mode voltage of the input signals Vip and Vim of the comparator 1 and reflected.

  Here, for example, a comparator such as a strong arm type comparator can be applied to the comparator 1, and a determination unit 2 and a voltage controller 3 are added to the comparator 1 to provide the fastest response time. A loop that automatically gives the resulting common-mode voltage is formed.

  As a result, the common-mode voltage from the voltage controller 3 is added to the differential input signals Vip and Vim and input to the comparator 1.

  The comparator 1 performs comparison (determination) in synchronization with the clock from the clock generator 200 on the input signals Vip and Vim to which the common-mode voltage is applied. As an initial value of the voltage controller 3, for example, the lowest common-mode voltage is given. The differential voltage (difference voltage between Vip and Vim) is a constant voltage.

  The determiner 2 holds (stores) the delay time of the comparator 1 as td0, further increases the common-mode voltage slightly, and then causes the comparator 1 to determine. Then, the delay time td0 stored before increasing the common-mode voltage and the delay time tdx after increasing the common-mode voltage are determined.

  Here, when td0> tdx, td0 = tdx is set, and the comparator 1 performs the following determination without changing the output of the voltage controller 3. Further, the determiner 2 compares the updated td0 with the delay time tdx.

  On the other hand, when Td0 <tdx (when it is later than before), td0 is not updated, and the voltage controller 3 increases the common-mode voltage. When Td0 <tdx is observed a plurality of times, the loop is terminated. By this loop, it is possible to finally obtain the common-mode voltage that has the fastest delay time (the shortest delay time).

  FIG. 2 is a circuit diagram showing an example of a comparator in the voltage comparison circuit shown in FIG. 1, and shows a strong arm type comparator. As shown in FIG. 2, the comparator 1 includes a plurality of pMOS (p-channel MOS) transistors Tp11 to Tp16 and a plurality of nMOS (n-channel MOS) transistors Tn11 to Tn15.

  Here, the transistors Tp11, Tp12, Tp15, and Tp16 indicate pull-up transistors. At the time of reset, the clock φC becomes a low level “L” and is turned on, and the drain node of each transistor is connected to the high potential power line. Pull up to the voltage of Vdd.

  When the comparison operation is performed, the transistors Tp11, Tp12, Tp15, and Tp16 are turned off when the clock φC is at the high level “H”, and the differential input signals Vip and Vim are compared and determined. The differential output signals Vop and Vom are output.

  Here, the input signals Vip and Vim are input to the gates of the differential pair transistors Tn13 and Tn14. The output signals Vop and Vom are output from the common connection node of the drain of Tp13 and the drain of Tn11 and the common connection node of the drain of Tp14 and the drain of Tn12.

  The transistor Tn15 is turned on when φC is “H” to flow current to the ground (GND) according to the clock φC input to its gate, and is turned off and reset when φC is “L”.

  The comparator 1 shown in FIG. 2 is merely an example, and it goes without saying that various circuits including, for example, complementary circuits in which p-channel and n-channel transistors are reversed may be used.

  FIG. 3 is a block diagram showing a first embodiment of the voltage comparison circuit, and FIG. 4 is a timing chart for explaining the operation of the decision unit shown in FIG.

  In FIG. 3, reference numeral 21 is an exclusive NOR (EXNOR) gate, 22 is a flip-flop (FF), 23 is a control circuit (CNTL: up / down counter), 24 is a demultiplexer (D-MPX), and 25 is a delay. Indicates a vessel.

  Here, the EXNOR gate 21 functions as a response detector that detects the response of the comparator 1. The FF 22, the control circuit 23, the D-MPX 24, and the control path from the D-MPX 24 to the delay unit 25 (and the control path to the D / A converter 3) constitute a loop processing circuit.

  As shown in FIG. 4, the output signals Vop and Vom of the comparator 1 are pulled up by the transistors Tp12 and Tp15 to “H” in the reset state of φC = “L”. When the clock φC rises from “L” to “H”, the comparator 1 starts a comparison (determination) operation.

  The output signals Vop and Vom of the comparator 1 are initially “H”, but positive feedback acts on the difference between Vop and Vom, and one is distributed to “H” and the other to “L”. The Vop and Vom are output as VO = “L” by the EXNOR gate 21 in the subsequent stage.

  That is, the EXNOR gate 21 detects that the determination of the comparator 1 is completed based on different levels of Vop and Vom, and outputs the low level “L” output signal VO. The low level “L” signal VO is input to the D terminal of the FF 22.

  On the other hand, the clock φC is also input to the delay unit 25 of the determination unit 2. The delay device 25 has a variable resistor Rd, a pMOS transistor Tp25, and an nMOS transistor Tn25 connected in series between Vdd and GND. Here, the resistance value of the variable resistor Rd is controlled by the output of the control circuit 23 via the D-MPX 24.

  That is, as shown in FIG. 4, the output signal V1 of the delay unit 25 changes to “L” in response to the rising of the clock φC to “H”, and this is used as the input clock (CK) of the FF22. Here, the FF 22 takes in the signal VO input to the data input D at the fall of the signal V1 input to the clock terminal CK from “H” to “L”.

  If the delay of the signal VO of the comparator 1 is slow (the delay time is long) with respect to the falling edge of the output signal V1 of the delay unit 25, VO = “H” is taken in, and the FF 22 ] Signal Od is output.

  That is, when the delay time td (V0) on the comparator 1 side is larger than the delay time Td (V1) of the delay device 25 (Td (V1)> td (V0)), the signal Od becomes “H”. .

  On the other hand, when the delay of the signal VO of the comparator 1 is fast (the delay time is short) with respect to the fall of the output signal V1 of the delay unit 25, VO = “L” is taken in, and the FF 22 The “L” signal Od is output.

  That is, when the delay time td (V0) on the comparator 1 side is smaller than the delay time Td (V1) of the delay device 25 (Td (V1) <td (V0)), the signal Od becomes “L”. .

  The output signal Od of the FF 22 is taken into the control circuit 23 at the subsequent stage. Here, the control circuit 23 is composed of, for example, an up / down counter, and counts H / L of the signal Od.

  Therefore, for example, when counting up by Od = “H” (that is, the comparator 1 is faster than the delay device 25 or the delay device 25 is slower than the comparator 1), the variable resistance Rd The resistance value is controlled to be small. As a result, the delay time of the delay unit 25 is shortened.

  By repeating this, the delay time of the delay unit 25 is gradually shortened and becomes shorter than the delay time of the comparator 1, and Od = “L” is output. In response to Od = “L”, the control circuit 23 controls the voltage controller 3 (D / A (Digital to Analog) converter for common-mode voltage control) 3.

  Here, the D / A converter 3 starts from a state where the lowest voltage is output at first. The control circuit 23 lowers the input code (Din) of the D / A converter (negative logic) 3 by counting down. As a result, the output voltage Vout of the D / A converter 3 increases.

  Then, the output voltage Vout of the D / A converter 3 is supplied to the comparator 1 as an in-phase voltage, and a loop for performing determination based on the clock φC is executed again. This loop is repeated, and when Od = “L” (that is, the comparator 1 is faster than the delay unit 25) is obtained twice in succession, the input code of the D / A converter 3 is set to “1”. Return to end the loop. As a result, the common-mode voltage of the comparator 1 converges to a voltage that minimizes the delay time of the comparator 1.

  FIG. 5 is a flowchart for explaining an example of the determination process in the determiner shown in FIG. 3, and FIG. 6 is a view for explaining the determination process shown in FIG. That is, the flowchart shown in FIG. 5 summarizes the processing of the above-described determiner.

  As shown in FIG. 5, when the determination process of the determiner 2 is started, the output signal Din = 0 of the D-MPX 24 is set to Rd = Max in step ST11. That is, in step ST11, the signal Din = 0 is set, the common-mode voltage from the D / A converter 3 is set to the minimum voltage, and further, the resistance value of the variable resistor Rd of the delay unit 25 is set to the maximum value to maximize the delay by the delay unit 25. To.

  Next, the process proceeds to step ST12 where the delay times are compared, that is, the delay time (signal VO) by the comparator 1 by the FF 22 and the delay time (signal V1) by the delay device 25 are compared. Furthermore, it progresses to step ST13 and it is determined whether the output signal Od = FF of FF22 is.

  If it is determined in step ST13 that Od = “L”, that is, if it is determined that the comparator 1 is faster than the delay unit 25, the process proceeds to step ST15, and the resistance value of the variable resistor Rd of the delay unit 25 is set. Move down one step.

  That is, in step ST15, the delay time by the delay unit 25 is decreased (speed-up), the process returns to step ST12, and the same processing is repeated. By repeating this, the delay time of the delay unit 25 is gradually shortened and becomes shorter than the delay time of the comparator 1, and Od = “H” is output.

  If it is determined in step ST13 that Od = “L” is not satisfied (Od = “H”), the process proceeds to step ST14 to determine whether Od (n−1) = “L”. Here, Od (n−1) indicates the previous determination result.

  If it is determined in step ST14 that Od (n−1) = “L”, the process proceeds to step ST16 and the signal Din is lowered by one step. That is, the input code (Din) of the D / A converter 3 is lowered by one step, the output voltage Vout of the D / A converter 3 is increased (the common-mode voltage at the inputs Vip and Vim of the comparator 1 is increased), and step Returning to ST12, the same processing is repeated.

  If it is determined in step ST14 that Od (n−1) = “L” is not satisfied (Od (n−1) = “H”), that is, Od = “L” (comparison twice). If it is determined that the device 1 is faster than the delay device 25, the process proceeds to step ST17.

  In step ST17, the output signal Din of the D-MPX 24 is increased by one step, that is, the output voltage Vout of the D / A converter 3 is returned by one step, and the common-mode voltage at the inputs Vip and Vim of the comparator 1 is controlled. The process ends.

  As described above, as shown in FIG. 6, the common-mode voltage (Vcm) can be converged to an optimum voltage that minimizes the delay Td. In the flowchart of FIG. 5, Od = “L” is detected twice in steps ST13 and ST14, and then the common-mode voltage by the D / A converter 3 is returned by one step in step ST17. Can be changed.

  That is, the common-mode voltage may be terminated when it starts from the lowest point and rises to a voltage at which the delay time td becomes the minimum. For example, after detecting Od = “L” three times, D / Changes such as returning the common-mode voltage by the A converter 3 by two stages are also possible.

  As described above, the processing described with reference to FIGS. 5 and 6 ends the loop processing (determination processing) when the common-mode voltage reaches the optimum value by the loop processing circuit described above. Yes. Next, the processing described with reference to FIGS. 7 and 8 is to continue the loop processing even after the common-mode voltage reaches the optimum value by the loop processing circuit.

  FIG. 7 is a flowchart for explaining another example of the determination process in the determiner shown in FIG. 3, and FIG. 8 is a view for explaining the determination process shown in FIG. Here, as is clear from a comparison between FIG. 7 and FIG. 5 described above, steps ST11 to ST17 are common.

  As shown in FIG. 7, if it is determined in step ST14 that Od (n−1) = “L”, as described above, the process proceeds to step ST17, and the output signal Din of the D-MPX 24 is increased by one stage. The process proceeds to step ST18.

  That is, if it is determined in step ST14 that Od = “L” twice in succession (the comparator 1 is faster than the delay unit 25), the process proceeds to step ST17 to input the input code Din of the D / A converter 3 Is lowered by one step, and the D / A converter 3 lowers (returns) the common-mode voltage by one step.

  In step ST18, the delay time is compared, that is, the delay time (signal VO) by the comparator 1 by the FF 22 and the delay time (signal V1) by the delay device 25 are compared. Then, the process proceeds to step ST19 to determine whether or not the output signal Od of the FF 22 is “L”.

  If it is determined in step ST19 that Od = “L” is not satisfied (Od = “H”), that is, if it is determined that the comparator 1 is slower than the delay unit 25, the process proceeds to step ST20, where the delay unit The resistance value of 25 variable resistors Rd is increased by one step.

  That is, in step ST20, the delay time by the delay unit 25 is increased (speed down), the process returns to step ST18, and the same processing is repeated. By repeating this, the delay time of the delay unit 25 is gradually extended, becomes longer than the delay time of the comparator 1, and outputs Od = “L”.

  If it is determined in step ST19 that Od = “L”, the process proceeds to step ST21 and the delay times are compared. Furthermore, it progresses to step ST22 and it is determined whether it is Od = "L".

  If it is determined in step ST22 that Od = “L” is not satisfied (Od = “H”), that is, if it is determined that the comparator 1 is slower than the delay unit 25, the process proceeds to step ST23. In step ST23, the input code Din of the D / A converter 3 is increased by one stage, the common mode voltage by the D / A converter 3 is decreased by one stage, the process returns to step ST23, and the same processing is repeated.

  If it is determined in step ST22 that Od = “L”, that is, if it is determined that the comparator 1 is faster than the delay unit 25, the process returns to step ST12 via step ST16 described above, and similar processing is performed. repeat.

  As described above, as shown in FIG. 8, the resistance value of the variable resistor Rd of the delay device 25 is decreased in order from the maximum side, and then the resistance value of the variable resistor Rd that has become too small is returned. The voltage can be converged to a voltage at which the delay time td of the comparator 1 is minimized.

  As described above, the processing described with reference to FIGS. 7 and 8 is configured to continue the loop processing even after the common-mode voltage reaches the optimum value by the loop processing circuit described above. As a result, for example, even when the optimum value of the common-mode voltage changes due to fluctuations in the power supply voltage of the device to which the voltage comparison circuit of the present embodiment is applied or due to changes in the ambient temperature, it is possible to cope with it.

  As described above, an optimal common-mode voltage can be applied to the comparator, and it is possible to improve tolerance to variations in manufacturing and voltage and temperature during actual operation, and to improve accuracy and operating speed. become. Note that the flowcharts of FIGS. 5 and 7 described above are merely examples, and it goes without saying that various changes can be made.

  FIG. 9 is a block diagram illustrating an example of a successive approximation A / D converter to which the voltage comparison circuit according to the present embodiment is applied, and FIG. 10 illustrates an operation of the successive approximation A / D converter illustrated in FIG. It is a timing diagram for demonstrating.

  In FIG. 9, reference numeral 30p denotes a positive logic side capacitance circuit, 30m denotes a negative logic side capacitance circuit, and 300 denotes a SAR (Successive Approximation Register) logic circuit.

  As shown in FIG. 9, in the successive approximation A / D converter, the comparator 1, the determination unit 2, and the D / A converter (voltage controller) 3 constituting the voltage comparison circuit of the first embodiment described above. Has been applied. The D / A converter 3 is provided for the positive and negative logic side capacitance circuits 30p and 30m, respectively.

  As shown in FIGS. 9 and 10, in the successive approximation A / D converter, for example, during the period (sampling period) when the control signal φA is “H”, the analog signal Vin (Vip, Vim) has a capacitance of 1C. , 2C, 3C, 8C, 16C, 32C.

  At this time, both of the input terminals of the differential comparator 1 are given a predetermined identical voltage by the D / A converter 3 as an in-phase voltage. As a result, the capacitors 1C, 2C, 3C, 8C, 16C, and 32C are charged with charges corresponding to the voltage of the analog signal Vin and the common-mode voltage from the D / A converter 3.

  Here, since the period when the signal φA is “H” is a sampling period, the comparator 1 does not need to operate originally. Therefore, in this sampling period, the clock φC is raised to “H” at the timing Ta to cause the comparator 1 to perform a determination operation.

  Note that the timings T5 to T0 during the period (determination period) when the signal φA is “L” cause the comparator 1 to perform the determination operation in a state where the connections of the switches SW0 to SW5 are controlled by the control signals φ0 to φ5, respectively. It is.

  That is, the control of the switches SW0 to SW5 by the control signals φ0 to φ5 in the determination period of the successive approximation A / D converter (period in which the signal φA is “L”) is the same as that of a normal successive approximation A / D converter. The description thereof is omitted.

  FIG. 9 shows an example in which the capacities of 1C, 2C, 3C, 8C, 16C, and 32C are connected and controlled by six switches SW0 to SW5. The capacities of 1C, 2C, 3C, 8C, 16C, and 32C may be controlled by seven switches.

  FIG. 11 is a timing chart for explaining another example of the operation of the successive approximation A / D converter shown in FIG. As is clear from comparison between FIG. 11 and FIG. 10 described above, in FIG. 11, the determination operation by the comparator 1 performed for controlling the common-mode voltage is performed immediately after the signal φA is not in the sampling period of “H”. To do.

  That is, the determination operation of the comparator 1 for controlling the common-mode voltage is performed from the end of the sampling when the signal φA becomes “L” to the timing T0 when the comparison operation for performing the A / D conversion by the comparator 1 is started. In other words, it is performed at the timing Tb.

  Thus, when the determination operation of the comparator 1 for controlling the common-mode voltage is performed at the timing Tb, the common-mode voltages of the input signals Vip and Vim after being stored in the capacitors 1C, 2C, 3C, 8C, 16C, and 32C. Can be controlled.

  As described above, the common-mode voltage applied to the input signals Vip and Vim of the comparator 1 can be obtained by the comparator 1 by the determination processing (loop processing) described with reference to FIGS. Convergence to voltage.

  Even when different analog signals are applied at different times, the voltage input to the comparator 1 at each timing Ta and Tb is always determined by the D / A converter 3, so that the above loop is operated. Can do.

  In the above setting, since the common-mode voltage is controlled during the sampling period of a normal successive approximation A / D converter, an extra period is not required for the actual A / D conversion operation. It is possible to always run this loop in the background without sacrificing.

  In FIG. 9, for example, if the analog signal Vin is fixed and the switch controlled by the signals φ0 to φ5 is fixed in the conduction state of Vin, the determination process of the comparator 1 that performs the comparison operation six times in the normal operation. Can all be used in a loop for controlling the common-mode voltage.

  In this case, the period for controlling the common-mode voltage is limited to the foreground process because the original A / D conversion operation by the successive approximation A / D converter cannot be performed.

  FIG. 12 is a block diagram showing an example of a flash A / D converter to which the voltage comparison circuit according to this embodiment is applied. FIG. 13 shows one voltage in the flash A / D converter shown in FIG. It is a block diagram which shows a comparison circuit.

  In FIG. 12, reference numeral 400 indicates a resistance ladder, and 500 indicates an encoder. Here, a plurality of voltage comparison circuits 100 according to this embodiment are provided between the resistance ladder 400 and the encoder 500. The common-mode voltage is controlled in the foreground.

  Each voltage comparison circuit 100 includes a reference voltage from a connection node (tap) of adjacent resistors in a plurality of resistors connected in series between a high potential reference voltage Vrefp and a low potential reference voltage Vrefm, and an input analog signal. Vin is received and the output signal is output to the encoder 500.

  That is, as shown in FIG. 12, the flash A / D converter divides the reference voltages Vrefp to Vrefm by the resistor ladder 400 and applies them as comparison reference voltages of the voltage comparison circuits 100.

  Each voltage comparison circuit 100 compares the comparison reference voltage from the resistance ladder 400 with the analog signal Vin, and the comparison result (output signal) is input to the encoder 500. The encoder 500 outputs an output Dout obtained by digitally converting the analog signal Vin.

  As shown in FIG. 13, each voltage comparison circuit 100 includes a comparator 1, a determiner 2, a D / A converter (voltage controller) 3, capacitors Cp, Cm, and switches SW11, SW12, SW21, SW22. , SW31, SW32.

  In FIG. 13, the comparator 1 does not have switches corresponding to the transistors Tp12 and Tp15 in FIG. 2 described above, but it is needless to say that the comparator in FIG. 2 can be applied as it is.

  Here, for the common-mode voltage control process (determination process), for example, the process described with reference to FIG. 7 can be applied as it is. That is, in FIG. 13, first, Din = 0 and xCLK ′ = “H” are given to the D / A converter 3 to start the processing. The D / A converter 3 assumes positive logic.

  By setting xCLK ′ = “H”, the switches SW31 and SW32 are turned on, and the outputs of the D / A converter 3 are supplied to both inputs Vip and Vim of the comparator 1 without depending on the analog signal Vin. Given.

  Next, the clock CLK (corresponding to the clock φC) is applied in the same manner as in the normal mode, and the comparator 1 executes the determination. Here, the delay time is compared by the determiner 2 in the same manner as described with reference to FIG. The configuration of the determiner 2 is the same as that in FIG.

  Then, the result of the determiner 2 is given to the D / A converter 3 or the delay unit 25 in the determiner 2, and the process of FIG. If each voltage comparison circuit 100 is made to wait for the determination device 2 individually, all the voltage comparison circuits 100 can perform processing simultaneously in parallel, but the circuit scale increases.

  Therefore, for example, if the connection of one determination device 2 is switched and processing is performed for each voltage comparison circuit 100 (comparator 1), the circuit time can be suppressed although the processing time becomes longer. In any configuration, the common-mode voltage of each comparator is given an optimum point, which enables high-speed operation. Note that, after the calibration is completed, xCLK ′ can be given as a signal (xCLK) having an inverted level of CLK.

  FIG. 14 is a block diagram showing a second embodiment of the voltage comparison circuit. As apparent from the comparison between FIG. 14 and FIG. 3 described above, in the voltage comparison circuit 100 of the second embodiment, instead of the variable resistor Rd whose resistance value is controlled by the output signal of the D-MPX 24, a variable capacitor Cd is provided.

  That is, the inverters Tp25 and Tn25 that receive the clock φC are directly provided between Vdd and GND, and have a variable capacitance as a load between the node of the output signal V1 of the inverter input to the clock terminal CK of the FF 22 and GND. Cd is provided. The capacitance value of the variable capacitor Cd is controlled by the output signal of the D-MPX 24.

  Here, in the first embodiment of the voltage comparison circuit shown in FIG. 3, the resistance value of the variable resistor Rd is reduced in order to reduce the delay time, but in the voltage comparison circuit of the second embodiment, the delay time is reduced. Therefore, the capacitance value of the variable capacitor Cd is reduced.

  In the voltage comparison circuit of the second embodiment, the stepwise increase and decrease in the resistance value of the variable resistor Rd in the processing shown in FIGS. If it is replaced with a drop, it can be applied as it is. 3 and 4 are merely examples, and it goes without saying that various modifications are possible.

  As described above, since the common-mode voltage of the comparator can be automatically set to the optimum point by using the voltage comparison circuit or the A / D converter of the present embodiment, the variation in the elements at the time of manufacture, the power supply voltage, etc. It is also possible to compensate for environmental changes during operation such as temperature. As a result, stable operation can be realized. Further, since the number of semiconductor devices that do not satisfy the required performance due to the common-mode voltage is reduced, it is possible to contribute to the improvement of the yield.

  FIG. 15 is a block diagram showing an example of a semiconductor device to which an A / D converter using the voltage comparison circuit according to this embodiment is applied, and shows a digital TV tuner (communication system) 50.

  In FIG. 15, reference numeral 51 is an antenna, 52 is a high-frequency amplifier, 53a and 53b are mixers, 54 is a frequency synthesizer, 55a and 55b are low-pass filters, and 56a and 56b are low-frequency amplifiers. Reference numerals 57a and 57b denote A / D converters, and 58 denotes a digital block.

  As shown in FIG. 15, the digital TV tuner 50 receives radio waves by the antenna 51 and amplifies the signal amplitude to a level suitable for signal processing by the high frequency amplifier 52. The output signal of the high-frequency amplifier 52 is combined with the signal shifted by 90 degrees from the frequency synthesizer 54 in the mixers 53a and 53b to generate Ich and Qch signals.

  Further, the Ich and Qch signals generated by the mixers 53a and 53b are adjusted in conversion band (signal amplitude) and signal band by the low-pass filters 55a and 55b and the low-frequency amplifiers 56a and 56b, and the A / D converter 57a. , 57b.

  In the A / D converters 57 a and 57 b, the input analog signal is converted into a digital signal, and the digital signal is output to the digital block 58. In the digital block 58, predetermined processing is performed. For example, video and audio are output from a display device, a speaker, and the like.

  Here, as the A / D converters 57a and 57b used in FIG. 15, the successive approximation A / D converter shown in FIG. 9 or the flash A / D converter shown in FIG. It is various A / D converters which applied the voltage comparison circuit of an example.

  The preceding stage of the A / D converters 57a and 57b is an analog signal processing unit that processes an analog signal, and the subsequent stage of the A / D converters 57a and 57b is a digital signal processing unit (digital block 58).

  Further, the digital TV tuner shown in FIG. 15 is merely an example of a semiconductor device (system) to which the voltage comparison circuit or the A / D converter of the present embodiment is applied, and the present embodiment is applied to various semiconductor devices. It can be widely applied to.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A comparator;
A determiner for determining a response speed of the comparator;
A voltage controller that controls a common-mode voltage at a plurality of inputs of the comparator so as to reduce a delay in a response speed of the comparator according to a determination result of the determiner;
A voltage comparison circuit comprising:

(Appendix 2)
The determiner performs determination of the response speed of the comparator a plurality of times.
The voltage comparison circuit according to appendix 1, wherein:

(Appendix 3)
The determiner is
A response detector for detecting a response of the comparator;
A delay device for controlling a delay of the first control signal;
A loop processing circuit that controls the delay unit to reduce a time difference between the delayed first control signal and the detected response of the comparator, and performs a loop process for converging the common-mode voltage to an optimum value; ,
The voltage comparison circuit according to appendix 1 or appendix 2, characterized by comprising:

(Appendix 4)
The loop processing circuit terminates the loop processing when the common-mode voltage reaches the optimum value.
4. The voltage comparison circuit according to appendix 3, wherein

(Appendix 5)
The loop processing circuit continues the loop processing even after the common-mode voltage reaches the optimum value.
4. The voltage comparison circuit according to appendix 3, wherein

(Appendix 6)
The delay device includes an amplifier, and a variable resistor that controls a current flowing through the amplifier according to an output of the loop processing circuit,
The loop processing circuit controls the resistance value of the variable resistor to converge the common-mode voltage to an optimum value;
The voltage comparison circuit according to any one of Supplementary Note 3 to Supplementary Note 5, wherein

(Appendix 7)
The delay device includes an amplifier, and a variable capacitor that controls a load of the amplifier according to an output of the loop processing circuit,
The loop processing circuit controls a capacitance value of the variable capacitor to converge the common-mode voltage to an optimum value;
The voltage comparison circuit according to any one of Supplementary Note 3 to Supplementary Note 5, wherein

(Appendix 8)
The voltage controller is a D / A converter that controls the common-mode voltage applied to the input of the comparator according to a determination result of the determiner.
8. The voltage comparison circuit according to any one of appendix 1 to appendix 7, wherein:

(Appendix 9)
The voltage controller controls a common mode voltage at a differential input of the comparator;
9. The voltage comparison circuit according to any one of supplementary notes 1 to 8, wherein

(Appendix 10)
An A / D converter having the voltage comparison circuit according to any one of appendix 1 to appendix 9,
While the analog signal is sampled by the A / D converter, the comparator is operated to control the common-mode voltage.
An A / D converter characterized by the above.

(Appendix 11)
An A / D converter having the voltage comparison circuit according to any one of appendix 1 to appendix 9,
The comparator is operated to control the common-mode voltage after sampling is completed by the A / D converter and before a comparison operation for performing A / D conversion by the comparator is started. ,
An A / D converter characterized by the above.

(Appendix 12)
The A / D converter is a successive approximation A / D converter,
The comparator is a strong arm type comparator,
The A / D converter according to appendix 10 or appendix 11, characterized by the above.

(Appendix 13)
An analog signal processing unit for processing analog signals;
The A / D converter according to any one of appendix 10 to appendix 12, which converts an analog signal from the analog signal processing unit into a digital signal;
A digital signal processing unit for processing a digital signal from the A / D converter;
A semiconductor device comprising:

1 comparator (voltage comparator)
2 Judgment device 3 Voltage controller (D / A converter)
21 exclusive NOR (EXNOR) gate 22 flip-flop (FF)
23 Control circuit (CNTL: Up / Down Counter)
24 Demultiplexer (D-MPX)
25 Delay device 30p, 30m Capacitance circuit 50 Digital TV tuner (communication system)
DESCRIPTION OF SYMBOLS 51 Antenna 52 High frequency amplifier 53a, 53b Mixer 54 Frequency synthesizer 55a, 55b Low pass filter 56a, 56b Low frequency amplifier 57a, 57b A / D converter 58 Digital block 100 Voltage comparison circuit 200 Clock generator 300 SAR logic circuit 400 Resistance Ladder 500 encoder

Claims (5)

A comparator;
A determiner for determining a response speed of the comparator;
A voltage controller that controls a common-mode voltage at a plurality of inputs of the comparator so as to reduce a delay in a response speed of the comparator according to a determination result of the determiner;
A voltage comparison circuit comprising: The determiner is
A response detector for detecting a response of the comparator;
A delay device for controlling a delay of the first control signal;
Loop processing for controlling the delay device to reduce a time difference between the delayed first control signal and the detected response of the comparator, and for converging the common-mode voltage to an optimum value via the voltage controller. A loop processing circuit for performing
The voltage comparison circuit according to claim 1, comprising: An A / D converter having the voltage comparison circuit according to claim 1 or 2,
While the analog signal is sampled by the A / D converter, the comparator is operated to control the common-mode voltage.
An A / D converter characterized by the above. An A / D converter having the voltage comparison circuit according to claim 1 or 2,
The comparator is operated to control the common-mode voltage after sampling is completed by the A / D converter and before a comparison operation for performing A / D conversion by the comparator is started. ,
An A / D converter characterized by the above. An analog signal processing unit for processing analog signals;
The A / D converter according to claim 3 or 4, which converts an analog signal from the analog signal processing unit into a digital signal;
A digital signal processing unit for processing a digital signal from the A / D converter;
A semiconductor device comprising:

Images