JP5761120B2 - Microcomputer and electronic control unit - Google Patents

Description

  The present invention relates to a microcomputer provided with an AD conversion block, a digital processing block shared input terminal, and an electronic control device on which the microcomputer is mounted.

  For example, an electronic control unit (engine ECU) equipped with a microcomputer for engine control (hereinafter abbreviated as a microcomputer) drives various actuators such as an injector and an igniter. Fail-safe processing is performed according to Various types of abnormality detection techniques of this type are provided (see, for example, Patent Document 1).

  The technology described in Patent Document 1 includes a multiplexer having a plurality of analog inputs and an AD converter having a binary code output, and two multiplexer inputs serving as AD inputs are connected to a power supply voltage Vcc and a ground, respectively. And the output is input to the AD converter. As a result, the sticking of the bits “0” and “1” can be detected. With the technique described in Patent Document 1, an output abnormality of the AD converter can be detected.

  However, in the technique described in Patent Document 1, since the multiplexer selects a signal according to the control signal among the sensor signal input, the power supply voltage Vcc, and the ground, for example, the switch for selecting the power supply voltage Vcc is normal. In contrast to the operation, when an abnormality in switching to the signal input terminal occurs, an open (open) abnormality due to a switch failure of the multiplexer cannot be detected. Since the power supply voltage Vcc and the ground input terminal are required, the number of effective terminals usable for control is also reduced.

  The engine ECU also outputs on / off digital signals such as analog signals such as a water temperature sensor and an electronic throttle opening sensor, an ignition switch signal, and a shift range switch signal (P, R, D, N, 2, L, etc.). Although it is input, the number of analog signals and digital signals input differs depending on, for example, the vehicle type. Here, as for the microcomputer mounted in the engine ECU, the number of analog signal inputs and the number of digital signal inputs are generally determined for each microcomputer type. Therefore, when the number of analog or digital inputs is insufficient, it is necessary to change to another microcomputer having a large number of inputs, which leads to an increase in the cost of the microcomputer and the ECU.

JP-A-8-330959

  In view of this, the terminals for inputting analog signals and digital signals are partly used, and a multi-function dual-purpose terminal is being developed so that the same microcomputer can be used even if the vehicle types are different. Conventionally, there was a concern about the deterioration of the accuracy of analog signals when using both digital input terminals and analog input terminals. However, in recent microcomputers, as analog technology advances in semiconductor wafers, digital-analog input can be used. Terminals are also being installed.

  An object of the present invention is to provide a microcomputer capable of detecting an internal abnormality when an AD conversion block and an input terminal serving as a digital signal processing block of a digital signal processing block are provided, and an electronic control device equipped with the microcomputer There is to do.

  According to the first aspect of the present invention, it is pre-assigned that the analog / digital input terminal is either an analog signal input or a digital signal input. The AD conversion block inputs an analog signal through an analog / digital input terminal and performs digital conversion. The digital signal processing block inputs a digital signal through the analog / digital input terminal, compares the digital signal with the H / L discrimination threshold by the comparison means, and acquires the digital signal as the comparison result.

The estimation means, a predetermined input signal, the conversion result of the AD conversion block obtained in a state of being input to the AD conversion block through the analog digital Alternate input terminals, and, the same input signal and a predetermined input signal, the analog digital combined An abnormality of the AD conversion block or the digital signal processing block is estimated based on the processing result of the digital signal processing block obtained in the state of being input to the digital signal processing block through the input terminal . When there is a contradiction between the conversion result of the AD conversion block obtained using the same input signal and the processing result of the digital signal processing block, an abnormality of the AD conversion block or the digital signal processing block can be estimated.

  According to the invention of claim 2, when the conversion result of the AD conversion block is outside the normal output range and is a value on the non-operation side of the AD conversion block, the analog signal input is abnormal when the AD conversion block is not operating. You can see that it has been converted to the output range. Further, the estimation means hypothetically inputs the non-operating value of the AD conversion block to the comparison means and obtains a logical level that is a result of comparison with the H / L discrimination threshold, and this logical level is the digital signal processing block. It is estimated whether or not the relationship is inverse to the logic level of the digital signal.

  As an example, a case where an analog signal close to H level is input to the analog / digital input terminal will be described. When the changeover switch is operating normally, an analog signal is normally supplied from the analog / digital input terminal to the AD conversion block side. Therefore, the AD conversion block outputs a digital value corresponding to an analog signal close to H level. However, when the change-over switch is abnormally open, the analog signal from the analog / digital input terminal is not energized to the AD conversion block, so that the non-operating value (for example, the input initial value ≈ 0) is input to the AD conversion block. The

  On the other hand, since the comparison means directly inputs the input signal of the analog / digital input terminal, the comparison means outputs the H level compared with the H / L discrimination threshold as the logic level of the output digital signal of the digital signal processing block. The estimation means obtains the L level by obtaining a result of a hypothetical input of the AD conversion block non-operating value to the comparison means. Therefore, the estimation means compares the logical level (H level) of the output digital signal with the logical level (L level) obtained hypothetically, and these are in an inverse relationship, so that it is an abnormal opening of the changeover switch. Can be estimated. The same applies when the logic level is reversed, but the description is omitted.

  According to the third aspect of the present invention, the digital signal processing block is low even though the AD conversion result of the input signal of the digital / analog input terminal is equal to or higher than the minimum level (HH) that guarantees the high (H) output. L), it can be estimated that the digital signal processing block is malfunctioning. The reverse is also true, and the output of the digital signal processing block is high (H) even though the AD conversion result of the input signal of the digital / analog input terminal is below the maximum level (LL) that guarantees the low (L) output. ), It can be estimated that the digital signal processing block is malfunctioning.

  According to the fourth aspect of the present invention, when the AD conversion block is in an abnormal state, the AD conversion is performed for each of the plurality of channels even if the changeover switches of the plurality of channels are sequentially switched and the input signals of the plurality of channels are sequentially input. When the result becomes almost the same value, it can be estimated that the AD conversion block is abnormal.

  According to the fifth aspect of the present invention, if the AD conversion result deviates from the normal output range even though the AD conversion block is operating normally, the input circuit or the input signal source is abnormal. Can be estimated.

  According to the sixth aspect of the present invention, when the estimation means estimates that an abnormality has occurred in the digital signal processing block, the logic level is obtained using the AD conversion value of the AD conversion block. Even if an abnormality occurs, the processing can be continued using the AD conversion block.

  If the storage means for storing the estimated cause of abnormality in a non-volatile manner is provided as in the seventh aspect of the invention, the storage contents of the storage means can be used later when performing analysis processing.

1 is a block diagram schematically showing an electrical configuration according to an embodiment of the present invention. Block diagram showing the electrical configuration of the signal input part of the microcomputer (when the number of sensor signal inputs is large) Block diagram showing the electrical configuration of the signal input part of the microcomputer (when the number of switch signal inputs is large) Block diagram showing the electrical configuration of the signal input part of the microcomputer (when the number of sensor signals and switch signals input is the same) The figure which shows an example of the detailed circuit of the signal input part of the microcomputer Flow chart showing the overall processing flow Flowchart showing the flow of AD detection block abnormality detection processing Explanatory drawing of abnormality detection processing of AD conversion block Flowchart showing the flow of abnormality detection processing of the digital signal processing block Flow chart showing the flow of abnormality determination processing Explanatory diagram showing abnormality mode and abnormality detection contents (1) Explanatory drawing which shows abnormal mode and abnormal detection contents (the 2) Explanatory diagram showing abnormality mode and abnormality detection (Part 3) Explanatory drawing which shows abnormality mode and abnormality detection contents (the 4)

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the engine ECU 1 inputs sensor signals S of various sensors such as a water temperature sensor S1 and an electronic throttle opening sensor S2 through analog input terminals AIa, AIb..., An ignition switch SW1, and a shift position switch. Various switch signals SW such as SW2 are input through digital input terminals DIa, DIb. As the sensor signal S, signals from various sensors such as an accelerator pedal sensor, an intake air amount sensor, and an oil temperature sensor may be used. Further, as the switch signal SW, signals of various switches such as a starter switch, a brake switch, and an air conditioner switch may be used.

  The ignition switch SW1 indicates switching such as OFF (engine off) or ON (engine on). The shift position switch SW2 indicates a switching state of P (parking), R (reverse), D (drive), N (neutral), 2 (second), L (low), and the like.

  The engine ECU 1 includes a microcomputer (hereinafter referred to as a microcomputer) 2 and a peripheral I / O circuit of the microcomputer 2. The peripheral I / O circuit of the microcomputer 2 is an input circuit CINa for the sensor signal S, an input circuit CINb for the switch signal SW, buffer circuits B1 and B2, output drivers DR1 and DR2, and the like.

  The sensor signal S is input to the microcomputer 2 through the input circuit CINa. This microcomputer 2 incorporates a plurality of AD converters 3 and a port input circuit 4 and the like together with a normal CPU (estimating means) 100, and converts the AD conversion value of the AD converter 3 and the port input value of the port input circuit 4. Are used to perform arithmetic processing for engine control, execute injection, ignition, electronic throttle opening control, diagnosis processing, etc., and actuators such as injectors O1, O2 based on these arithmetic processing results and control processing results Drive.

  2 to 4 show detailed configuration examples of the signal input unit of the microcomputer. As shown in FIGS. 2 to 4, a bus 5 is configured in the microcomputer 2. A plurality of AD converters 3 and a plurality of port input circuits 4 are connected to the bus 5. For convenience of explanation, the plurality of AD converters 3 are respectively denoted by reference numerals 3a and 3b, and the plurality of port input circuits 4 are respectively denoted by reference numerals 4a to 4d and 4e to 4h.

  A multiplexer 6a is connected to the analog input of the AD converter 3a. The multiplexer 6a inputs the sensor signals Sa of the sensors S1 to S4 through the analog input terminals AI0 to AI3 and the input circuit, selects any one of these sensor signals Sa, and outputs it to the AD converter 3a. To do. The AD converter 3a AD converts this sensor signal.

  Each of the port input circuits 4a to 4d incorporates a port register (not shown), and inputs the switch signals SW of the switches SW1 to SW4 through the digital input terminals DI0 to DI3 and the input circuit, respectively. Compared with a comparator (described later), it is converted into a digital signal and held as a port input value.

  A multiplexer (equivalent to a changeover switch) 6b is connected to the analog input of the AD converter 3b. The multiplexer 6b receives any one of the sensor signals Sb when the sensor signals Sb of the sensors S5 to S8 are input through the analog input / output terminals ADI0 to ADI3 and the microcomputer input terminals ADIN0 to ADIN3 in the ECU connector. Is output to the AD converter 3b.

  The port input circuits 4e to 4h each have a built-in port register (see the boat registers 150 to 153 in FIG. 5), and input signals are input to the analog-purpose input terminals ADI0 to ADI3, respectively. The multiplexer 6b and the AD converter 3b constitute an AD conversion block AB, and the port input circuits 4e to 4h constitute a digital signal processing block DB.

  The microcomputer input terminals ADIN0 to ADIN3 are analog / digital input terminals capable of inputting both analog signals and digital signals. Either a sensor or a switch may be connected to the microcomputer input terminals ADIN0 to ADIN3. Therefore, as shown in FIG. 3, switches SW5 to SW8 may be connected to the microcomputer input terminals ADIN0 to ADIN3 instead of the sensors S5 to S6. When the switch signal SWb is input from these switches SW5 to SW8, the information of the switch signal SWb can be stored and held in the port registers 150 to 153 (see FIG. 5) of the port input circuits 4e to 4h.

  Also, as shown in FIG. 4, for example, sensors S5 and S6 and switches SW5 and SW6 may be connected. That is, by changing the assignment of the use of these microcomputer input terminals ADIN0 to ADIN3 for each vehicle type and each vehicle grade, for example, the sensors S5 to S8 or the switches SW5 to SW8 are used while the microcomputer 2 is shared among the corresponding types. You can select and connect.

  FIG. 5 shows a detailed circuit configuration example. The microcomputer input terminals ADIN0 to ADIN3 are connected to input protection circuits 70 to 73, respectively, in which diodes are combined. Analog switches 80 to 83 are connected to the subsequent stages of the input protection circuits 70 to 73, respectively.

  The multiplexer 6b shown in FIGS. 2 to 4 is configured by combining the analog switches 80 to 83, and the outputs of these analog switches 80 to 83 are commonly connected to each other. This common connection node is given to the buffer 10 through the parasitic capacitance 9. The parasitic capacitance 9 is a parasitic capacitance component generated in the analog switches 80 to 83 and the like, and is much smaller than the capacitor capacitance of the input circuit CINa illustrated in FIG.

  The output of the buffer 10 is given to the sample hold circuit 12 through the switch 11, and the AD converter 13 subjects the data held by the sample hold circuit 12 to AD conversion processing. An initialization switch 14 for discharging the accumulated charge is provided at both ends of the parasitic capacitor 9. In this embodiment, the parasitic capacitance 9 is generally initialized to the ground potential by the initialization switch 14. Note that the circuit configuration may be changed to be initialized to the potential on the power supply VDD side.

  Each of the port input circuits 4e to 4h includes comparators (comparison means) 140 to 143, and compares a signal input to the input terminals ADIN0 to ADIN3 with a threshold voltage Vth (for example, 1/2 of the power supply voltage VDD = 2.5V). These comparison data are held in the port registers 150 to 153, respectively. Further, the microcomputer 2 is equipped with AD abnormality counters 160 to 163 and port abnormality counters 170 to 173.

  The AD abnormality counters 160 to 163 are counters provided in advance for each of the channels ch10 to ch13 in order to count the state where the sensor signal S is not within the normal range. The port abnormality counters 170 to 173 are counters provided in advance for each of the channels ch10 to ch13 in order to count a state in which the switch signal SW cannot be normally detected. Here, an example of four channels is shown, but the same can be executed with 16 channels, and the number of channels is not limited to the contents of each embodiment.

  The operation will be described below. The CPU 100 executes a signal input process shown in FIG. 6 by using, for example, a 4 ms timer interrupt. At this time, in the microcomputer 2, the CPU 100 first reads values held in the port registers 150 to 153 of the port input circuits 4e to 4h (S1). Further, the AD converter 3b is used to acquire the AD conversion value of the analog signal input through the multiplexer 6b (S2). At this time, the input of the multiplexer 6b is switched, and the process is repeated until the AD conversion processing for all the inputs (AD10 to AD13) is completed (S3).

  Then, using this result, the CPU 100 performs application control using the abnormality detection process (part 1: S4), the abnormality detection process (part 2: S5), the abnormality estimation process (S6), the input port value, and the AD conversion value. Perform (S7). In this application control, injection, ignition, electronic throttle opening degree control, etc. are performed.

  In the abnormality detection process (No. 1) in step S4, the process shown in FIG. 7 is executed. The process shown in FIG. 7 is a process executed for each channel (ch10 to ch13). In this process, it is determined whether or not each channel has an abnormality.

  First, the CPU 100 checks whether the target channel ch1 * (* is any of 0 to 3) is assigned to an analog signal input or a digital signal input (T1). Note that this allocation state is determined in advance so as to change according to the engine system such as the vehicle type and grade as described above.

  When the microcomputer 2 determines that the channel ch1 * is assigned to the analog signal input (T1: YES), the analog conversion value of the analog input value is not less than a predetermined low threshold L and not higher than the high threshold H. It is determined whether or not the input range (T2). Here, if the low threshold L is set to a digital value corresponding to the analog input value 0.5V and the high threshold H is set to a digital value corresponding to the analog input value 4.5V, the sensor signal S is input normally. It can be determined whether or not the signal is in the range of 0.5V to 4.5V.

  The normal input range of the sensor signal S excludes a voltage range (for example, 4.51 V to 5 V) near the circuit operating power supply voltage (VDD) or a voltage range (for example, 0 to 0.49 V) near the ground (GND). Range (for example, 0.5 to 4.5 V). When the CPU 100 determines that it is within the normal input range (T2: YES), it clears the AD abnormality counter 16 * of the channel ch1 * (T3) and ends the abnormality detection process (part 1).

  When the microcomputer 2 determines that the value of the sensor signal S is not within the normal input range (T2: NO), the microcomputer 2 counts up the AD abnormality counter 16 * of the channel ch1 * (T4). Then, when the AD abnormality counter 16 * exceeds the abnormality determination value (for example, 10) (T5: YES), it is determined that some abnormality has occurred. Then, the CPU 100 performs an abnormality content determination process. First, it is determined whether or not the AD conversion value of the channel ch1 * is below the low threshold L and the port register value of the channel ch1 * is at the H level (T6).

  That is, in the circuit shown in FIG. 5, when the threshold voltage Vth to be compared by the comparator 14 * (* = 0 to 3) is set to 2.5V, the AD conversion value is 0.5V in the normal state. In some cases, the port register 15 * (* = 0 to 3) originally holds a digital value corresponding to the L level. However, if the AD register value is a digital value corresponding to less than 0.5 V, but the port register value of the channel ch1 * is a digital value corresponding to the H level, the analog switch 8 of the channel ch1 * It can be estimated that * (* = 0 to 3) has an open abnormality. Therefore, when the condition of step T6 is satisfied (T6: YES), the CPU 100 estimates that an open abnormality has occurred in the multiplexer 6b (particularly the analog switch 8 * of the channel ch1 *) (T7). At this time, the CPU 100 turns on the analog switch abnormality flag.

  Further, when the mutual maximum value (MAX value) −minimum value (MIN value) of the AD conversion values of all the channels ch10 to ch13 is less than a threshold D (for example, 0.5 V) (T8: YES), the AD conversion block It is estimated that there is an abnormality in the output side circuit (analog switch 8 * subsequent circuit: AD converter 3b) of AB (T9).

  When an abnormality occurs in the output side circuit of the AD conversion block AB, it may be caused by, for example, an internal abnormality of the buffer 10 shown in FIG. 5, a power supply short circuit abnormality, a ground short circuit abnormality, or a fixed bit of the AD conversion value storage register. In such a case, almost the same AD conversion value is often obtained for all channels ch10 to ch13, as shown in FIG. Therefore, it is determined whether or not the difference between the MAX value and the MIN value of these values is within a certain minute range (less than 0.5 V in the example shown in FIG. 8), and an abnormality occurs in the AD converter 3b and the like. It is good to judge whether or not.

  Here, the reason why the threshold value D is set to 0.5 V, for example, is that the threshold value D is often constant outside the normal input range such as a ground short circuit and a power supply short circuit, and a determination margin such as a power supply offset and a leakage current offset. Is set to 0.5 V based on this margin value. In step T8, when the condition is satisfied (T8: YES), it is estimated that the AD converter is abnormal (T9), and the AD output abnormality flag is turned on. On the other hand, when it is determined that the condition is not satisfied (T8: NO), it is estimated that the input circuit CIN * or the input signal source of the channel ch1 * is abnormal (T10), and the input circuit abnormality flag is turned on.

  The microcomputer 2 executes the abnormality detection process (part 2) after completing the abnormality detection process (part 1) in FIG. 7 (S5). In the abnormality detection process (part 2) shown in FIG. 9, the abnormality detection process of the port input circuits 4e to 4h is performed. The microcomputer 2 determines whether or not the channel ch1 * is assigned to the port input (U1), and when it is not assigned, the process exits.

  If the microcomputer 2 determines that the channel ch1 * is assigned to the port input, whether the AD conversion value of the channel ch1 * is higher than the high threshold HH (U2) and whether it is lower than the low threshold LL ( U3) is determined. For example, the high threshold HH is set to a digital value corresponding to 3.5V, and the low threshold LL is set to a digital value corresponding to 1.5V. These high threshold HH and low threshold LL are set based on the electrical characteristics of the DC specifications of the port input of the microcomputer 2. The high threshold value HH indicates the minimum value (MIN value) of the input voltage at which the port input (port register value) is always at the H level, and the low threshold value LL is the maximum value of input voltage at which the port input is always at the L level ( MAX value).

  If the microcomputer 2 determines that neither of the conditions of steps U2 and U3 is satisfied (NO in U2 and U3), the microcomputer 2 exits the process, but determines that the AD conversion value of the channel ch1 * exceeds the high threshold value HH, for example. (U2: YES), it is determined whether or not the holding level of the port register 15 * of the channel ch1 * is H level (U4). When the holding level of the port register 15 * is H level (U4: YES), the port abnormality counter 17 * is cleared (U5) and the process is exited.

  However, when the holding level of the port register 15 * is not H level (U4: NO), the port abnormality counter 17 * of the channel ch1 * is counted up (U6), and the port abnormality counter 17 * of the channel ch1 * is determined to be abnormal. When the value (for example, 10) is exceeded (U7: YES), it is determined (estimated) that the port input circuit of channel ch1 * is abnormal (U8), and the port input circuit abnormality flag is turned on.

  That is, under the condition that the channel ch1 * is assigned to the port input, when the AD conversion value exceeds the high threshold value HH, but the retained value of the port register 15 * is not H level, the port abnormality counter 17 * is When the count is incremented and the held value of the port abnormality counter 17 * exceeds the abnormality determination value, the port input circuit of the channel ch1 * is determined to be abnormal.

  On the other hand, the CPU 100 determines in step U3 whether or not the holding level of the port register 15 * of the channel ch1 * is L level. If the holding level of the port register 15 * is L level, the CPU 100 is operating normally. Judgment is made, the port abnormality counter 17 * is cleared (U10), and the process is exited. However, when the holding level of the port register 15 * is not the L level, the above-described steps U6 to U8 are performed.

  That is, when the channel ch1 * is assigned to the port input and the AD conversion value is lower than the low threshold LL, but the held value of the port register 15 * is not L level, the port abnormality counter 17 * is When the count is incremented and the held value of the port abnormality counter 17 * exceeds the abnormality determination value, the port input circuit of the channel ch1 * is determined to be abnormal.

  As shown in FIG. 6, after completing the abnormality detection process (part 2), the CPU 100 executes an abnormality determination process (S6). In the abnormality determination process shown in FIG. 10, the cause of the abnormality is determined, and an abnormality signal output and fail-safe process (or fail software process) corresponding to the determined abnormality cause is performed.

  The CPU 100 determines that the AD output abnormality flag is on due to an abnormality in the output side circuit of the AD conversion block AB, that is, the AD converter 3b (V1), or that the input circuit CIN * or the input signal source is abnormal. Whether the input circuit abnormality flag is on (V2), the multiplexer 6b (analog switch 8 *) is abnormal, the analog switch abnormality flag is on (V3), or the port input circuit is abnormal To determine whether the port input circuit abnormality flag is on (V4).

  The microcomputer 2 outputs an abnormality signal (diagnosis signal) due to diagnosis according to these abnormal contents (V5 to V8), and performs fail-safe processing or fail soft processing corresponding to these abnormal contents (V9 to V9). V12). When it is determined that there is an abnormality in the AD converter 3b, the sensor signal S cannot be input. Therefore, in step V9, a process for safely stopping the engine is executed.

  If the input circuit CIN * or input signal source is abnormal or the analog switch 8 * is abnormal, the channel CH1 * abnormal state (abnormality of the input circuit including the sensor and analog switch) is notified to the user. The processing is executed so as to perform engine control using the sensor signal S and the switch signal SW. When the corresponding channel ch1 * of the abnormal process is assigned to an important sensor such as the electronic throttle opening sensor S2, the process for shifting to a mode such as the evacuation travel mode and continuing the travel safely and stopping safely I do.

  On the other hand, when the port input circuit error flag is on (V4: YES) because an error has occurred in the port input circuit of channel ch1 * (V8: YES), the port is set on the output of the diagnosis signal (V8). Substitute processing is performed when the input circuit is abnormal (V12). That is, the AD conversion value of the corresponding channel ch1 * is compared with a digital value corresponding to 1/2 of the power supply voltage VDD (V12a), the logic level (H / L) is determined, and the port input value is substituted (V12b, V12c). ).

  That is, even if an abnormality occurs in the port input circuits 4e to 4h, the digital value can be acquired using the AD conversion value. In this case, since engine control can be continued as usual, the normal running control can be maintained by fail-softing without shifting to a mode such as the evacuation running mode.

  Such an abnormal mode and abnormality detection contents are summarized as shown in FIGS. FIG. 11 shows abnormal contents of the digital signal processing block DB (port input circuit). 12 and 13 show the abnormal contents of the AD conversion block AB. In particular, FIG. 12 shows abnormal output values under the conditions of the ground short of the multiplexer 6b (analog switch 8 *), the power supply short, and the input short of the operational amplifier 10. Indicates. FIG. 13 shows the details of the open abnormality of the multiplexer 6b (analog switch 8 *). FIG. 14 shows a detection state in the case of the power supply VDD short circuit and the ground GND short circuit before the microcomputer input terminals ADIN0 to ADIN3. If an abnormality is determined according to such a condition, it is possible to determine which part has an abnormality by referring to both the AD conversion value of the AD conversion block AB and the held value of the port register 15 *.

  According to the present embodiment, based on the conversion result of the AD conversion block AB and the processing result of the digital signal processing block DB obtained in a state where the same input signal is input to the input terminals ADIN0 to ADIN3, the AD conversion block AB or digital Abnormalities in the signal processing block DB can be estimated.

  In particular, when channel ch1 * is assigned to an analog signal input, the multiplexer 6b open error is provided on condition that the AD conversion value of channel ch1 * is below the low threshold L and the port register value of channel ch1 * is H. It is estimated that.

  Further, when channel ch1 * is assigned to an analog signal input, the multiplexer 6b (analog switch 8 *) is switched, and the conversion results of the AD conversion blocks AB of all the channel ch1 * are within the error range. It is estimated that the AD conversion block AB is abnormal.

  When channel ch1 * is assigned to an analog signal input, it can be determined that the AD conversion block AB is operating normally, and the conversion result of the AD conversion block AB deviates from the normal output range. The input circuit CIN * or the input signal source is estimated to be abnormal.

  When channel ch1 * is assigned to the digital signal input, the conversion result of the AD conversion block AB is equal to or higher than the high threshold value HH that guarantees the H output of the digital signal processing block DB, and the digital signal processing block DB It is estimated that the digital signal processing block DB is abnormal on the condition that the output is L level.

  When the channel ch1 * is assigned to the digital signal input, the conversion result of the AD conversion block AB is equal to or lower than the low threshold LL that guarantees the L output of the digital signal processing block DB, and the digital signal processing block DB It is estimated that the digital signal processing block DB is abnormal on the condition that the output is H. According to these processes, it can be determined in detail in which block the cause of the abnormality exists.

  Further, when channel ch1 * is assigned to a digital signal input, when it is estimated that an abnormality has occurred in the digital signal processing block DB, the logic level of the port input value is set using the AD conversion value of the AD conversion block AB. Fail software is processed by acquiring. Therefore, the process can be continued.

  Input signals that require control reliability (sensor signal S, switch signal SW) are not assigned to analog input dedicated terminals AI0 to AI3 and digital input dedicated terminals DI0 to DI3. Assign to ADIN3.

The engine ECU 1 or the like may be configured to include a nonvolatile memory (storage means) that stores the abnormal cause estimated and determined as described above in a nonvolatile manner. Then, for example, a dealer can easily analyze the cause of the abnormality later.
By switching the analog-purpose input terminals ADIN0 to ADIN3 for each vehicle type, the microcomputer 2 can be shared among a plurality of vehicle types, and the types of microcomputers 2 can be reduced.

  In the drawings, 1 is an engine ECU (electronic control unit), 2 is a microcomputer, 6b is a multiplexer (switch), 8 * (80 to 83) is an analog switch, 100 is a CPU (estimating means), 14 * (140 to 143) is a comparator (comparison means), AB is an AD conversion block, DB is a digital signal processing block, and ADIN0 to ADIN3 are analog / digital input terminals.

Claims (8)

An analog / digital input terminal pre-assigned to be either an analog signal input or a digital signal input;
An AD conversion block for inputting and converting an analog signal through the analog-purpose input terminal;
A digital signal processing block for obtaining a logic level as a comparison result of a comparison means for inputting a digital signal through the analog-purpose input terminal and comparing it with an H / L discrimination threshold;
A predetermined input signal, the analog digital Alternate input the conversion result of the AD conversion block obtained in a state of being input to the AD conversion block through the terminal, and, the same input signal and said predetermined input signal, the analog digital Alternate input An estimation unit for estimating an abnormality of the AD conversion block or the digital signal processing block based on a processing result of the digital signal processing block obtained in a state of being input to the digital signal processing block through a terminal. A microcomputer characterized by. When the analog-purpose input terminal is pre-assigned to be an analog signal input,
A switch for switching the energization of the input signal of the analog / digital input terminal to the AD conversion block side is provided, and the comparing means is configured to directly input the input signal of the analog / digital input terminal,
For the input signal of the analog / digital input terminal, the estimating means
The conversion result of the AD conversion block is outside the normal output range and is a value on the non-operating side of the AD conversion block, and the non-operating value of the AD conversion block is assumed to be input to the comparing means. On the condition that the logical level as a result of comparison with the H / L discrimination threshold is opposite to the output logical level of the digital signal processing block,
2. The microcomputer according to claim 1, wherein the microcomputer is estimated to be an open abnormality of the changeover switch. When the analog-purpose input terminal is pre-assigned to be a digital signal input,
For the input signal of the analog / digital input terminal, the estimating means
Whether the conversion result of the AD conversion block is equal to or higher than the minimum level (HH) that guarantees the high (H) output of the digital signal processing block, and the output of the digital signal processing block is low (L); Or
The conversion result of the AD conversion block is equal to or lower than the highest level (LL) that guarantees the low (L) output of the digital signal processing block, and the output of the digital signal processing block is high (H). Subject to
3. The microcomputer according to claim 1, wherein the microcomputer is estimated to be abnormal in the digital signal processing block. When the analog-purpose input terminal is pre-assigned to be an analog signal input,
When the AD conversion block is assigned to a plurality of channels, an analog switch for switching on / off the input signal of the analog / digital input terminal to the AD conversion block side is provided for each of the plurality of channels.
The estimation means is that the AD conversion block is abnormal on the condition that the conversion results of the AD conversion block are within an error range for all input signals by sequentially switching the analog switches of the plurality of channels. The microcomputer according to claim 1, wherein the microcomputer is estimated. When the analog-purpose input terminal is pre-assigned to be an analog signal input,
An input circuit for stabilizing and inputting the input signal of the analog-purpose input terminal;
The estimation means estimates that the AD conversion block is operating normally, and when the conversion result of the AD conversion block deviates from the normal output range of the analog signal, the input circuit or the input signal source The microcomputer according to claim 1, wherein the microcomputer is estimated to be abnormal. When the analog-purpose input terminal is pre-assigned to be a digital signal input,
The logic level is acquired using an AD conversion value of the AD conversion block when the estimation means estimates that an abnormality has occurred in the digital signal processing block. A microcomputer according to 1.   The microcomputer according to any one of claims 1 to 6, further comprising storage means for storing the cause of abnormality estimated by the estimation means in a nonvolatile manner.   An electronic control device comprising the microcomputer according to claim 1.

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