JP5758790B2 - STRESS TEST SYSTEM AND METHOD, STRESS TEST CONTROL DEVICE AND ITS CONTROL METHOD AND CONTROL PROGRAM, COOLING / HEATING DEVICE, AND TEST PROGRAM - Google Patents

Description

  The present invention relates to a stress test technique for an electronic circuit board that executes a program.

  In the above technical field, as disclosed in Patent Document 1, a technique for testing an IC device while measuring a temperature with a thermal diode provided inside the IC device is known. Patent Document 2 discloses that an IC chip mounted on a printed circuit board is heated or cooled to be controlled to a set temperature.

International Publication No. 2007/023557 Japanese Utility Model Publication No. 60-113568

  However, in the technique described in the above-mentioned document, a program is executed on the electronic circuit board while applying stress due to temperature on each IC chip mounted on the electronic circuit board, thereby causing troubles that are difficult to reproduce or intermittent failures. Could not be diagnosed.

  The objective of this invention is providing the technique which solves the above-mentioned subject.

In order to achieve the above object, a system according to the present invention provides:
An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip ,
A cooling and heating device for cooling and heating the IC chip;
The IC chip is controlled by the cooling / heating device so as to control the cooling / heating device based on temperature measurement by the temperature measuring element and to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. A stress test control device that monitors the operation of the electronic circuit board during program execution by the electronic circuit board while changing the temperature of the electronic circuit board;
It is characterized by providing.

In order to achieve the above object, the method according to the present invention comprises:
An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test method for performing a stress test on an electronic circuit board that executes a program using the IC chip ,
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And changing the temperature of the IC chip with the cooling and heating device,
Monitoring the operation of the electronic circuit board during program execution by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern;
It is characterized by providing.

In order to achieve the above object, an apparatus according to the present invention provides:
In the stress test system, a cooling and heating device for cooling and heating the IC chip,
A thermo module consisting of Peltier elements;
A copper heat conducting plate thermally coupled to the thermo module;
A copper attachment having a shape matched to the IC chip;
At least one heat pipe having one end thermally coupled to the heat conducting plate and the other end thermally coupled to the attachment;
Have
The thermo module absorbs heat and generates heat by a current corresponding to a pulse width modulated signal corresponding to a set temperature.
In order to achieve the above object, an apparatus according to the present invention provides:
An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test control device in a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip ,
Providing means for providing a program corresponding to the IC chip to be subjected to the stress test to the electronic circuit board;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control means for changing the temperature of the IC chip by the cooling and heating device,
Monitoring means for monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip by the temperature control means according to the predetermined temperature change pattern;
It is characterized by providing.

In order to achieve the above object, the method according to the present invention comprises:
An electronic circuit board on which an IC chip having a temperature measuring element is mounted , wherein the stress test system controls the electronic circuit board that executes a program using the IC chip. There,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step of changing the temperature of the IC chip by the cooling and heating device,
A monitoring step of monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
It is characterized by including.

In order to achieve the above object, a program according to the present invention provides:
An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a control program for a stress test control device in a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip There,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step of changing the temperature of the IC chip by the cooling and heating device,
A monitoring step of monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
Is executed by a computer.

In order to achieve the above object, a program according to the present invention provides:
A test program for causing the computer of the electronic circuit board to execute using the IC chip in the stress test system,
USB communication establishment step for establishing information exchange between the electronic circuit board and an external stress test control device by USB communication via the USB port of the electronic circuit board;
A temperature change pattern transmission step of transmitting a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test accompanying the test program to the stress test control device by the USB communication;
A measured temperature information transmission step of transmitting measured temperature information of the temperature measuring element to the stress test control device by the USB communication;
A test for executing a test of the electronic circuit board according to temperature control of the IC chip to be subjected to the stress test based on measured temperature information of the temperature measuring element according to the temperature change pattern by the stress test control device Steps,
An operation status transmission step of transmitting the operation status of the electronic circuit board to the stress test control device by the USB communication;
An error log storing step of storing an error log in an external storage device for testing via an external storage interface of the electronic circuit board when an error occurs;
Is executed by a computer of an electronic circuit board.

  According to the present invention, it is possible to diagnose a trouble that is difficult to reproduce or an intermittent trouble that occurs by causing the electronic circuit board to execute a program while applying stress due to temperature to each IC chip mounted on the electronic circuit board. it can.

1 is a block diagram showing a configuration of a stress test system according to a first embodiment of the present invention. It is a block diagram which shows the structure of the stress test system which concerns on 2nd Embodiment of this invention. It is a sequence diagram which shows the operation | movement procedure of the stress test system which concerns on 2nd Embodiment of this invention. It is a sequence diagram which shows the operation | movement procedure of the stress test system which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the function structure of the stress test control apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the active heat sink which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the PC motherboard which concerns on 2nd Embodiment of this invention. It is a figure which shows the 1st example of the temperature measurement of the IC chip which concerns on 2nd Embodiment of this invention. It is a figure which shows the 2nd example of the temperature measurement of the IC chip which concerns on 2nd Embodiment of this invention. It is a figure which shows the 3rd example of the temperature measurement of the IC chip which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the hardware constitutions of the stress test control apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the temperature / PW table which concerns on 2nd Embodiment of this invention. It is a figure which shows the result of selection of the OS / test program which concerns on 2nd Embodiment of this invention, and a stress test. It is a flowchart which shows the process sequence of the stress test control apparatus which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the initial temperature setting process which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the temperature stress test process which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the test program which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the stress test system which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the function structure of the stress test control apparatus which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the structure of the stress test system which concerns on 4th Embodiment of this invention. It is a block diagram which shows the function structure of the stress test control apparatus which concerns on 4th Embodiment of this invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in the following embodiments are merely examples, and are not intended to limit the technical scope of the present invention only to them.

[First Embodiment]
A stress test system 100 as a first embodiment of the present invention will be described with reference to FIG. The stress test system 100 is a system in which an IC chip 101 having a temperature measuring element 101a is mounted and a stress test is performed on an electronic circuit board 102 that executes a program.

  As shown in FIG. 1, the stress test system 100 includes a cooling and heating device 110 and a stress test control device 120. The cooling and heating device 110 cools and heats the IC chip 101. The stress test control device 120 controls the cooling and heating device 110 based on the temperature measurement by the temperature measuring element 101a, and follows the temperature change pattern 120a determined in advance corresponding to the IC chip 101 to be subjected to the stress test. The temperature of the chip 101 is changed. The operation of the electronic circuit board 102 during program execution is monitored while changing the temperature of the IC chip 101.

  According to the present embodiment, a program is executed on an electronic circuit board while applying stress due to temperature to each IC chip mounted on the electronic circuit board, and a trouble that is difficult to reproduce or an intermittent trouble is diagnosed. Can do.

[Second Embodiment]
Next, a stress test system according to the second embodiment of the present invention will be described. In the present embodiment, the active heat sink is controlled with respect to the IC chip on the PC mother board, and stress is applied by the temperature change pattern provided corresponding to the IC chip to be tested on an IC chip basis. Here, the active heat sink is a small cooling and heating device that can arbitrarily set the temperature in the range of about 0 to 70 ° C. Then, a test program corresponding to the IC chip to be tested is downloaded from the stress test control device to the PC mother board and executed to diagnose troubles that are difficult to reproduce or intermittent troubles occurring in the PC mother board. In the present embodiment, the failure of the PC motherboard is diagnosed, but the present invention can also be applied to a computer board that executes a similar program.

  Note that the PC motherboard used in this specification refers to an IC chip such as a CPU or memory that is mounted in each slot so that a program can be executed.

  According to the present embodiment, it is possible to automatically perform a long-time test by changing the temperature for each chip to be tested. Therefore, it is possible to reduce the number of man-hours while increasing the ability to detect intermittent faults resulting from a lack of margin due to a temperature change, which required a lot of man-hours until reproduction.

<Structure of stress test system>
FIG. 2 is a block diagram showing a configuration of the stress test system 200 according to the present embodiment.

  The stress test system 200 includes a stress test control device 210 that controls the stress test, and an active heat sink 220 that is a cooling and heating device that cools and heats the IC chip 241 mounted on the PC motherboard 240.

  The stress test control device 210 is connected to the active heat sink 220 by the connection cable 201 to control the temperature, and adjusts the temperature according to the temperature change pattern associated with the test program executed on the PC motherboard 240 corresponding to the IC chip 241. To do. Further, the stress test control device 210 exchanges information with the PC mother board 240 by USB communication through the USB cable 202 connected to the USB (Universal Serial Bus) port of the PC mother board 240 targeted for the stress test.

  An IC chip 242 is mounted on the PC mother board 240 in addition to the IC chip 241 targeted for the stress test. When performing a stress test of these IC chips, the active heat sink 220 is mounted on the IC chip. Then, a test program corresponding to the IC chip is executed under a corresponding temperature change pattern. In this embodiment, the IC chips 241 and 242 have built-in thermal diodes 241a and 242a for measuring the chip temperature.

  A power supply unit 250 for supplying power is connected to the PC motherboard 240 by a power cable 204. Further, a test HDD (Hard Disk Drive) 230 that is a test external storage device for storing an error log generated in the stress test is connected to the external storage interface of the PC motherboard 240 by an interface cable 203.

《Operation procedure of stress test system》
3A and 3B are sequence diagrams showing operation procedures 300-1 and 300-2 of the stress test system according to the present embodiment.

  First, in step S301, the copper attachment of the active heat sink 220 is attached to the IC chip 241 to be inspected on the PC motherboard 240 via a heat conductive sheet (see FIG. 5). If the adhesion between the copper attachment and the IC chip 241 is incomplete, for example, when the IC chip 241 is a heat generating system, the heat conduction is insufficient. For this reason, the IC chip 241 may be overheated due to defective heat exhaustion and the test temperature may be changed, and further, thermal destruction or the like may occur.

  Next, in step S <b> 303, the stress test control device 210 is connected to the power supply terminal of the active heat sink 220 with the connection cable 201. In step S 305, the test HDD 230 is connected to the PC motherboard 240 with the interface cable 203. In step S 307, the stress test control device 210 is connected to the USB port of the PC motherboard 240 with the USB cable 202. Note that the order of steps S301 to S307 is not limited to this.

  In step S311, an initial temperature is set in the stress test control device 210, and a start switch is turned on to supply power and activate the active heat sink 220. Since the operating temperature of the active heat sink 220 is obtained from the driving power and the waste heat temperature when there is no load, the set temperature is maintained until the start of the test by appropriately controlling. That is, the active heat sink 220 absorbs heat or generates heat according to a pulse width modulation (hereinafter, PWM: Pulse Width Modulation) signal from the stress test control device 210 in step S313. And the waste heat temperature signal which measured the temperature with the thermistor is returned to the stress test control apparatus 210. The stress test control apparatus 210 repeats steps S313 to S319 until the initial temperature is reached while displaying the heating temperature in step S317.

  On the other hand, when power is supplied to the PC motherboard 240 and the test HDD 230 in step S321, the CPU of the PC motherboard 240 executes BIOS (Basic Input / Output System). In step S325, the stress test control apparatus 210 connected by the USB cable 202 is requested to download the OS. In response to the OS download request, the OS held in the stress test control apparatus 210 is downloaded in step SD327, and the PC motherboard 240 starts executing the OS in step S329. When the activation of the OS is completed, a test program download is requested in step S331. In step S333, the stress test control apparatus 210 reads a test program corresponding to the IC chip to be inspected held in advance and downloads it to the PC motherboard 240 in step S335. In step S329, the downloaded test program is executed. First, in step S339, the test program establishes USB communication with the stress test control device 210 via the USB port, and in step S341, the test HDD 230 is initialized to be writable.

  When the test is started, first, in step S343, the PC mother board 240 sends temperature change pattern data to the stress test control device 210 via the USB port. The stress test control device 210 that has received the data sequentially changes the temperature according to the temperature change pattern after step S345, and the PC motherboard 240 executes the test program under each temperature.

  That is, first, in step S345, the first test temperature is set. In step S347, a PWM signal corresponding to the set test temperature is sent to the active heat sink 220. The temperature of the IC chip 241 to be inspected is measured by a built-in thermal diode, and the test program sends temperature information to the stress test control device 210 via the USB cable 202 in step S349. In step S351, the CPU waits for a temperature OK signal from the stress test control device 210. The stress test control apparatus 210 repeats steps S347 to S355 until the set test temperature is reached while displaying the temperature on the target IC chip 241 in step S353. When the set test temperature is reached, a temperature OK signal is sent to the PC motherboard 240 in step S357. By this temperature adjustment, the temperature of the IC chip 241 can be accurately grasped, so that there is no failure such as thermal breakdown or test temperature difference.

  The PC motherboard 240 executes the test program, and sends the current operation status to the stress test control device 210 in step S359. In step S361, the stress test control apparatus 210 stores the operation status information. When the test program running on the PC motherboard 240 detects an error due to a failure, the process proceeds from step S363 to S365, where the error log is transmitted to the test HDD 230, and stored in the test HDD 230 in step S367. At the same time, if USB communication is possible, in step S369, an error log is transmitted to the stress test control apparatus 210, and stored in the stress test control apparatus 210 in step S371. In step S373, the process waits for the end of the test program from the PC motherboard 240. If there is no notification of completion, the process returns to step S345 to change to the next temperature and continue the test.

  If no error is detected by the test program, the process advances from step S363 to S375 to determine whether or not the test is completed. If not completed, the process returns to step S349 to continue the test. If completed, in step S377, the test result is transmitted to the stress test control device 210 together with the test completion notification. When the test end notification is received, the stress test control apparatus 210 proceeds from step S373 to step S379, stores the test result, and displays the result in step S381. Here, the operation status and the error log may be displayed together.

  The stress test control device 210 that monitors the operation status of the PC motherboard 240 by USB communication records time and temperature in the error log as an operation error of the PC motherboard 240 when a communication abnormality due to a failure occurs. To do. In this way, even if the PC motherboard 240 stops due to a failure and an error log cannot be collected in the test HDD 230, the USB test abnormality is detected and the stress test control device 210 grasps the failure. Error logs can be collected.

<Functional configuration of stress test control device>
FIG. 4 is a block diagram showing a functional configuration of the stress test control apparatus 210 according to the present embodiment.

  As shown in FIG. 4, the stress test control apparatus 210 has a control unit 401 that controls the entire apparatus. Control unit 401 includes a CPU that performs arithmetic control, a ROM that stores fixed data or a program, and a temporary storage RAM. Further, it has an NVRAM (Non-volatile RAM) 402 for storing an OS 402a and a test program 402b supplied to the PC motherboard 240 and recording an error log. Further, it has a PWM control unit 403 that is connected to the active heat sink 220 by the connection cable 201 and controls the power to vary the temperature. Note that the connection cable 201 includes a line for transmitting a temperature signal from the thermistor 507 (see FIG. 5) to the control unit 401. In addition, a USB communication unit 404 that performs USB communication with the PC motherboard 240 via the USB cable 202 is provided. In addition, it has a temperature setting unit 405 for inputting initial temperature or test temperature settings. In addition, the display unit 406 displays an input set temperature, an operation determination result, and the like.

<Configuration of active heat sink>
FIG. 5 is a diagram showing a configuration of the active heat sink 220 according to the present embodiment.

  On both end faces of the thermo module 503 (Peltier element), copper heat conducting plates 502a and 502b having high thermal conductivity are mounted in a thermally coupled state. Copper heat radiating fins 501 are integrally formed on the heat conducting plate 502b. A cooling fan 508 driven by an electric motor is attached to the open end of the heat radiation fin 501. Further, one end of a heat pipe 504 is attached to the heat conducting plate 502a in a state where it is thermally coupled. The other end of the heat pipe 504 is attached in a state of being thermally coupled to the copper attachment 505. In FIG. 5, the heat pipe 504 is represented as a single bar, but in practice, a plurality of heat pipes are generally used due to the large amount of heat to be transported and the convenience in handling. There are several types of copper attachments 505 having different shapes according to the chip to be attached.

  Note that a heat conductive sheet 506 having high thermal conductivity using silicon or the like is attached to the chip side of the copper attachment 505 so as to be in close contact with an object so that air does not enter between them. This is because air has a very poor thermal conductivity and prevents heat conduction from the IC chip to be inspected, thereby preventing malfunction due to overheating due to defective exhaust heat. Further, a thermistor 507 for measuring the waste heat temperature of the thermo module 503 is attached to the heat conducting plate 502b in a thermally coupled state. As a result, the operating state of the active heat sink 220 can be grasped from the state of waste heat. If the exhaust heat cannot catch up due to overload and the temperature of the radiating fin 501 rises abnormally, this is immediately detected and tested. Discontinue. Therefore, it is possible to prevent the active heat sink 220 and the IC chip to be inspected from being thermally destroyed due to overheating.

<Configuration of PC motherboard>
FIG. 6A is a block diagram showing the configuration of the PC motherboard 240 according to this embodiment. Note that the configuration of FIG. 6A is an example, and the present invention is not limited to this.

  The PC motherboard 240 is mounted with a CPU 601 for arithmetic processing. It is desirable that the VIOS is built in the chip of the CPU 601. In addition, a memory 602 including a temporary storage RAM is mounted. Further, a chip set 603 for connecting the CPU 601 and various interfaces and controlling connected hardware, graphics, sound, and the like is mounted. Also, an IDE (Integrated Drive Electronics) port and a SATA (Serial Advanced Technology Attachment) port 604 for connecting a hard disk and an optical device are mounted. The test HDD 230 is connected here. In addition, USB, IEEE (Institute of Electrical and Electronics) 1394 (high-speed serial bus), LAN (Local Area Network), and audio port 605 are mounted. Here, the USB communication unit 404 of the stress test control apparatus 210 is connected by the USB cable 202. In addition, an I / O controller 606 to which a keyboard and a pointing device are connected is mounted. Further, a PCI (Peripheral Components Interconnect) bus 609 and PCI_Express 607 and 608 which are expansion buses are mounted. Further, there is a power connector (not shown), and various power supply voltages from the power supply unit 250 are supplied to the PC motherboard 240 by the power cable 204.

《IC chip temperature measurement》
Hereinafter, the temperature measurement configuration of the IC chip will be described with reference to FIGS. 6B to 6D.

(First example of IC chip temperature measurement)
FIG. 6B is a diagram showing a first example 610 of temperature measurement of the IC chip according to the present embodiment.

  In the first example 610, the collector incorporated in the IC chip 611 is grounded, and the temperature is reflected in the voltage VBE between the base and the emitter by the transistor 611a that uses the emitter and base as a thermal diode. Is output. The temperature calculation unit 612 calculates the temperature T according to the equation shown in correspondence with the difference in the voltage VBE. The calculated temperature T is sent from the USB port 605 by the CPU 601 and received by the USB communication unit 404 of the stress test control device 210 via the USB cable 202.

(Second example of IC chip temperature measurement)
FIG. 6C shows an IC chip temperature measurement configuration different from that in FIG. 6B. However, the principle is similar and the difference is where the temperature is calculated.

  In FIG. 6C, the IC chip 621 has a temperature calculation unit 621b, and the calculated temperature T is output from the IC chip 621. Note that the thermal diode in FIG. 6C is a diode in which the base and the collector of the transistor 621a are connected. The calculated temperature T is sent from the USB port 605 by the CPU 601 and received by the USB communication unit 404 of the stress test control device 210 via the USB cable 202.

(Third example of IC chip temperature measurement)
FIG. 6D shows an IC chip temperature measurement configuration different from those in FIGS. 6B and 6C. However, the principle is similar and the difference is where the temperature is calculated.

  6D, in the PC motherboard 240, VBE is detected by the potential difference detection unit 631, transmitted from the USB port 605 by the CPU 601, and received by the USB communication unit 404 of the stress test control device 210 via the USB cable 202. . The temperature T of the IC chip 611 is calculated by the control unit 401 of the stress test control device 210.

《Hardware configuration of stress test control device》
FIG. 7 is a block diagram showing a hardware configuration of the stress test control apparatus 210 according to the present embodiment.

  In FIG. 7, a CPU 710 is an arithmetic control processor, and implements each functional component of the stress test control device 210 of FIG. 4 by executing a program. The ROM 720 stores initial data and fixed data such as programs and programs. In addition, the USB communication unit 404 performs USB communication with the USB port 605 of the PC motherboard 240 via the USB cable 202.

  The RAM 740 is a random access memory that the CPU 710 uses as a work area for temporary storage. In the RAM 740, an area for storing data necessary for realizing the present embodiment is secured.

  741 is an APC model / motherboard type / IC chip type indicating a PC model or motherboard type to be subjected to a stress test, or a CPU type or an IC chip type to be inspected, and is used for selecting an OS and a test program. (See FIG. 9). Note that this data may be configured to be automatically read from a mother board or an IC chip, even if an operator inputs it from a keyboard or the like. Reference numeral 742 denotes an initial set temperature and a waste heat temperature detected by the thermistor 507, which are used to set the active heat sink 220 to an initial set temperature. Note that the initial set temperature may be automatically determined from the PC model / motherboard type / IC chip type 741 or the like, even if the operator inputs from the keyboard or the like. Reference numeral 743 denotes a test temperature change pattern for adjusting the temperature of the IC chip to be inspected, a potential difference (ΔVBE) from a thermal diode built in the IC chip, and the calculated IC chip temperature.

  Reference numeral 744 denotes a setting PW (Pulse Width) set by the PWM control unit 403 corresponding to the target temperature of the active heat sink 220 or the temperature of the IC chip (see FIG. 8). Reference numeral 745 denotes an operation state, an error log if transfer is possible, and a test result transferred from the PC motherboard running the test program via USB communication. Reference numeral 746 denotes USB reception data transferred from the PC motherboard by USB communication. On the other hand, 747 is USB transmission data transferred to the PC motherboard by USB communication. Reference numeral 748 denotes input data input via the input interface 760. Reference numeral 749 denotes display data displayed on the display unit 406 via the output interface 770.

  The storage 750 stores a database, various parameters, or the following data or programs necessary for realizing the present embodiment. Reference numeral 402a denotes an OS (OS-A, OS-B,...) Corresponding to a PC motherboard that can be tested by the stress test control apparatus 210 (see FIG. 4). Reference numeral 402b denotes a test program (test program a, test program b,...) Corresponding to an IC chip that can be tested by the stress test control apparatus 210. 751 is a temperature / PW table for determining the PW of the PWM control unit 403 from the target temperature (see FIG. 8). In addition, you may calculate in a control program instead of such a table. Reference numeral 752 denotes a potential difference-temperature conversion formula for calculating the temperature from the potential difference (ΔVBE) from the thermal diode built in the IC chip in the stress test control device 210 as shown in FIG. 6D. Reference numeral 753 denotes test results (test result a, test result b,...) Including an operation status and an error log. Each test result corresponds to a test program. In addition, a record of time and temperature when a communication abnormality occurs is also stored here.

  The storage 750 stores the following programs. In 754, a stress test control program for controlling the entire stress test control apparatus 210 is stored. 755 stores a temperature control module for controlling the temperature of the active heat sink 220 in the stress test control program 754. 756 stores a USB communication control module that controls USB communication with the PC motherboard in the stress test control program 754. 757 stores a display control module for controlling the display on the display unit 406 of the operator's internal settings, temperature, operation status, error log, test results, etc. in the stress test control program 754.

  The input interface 760 interfaces input data from an input device or the like. The connection cable 201 from the active heat sink 220 is connected to the input interface 760, and temperature information is input from the thermistor 507. Further, a keyboard 761 for inputting operator instructions and data is connected. Further, a pointing device 762 for instructing on the display screen of the display unit 406 is connected.

  The output interface 770 interfaces output data to an output device or the like. A display unit 406 is connected to the output interface 770. Also, a PWM control unit 403 is connected to control the temperature of the active heat sink 220 via the connection cable 201.

  FIG. 7 shows only data and programs essential to the present embodiment, and does not illustrate data and programs not related to the present embodiment.

(Temperature / PW table)
FIG. 8 is a diagram showing a configuration of the temperature / PW table 751 according to the present embodiment. The configuration is not limited to that shown in FIG.

  The temperature / PW table 751 stores a setting PW 804 to be sent from the PWM control unit 403 to the active heat sink 220 in association with the setting temperature 801, the detection temperature 802, and the temperature difference 803 (= setting temperature−detection temperature). .

  At the initial temperature setting, the set temperature 801 is the initial set temperature, and the detected temperature 802 is the detected temperature of the thermistor 507. On the other hand, when setting the test temperature, the set temperature 801 is the set test temperature, and the detected temperature 802 is the detected temperature of the IC chip calculated from the potential difference of the thermal diode built in the IC chip to be inspected.

(OS / test program selection and stress test results)
FIG. 9 is a diagram showing a result 900 of the OS / test program selection and the stress test according to the present embodiment. Note that each piece of data shown in FIG. 9 is a collection of data over a plurality of areas of the RAM 740 in FIG. 7 and does not have to be in the format as shown in FIG.

  Each data is stored in the OS / test program selection and stress test result 900 in association with a test ID 901 for identifying each test. First, the OS 903 used in association with the PC model / motherboard type 902 to be tested is stored. In addition, a test program 905 and a test temperature change pattern 906 used in association with the test target IC chip 904 are stored. Note that the test temperature change pattern 906 may be embedded in the test program 905. In addition, an operation state 907, an error log 908, and a test result 909 in the stress test are stored.

  This data can be stored in a stress test database and used for error statistics and analysis. Such error statistics and analysis can be used to improve test programs and test temperature change patterns, and also to motherboard design.

<Processing procedure of stress test control device>
FIG. 10A is a flowchart showing a processing procedure of the stress test control apparatus 210 according to the present embodiment. This flowchart is executed by the CPU 710 in FIG. 7 while using the RAM 740, and implements each functional component in FIG.

  First, in step S1011, an initial temperature setting process using the active heat sink 220 as an initial temperature is executed (refer to FIG. 10B for details).

  When the initial temperature setting process is completed and the initial temperature is reached, an OS request from the PC motherboard 240 is awaited in step S1013. As described above, the OS request from the PC motherboard 240 is made via the USB cable 202 after power is supplied to the PC motherboard 240 and the BIOS is activated and the test of each connection circuit is completed. When the OS request is received from the PC motherboard 240, the process proceeds to step S1015, and an appropriate OS is selected based on the type of the PC motherboard 240, the installed CPU type, and the like. Then, the selected OS is read from the NVRAM 402 and downloaded to the PC motherboard 240.

  Next, in step S1017, a test program request from the PC motherboard 240 is awaited. As described above, the test program request from the PC motherboard 240 is made via the USB cable 202 when the activation of the OS on the PC motherboard 240 is completed. When the test program request is received from the PC motherboard 240, the process proceeds to step S1019, and the test program selected corresponding to the IC chip to be inspected is read from the NVRAM 402 and downloaded to the PC motherboard 240. This test program includes an associated test temperature change pattern.

  In step S1021, it is determined whether USB communication has been established with the PC motherboard 240. USB communication is established with each other during the execution of the test program by the PC motherboard 240 (see FIG. 11). If the USB communication is established, the process proceeds to step S1023 to perform a stress test process based on temperature (refer to FIG. 10C for details). If USB communication is not established, the process proceeds to step S1025 to notify a USB communication error. In step S1027, the test result including the error information is displayed on the display unit 406.

(Initial temperature setting process)
FIG. 10B is a flowchart showing a processing procedure of the initial temperature setting processing S1011 according to the present embodiment.

First, in step S1031, the initial temperature of the active heat sink 220 is set. The temperature setting may be performed manually by the operator or automatically by the stress test control device 210. Next, in step S1033,
Wait for the start button to be pressed (or turn on the start switch).

  When the start button is pressed, the process proceeds to step S1035, and the active heat sink 220 is activated by supplying a PWM-controlled drive current to the thermo module 503. In step S1037, power supplied to the active heat sink 220 is acquired, and in step S1039, the waste heat temperature detected by the thermistor 507 is received. In step S1941, the operating temperature of the thermo module 503 is calculated, and the operating temperature calculated in step S1043 is displayed.

  In step S1045, it is determined whether the thermo module 503 has reached the initial set temperature. If it is not the initial set temperature, the process returns to step S1035 to repeat the PWM control and the calculation of the operating temperature of the thermo module 503. Return to the initial set temperature and keep the initial set temperature until the test starts.

(Temperature stress test process)
FIG. 10C is a flowchart showing a processing procedure of the temperature stress test processing S1023 according to the present embodiment.

  First, it waits for reception of a test temperature change pattern from a test program running on the PC motherboard 240. If the test temperature change pattern is received, the process proceeds to step S1053, and the test temperature change pattern is stored. In step S1055, the set temperature for PWM control for the thermo module 503 is set to the initial IC chip temperature.

  In step S1057, the drive power from the PWM control unit 403 to the active heat sink 220 is controlled to change the temperature. In step S1059, it waits for reception of temperature information of the IC chip measured by the thermal diode disposed inside the IC chip to be inspected. This temperature information is read by the temperature measurement routine in the test program and sent to the stress test control device 210 via the USB. In step S1061, the IC chip temperature is calculated. The calculation of the IC chip temperature may be performed by either the PC motherboard 240 or the stress test control device 210 as shown in FIGS. 6B to 6D. In step S1063, the calculated IC chip temperature is compared with the set test temperature to determine whether they match. If they do not match, the process returns to step S1057, and the PWM control unit 403 appropriately controls the temperature of the active heat sink 220. By this control, the temperature of the IC chip to be inspected can be accurately controlled, so that there is no failure such as thermal destruction and test temperature difference.

  If the set IC chip temperature is reached, the process proceeds to step S1065 to notify the PC motherboard 240 that the IC chip temperature is OK. Since the set IC chip temperature is executed in the PC mother board 240, in step S1067, it is determined whether or not an operation state or a test error is received from the PC mother board 240. If an operation status or a test error is received, the process proceeds to step S1069, and the received operation status or test error is stored in the NVRAM 402 or the like. If no operation status or test error is received, the process proceeds to step S2071.

  In step S1071, it is determined whether the end of the test program has been received. If not completed, the process proceeds to step S1073, and it is determined whether or not the waste heat temperature, which is the temperature detected by the thermo module 503 from the thermistor 507, exceeds a predetermined threshold Th. If not, the process returns to step S1055, the next temperature of the test temperature change pattern is set to the IC chip temperature, and steps S1055 to S1073 are repeated. When the waste heat temperature of the thermo module 503 from the thermistor 507 exceeds a predetermined threshold value Th, the test is stopped and the active heat sink 220 is stopped in step S1075, and the waste heat temperature and time are stored as an error log. To do.

  In step S1077, the test result is received and the process returns. In receiving the test result, for example, if the test program ends normally, the test result stored in the test HDD 230 is received from the PC motherboard 240. If the test program is interrupted, the test HDD 230 receives the status of the PC motherboard 240 if the test HDD 230 can read the test program. If the test is canceled due to a failure of the PC motherboard 240 or a USB communication failure, the stress test control device 210 records the time and temperature when the failure occurred as an error log in the NVRAM 402. With this process, even if the PC motherboard 240 stops due to a failure and a log cannot be collected in the test HDD 230, an error log is collected because the stress test control device 210 recognizes the failure status by detecting an abnormality in USB communication. Is possible.

《Test program processing procedure》
FIG. 11 is a flowchart showing the processing procedure of the test program according to the present embodiment. This flowchart is executed using the memory 602 by the CPU 601 in FIG. 6A.

  First, USB communication with the stress test control device 210 is established at step S1101 at the beginning of the test program. If the USB communication is established, the test HDD 230 is initialized in step S1103. Next, in step S1105, a temperature change pattern transmission process for transmitting the test temperature change pattern to the stress test control device 210 by USB communication is executed. As shown in FIG. 10C, the stress test control device 210 receives the test temperature change pattern and controls the thermo module 503 to adjust the temperature of the IC chip.

  In step S1107, the temperature information of the target IC chip is acquired from the thermal diode 241a built in the IC chip. Then, in step S1109, a measured temperature information transmission process for transmitting the acquired measured temperature information of the IC chip to the stress test control device 210 is executed. Here, the temperature calculation is described as being performed by the stress test control device 210. However, as shown in FIG. 6B or 6C, the temperature calculation may be performed by the PC motherboard 240 or the IC chip. Good. In step S1111, the reception of a temperature OK signal, which is a notification that the temperature of the IC chip matches the set temperature, from the stress test control device 210 is awaited. If no temperature OK signal is received, the process returns to step S1107 to repeat the IC chip temperature measurement and temperature information transmission.

  If the temperature OK signal is received, the process proceeds to step S1113 to execute a stress test. Then, in step S1115, an operation status transmission process for transmitting the operation status to the stress test control device 210 is executed. In step S1117, it is determined whether there is a test error. If there is a test error, an error log saving process for saving the error log in the test HDD 230 is executed in step S1119. At the same time, if possible, it is transmitted to the stress test control device 210. If there is no test error, the process proceeds to step S1121 to determine the end of the test program. If it is not the end of the test program, the process returns to step S1107 and steps S1107 to S1121 are repeated. If the test program has been completed, the test result including the error log stored in the test HDD 230 is reported to the stress test control device 210 in step S1123.

  In the flowchart of FIG. 11, if a failure occurs in the PC motherboard 240 during the stress test, there is a possibility of stopping or running out of control. In that case, the stress test control device 210 can know the failure in the PC motherboard 240 by detecting the interruption or failure of the USB communication.

[Third Embodiment]
Next, a stress test system according to the third embodiment of the present invention will be described. The stress test system according to the present embodiment is different from the second embodiment in that the stress test control apparatus includes a test HDD and a power supply unit. Since other configurations and operations are the same as those of the second embodiment, the same configurations and operations are denoted by the same reference numerals, and detailed description thereof is omitted.

  According to this embodiment, it is possible to execute a stress test on a PC motherboard that combines power source stress with a simple operation simply by connecting a stress test control device.

<Structure of stress test system>
FIG. 12 is a block diagram showing a configuration of the stress test system 1200 according to the present embodiment. In addition, the part which fulfill | performs the function similar to FIG. 2 of 2nd Embodiment attaches | subjects the same reference number, and abbreviate | omits description.

  In FIG. 12, a test HDD 1230 and a power supply unit 1250 are mounted on a stress test control device 1210, so that the stress test control device 1210 can perform not only thermal stress but also power supply stress. The test HDD 1230 is connected to the PC motherboard 240 by an interface cable 1203. The power supply unit 1250 is connected to the PC motherboard 240 by a power cable 1204.

<Functional configuration of stress test control device>
FIG. 13 is a block diagram showing a functional configuration of the stress test control apparatus 1210 according to the present embodiment. In addition, the part which fulfill | performs the function similar to FIG. 4 of 2nd Embodiment attaches | subjects the same reference number, and abbreviate | omits description.

  In FIG. 13, a test HDD 1230 and a power supply unit 1250 are newly mounted on the stress test control device 1210. The test HDD 1230 is connected to the PC motherboard 240 by an interface cable 1203. The power supply unit 1250 is connected to the PC motherboard 240 by a power cable 1204.

  Note that the test HDD 1230 and the power supply unit 1250 are not dedicated to the PC motherboard 240 and may be shared by the stress test control device 1210 as its own storage medium or power supply.

[Fourth Embodiment]
Next, a stress test system according to the fourth embodiment of the present invention will be described. The stress test system according to the present embodiment differs from the second embodiment in that the stress test control device controls the active heat sink to be automatically mounted on the IC chip to be tested. Since other configurations and operations are the same as those of the second embodiment, the same configurations and operations are denoted by the same reference numerals, and detailed description thereof is omitted.

  According to this embodiment, the mounting of the active heat sink to the IC chip to be tested can be realized without human operation.

<Structure of stress test system>
FIG. 14 is a block diagram showing a configuration of a stress test system 1400 according to the present embodiment. In addition, the part which fulfill | performs the function similar to FIG. 2 of 2nd Embodiment attaches | subjects the same reference number, and abbreviate | omits description.

  The active heat sink 1420 in FIG. 14 has a configuration that can move in the horizontal direction (X-axis direction) of the PC motherboard 240 and a configuration 1409 that can move in the vertical direction (Y-axis direction). The shape and position of the configuration 1409 are not limited. The stress test control device 1410 controls the position of the active heat sink 1420 on the PC mother board 240 with a set of (X coordinate, Y coordinate), and attaches the active heat sink 1420 to the IC chip to be inspected. Such control is performed via a control cable 1405 from the stress test controller 1410 to the active heat sink 1420.

<Functional configuration of stress test control device>
FIG. 15 is a block diagram showing a functional configuration of the stress test control apparatus 1410 according to the present embodiment. In addition, the part which fulfill | performs the function similar to FIG. 4 of 2nd Embodiment attaches | subjects the same reference number, and abbreviate | omits description.

  In the stress test control device 1410 of FIG. 15, an IC chip position coordinate 1502c is added to the active heat sink mounting control unit 1505 and the NVRAM 1502. The active heat sink mounting control unit 1505 reads the arrangement of the IC chip to be inspected on the PC motherboard from the IC chip position coordinates 1502c, and controls the active heat sink 1420 via the control cable 1405 so that the active heat sink 1420 moves to the coordinates.

[Other Embodiments]
Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, a system or an apparatus in which different features included in each embodiment are combined in any way is also included in the scope of the present invention.

  In addition, the present invention may be applied to a system composed of a plurality of devices, or may be applied to a single device. Furthermore, the present invention can also be applied to a case where an information processing program that implements the functions of the embodiments is supplied directly or remotely to a system or apparatus. Therefore, in order to realize the functions of the present invention on a computer, a control program installed in the computer, a medium storing the control program, and a WWW (World Wide Web) server that downloads the control program are also included in the scope of the present invention. include.

[Other expressions of embodiment]
A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
An IC chip having a temperature measuring element is mounted, and a stress test system that performs a stress test on an electronic circuit board that executes a program,
A cooling and heating device for cooling and heating the IC chip;
While controlling the cooling and heating device based on the temperature measurement by the temperature measuring element and changing the temperature of the IC chip so as to follow a predetermined temperature change pattern corresponding to the IC chip subject to the stress test A stress test control device for monitoring the operation of the electronic circuit board during program execution;
A stress test system comprising:
(Appendix 2)
The cooling heating device
A thermo module consisting of Peltier elements;
A copper heat conducting plate thermally coupled to the thermo module;
A copper attachment having a shape matched to the IC chip;
At least one heat pipe having one end thermally coupled to the heat conducting plate and the other end thermally coupled to the attachment;
Have
2. The stress test system according to claim 1, wherein the thermo module absorbs heat and generates heat by a current corresponding to a signal from the stress test control device, which is pulse-width modulated in accordance with a set temperature.
(Appendix 3)
The cooling and heating device further includes a thermistor that measures the temperature of the thermo module,
The stress test system according to claim 2, wherein the stress test control device stops the stress test when a temperature of the thermo module exceeds a predetermined threshold.

(Appendix 4)
4. The stress test system according to any one of appendices 1 to 3, wherein the temperature measuring element is a thermal diode arranged inside the IC chip.
(Appendix 5)
The program executed during the stress test by the electronic circuit board is a test program corresponding to the IC chip to be subjected to the stress test downloaded from the stress test control device to the electronic circuit board,
The stress test system according to any one of appendices 1 to 4, wherein the temperature change pattern is provided in association with the test program.
(Appendix 6)
Information exchange between the electronic circuit board and the stress test control device is executed by USB communication via a USB port of the electronic circuit board,
6. The stress test system according to any one of appendices 1 to 5, wherein an external storage device for storing test results is connected to the external storage interface of the electronic circuit board.
(Appendix 7)
An IC chip having a temperature measuring element is mounted, and a stress test method for performing a stress test on an electronic circuit board that executes a program,
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. Changing the temperature of the IC chip to:
Monitoring the operation of the electronic circuit board during program execution while changing the temperature of the IC chip according to the predetermined temperature change pattern;
A stress test method comprising:
(Appendix 8)
In a stress test system in which an IC chip having a temperature measuring element is mounted and a stress test is performed on an electronic circuit board that executes a program, a cooling and heating device that cools and heats the IC chip,
A thermo module consisting of Peltier elements;
A copper heat conducting plate thermally coupled to the thermo module;
A copper attachment having a shape matched to the IC chip;
At least one heat pipe having one end thermally coupled to the heat conducting plate and the other end thermally coupled to the attachment;
Have
A cooling and heating apparatus, wherein the thermo module absorbs heat and generates heat by a current corresponding to a pulse width modulated signal corresponding to a set temperature.
(Appendix 9)
A stress test control device in a stress test system in which an IC chip having a temperature measuring element is mounted and a stress test is performed on an electronic circuit board that executes a program,
Providing means for providing a program corresponding to the IC chip to be subjected to the stress test to the electronic circuit board;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. Temperature control means for changing the temperature of the IC chip,
Monitoring means for monitoring the operation at the time of execution of the provided program by the electronic circuit board while changing the temperature of the IC chip by the temperature control means in accordance with the predetermined temperature change pattern;
A stress test control device comprising:
(Appendix 10)
A control method of a stress test control device in a stress test system in which an IC chip having a temperature measuring element is mounted and a stress test is performed on an electronic circuit board that executes a program,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step for changing the temperature of the IC chip,
A monitoring step of monitoring an operation at the time of execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
A control method for a stress test control device, comprising:
(Appendix 11)
A control program for a stress test control device in a stress test system in which an IC chip having a temperature measuring element is mounted and a stress test is performed on an electronic circuit board that executes the program,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step for changing the temperature of the IC chip,
A monitoring step of monitoring an operation at the time of execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
A control program for causing a computer to execute.
(Appendix 12)
A test program to be executed by a computer of the electronic circuit board in a stress test system in which an IC chip having a temperature measuring element is mounted and a stress test is performed on the electronic circuit board executing the program,
USB communication establishment step for establishing information exchange between the electronic circuit board and an external stress test control device by USB communication via the USB port of the electronic circuit board;
A temperature change pattern transmission step of transmitting a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test accompanying the test program to the stress test control device by the USB communication;
A measured temperature information transmission step of transmitting measured temperature information of the temperature measuring element to the stress test control device by the USB communication;
A test for executing a test of the electronic circuit board according to temperature control of the IC chip to be subjected to the stress test based on measured temperature information of the temperature measuring element according to the temperature change pattern by the stress test control device Steps,
An operation status transmission step of transmitting the operation status of the electronic circuit board to the stress test control device by the USB communication;
An error log storing step of storing an error log in an external storage device for testing via an external storage interface of the electronic circuit board when an error occurs;
Is executed by a computer of an electronic circuit board.

Claims (10)

An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip ,
A cooling and heating device for cooling and heating the IC chip;
The IC chip is controlled by the cooling / heating device so as to control the cooling / heating device based on temperature measurement by the temperature measuring element and to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. A stress test control device that monitors the operation of the electronic circuit board during program execution by the electronic circuit board while changing the temperature of the electronic circuit board;
A stress test system comprising: The cooling heating device
A thermo module consisting of Peltier elements;
A copper heat conducting plate thermally coupled to the thermo module;
A copper attachment having a shape matched to the IC chip;
At least one heat pipe having one end thermally coupled to the heat conducting plate and the other end thermally coupled to the attachment;
Have
2. The stress test system according to claim 1, wherein the thermo module absorbs heat and generates heat by a current corresponding to a signal from the stress test control device that is pulse-width modulated in accordance with a set temperature. The cooling and heating device further includes a thermistor that measures the temperature of the thermo module,
The stress test system according to claim 2, wherein the stress test control device stops the stress test when a temperature of the thermo module exceeds a predetermined threshold. The program executed during the stress test by the electronic circuit board is a test program corresponding to the IC chip to be subjected to the stress test downloaded from the stress test control device to the electronic circuit board,
The stress test system according to claim 1, wherein the temperature change pattern is provided in association with the test program. An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test method for performing a stress test on an electronic circuit board that executes a program using the IC chip ,
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And changing the temperature of the IC chip with the cooling and heating device,
Monitoring the operation of the electronic circuit board during program execution by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern;
A stress test method comprising: The stress test system according to any one of claims 1 to 4, wherein the IC chip is a cooling and heating device that cools and heats the IC chip.
A thermo module consisting of Peltier elements;
A copper heat conducting plate thermally coupled to the thermo module;
A copper attachment having a shape matched to the IC chip;
At least one heat pipe having one end thermally coupled to the heat conducting plate and the other end thermally coupled to the attachment;
Have
A cooling and heating apparatus, wherein the thermo module absorbs heat and generates heat by a current corresponding to a pulse width modulated signal corresponding to a set temperature. An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a stress test control device in a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip ,
Providing means for providing a program corresponding to the IC chip to be subjected to the stress test to the electronic circuit board;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control means for changing the temperature of the IC chip by the cooling and heating device,
Monitoring means for monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip by the temperature control means according to the predetermined temperature change pattern;
A stress test control device comprising: An electronic circuit board on which an IC chip having a temperature measuring element is mounted , wherein the stress test system controls the electronic circuit board that executes a program using the IC chip. There,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step of changing the temperature of the IC chip by the cooling and heating device,
A monitoring step of monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
A control method for a stress test control device, comprising: An electronic circuit board on which an IC chip having a temperature measuring element is mounted, and a control program for a stress test control device in a stress test system that performs a stress test on an electronic circuit board that executes a program using the IC chip. There,
Providing the electronic circuit board with a program corresponding to the IC chip to be subjected to the stress test;
A cooling and heating device that cools and heats the IC chip based on the temperature measurement by the temperature measuring element is controlled so as to follow a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test. And a temperature control step of changing the temperature of the IC chip by the cooling and heating device,
A monitoring step of monitoring the operation of the electronic circuit board during execution of the provided program by the electronic circuit board while changing the temperature of the IC chip according to the predetermined temperature change pattern in the temperature control step;
A control program for causing a computer to execute. The test program according to any one of claims 1 to 4, wherein the test program is executed by a computer of the electronic circuit board using the IC chip .
USB communication establishment step for establishing information exchange between the electronic circuit board and an external stress test control device by USB communication via the USB port of the electronic circuit board;
A temperature change pattern transmission step of transmitting a predetermined temperature change pattern corresponding to the IC chip to be subjected to the stress test accompanying the test program to the stress test control device by the USB communication;
A measured temperature information transmission step of transmitting measured temperature information of the temperature measuring element to the stress test control device by the USB communication;
A test for executing a test of the electronic circuit board according to temperature control of the IC chip to be subjected to the stress test based on measured temperature information of the temperature measuring element according to the temperature change pattern by the stress test control device Steps,
An operation status transmission step of transmitting the operation status of the electronic circuit board to the stress test control device by the USB communication;
An error log storing step of storing an error log in an external storage device for testing via an external storage interface of the electronic circuit board when an error occurs;
Is executed by a computer of an electronic circuit board.

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