JP5752091B2 - Memory controller - Google Patents

Description

  The present invention relates to a memory controller.

  With the progress of miniaturization of semiconductor processes, the internal operating frequency of SoC (System On a Chip) is increasing day by day. On the other hand, the operating frequency of memory devices is increasing and the memory interface standard is also improved. For example, in DDR3-SDRAM (Double Data Rate 3-Synchronous Dynamic Random Access Memory), the operating frequency is 1 GHz or more. Has been achieved.

  A memory controller is provided between the memory device and the system bus inside the SoC, interprets the protocol of the system bus inside the SoC, converts it to a command conforming to the specifications of the memory device, and converts the command to the memory device. And read / write data (see, for example, Patent Document 1). At this time, based on the state of the memory device, the memory controller issues commands for various commands so that the command issue timing does not violate the timing rules defined for the memory devices.

  In the latest memory devices such as DDR3-SDRAM, fine timing adjustments such as read leveling and write leveling are performed, so the memory device vendor provides a standard library for the physical layer that directly controls the memory device. There are many cases. In addition, as an interface between the physical layer of such a memory controller and a logical layer provided above the memory controller, an interface developed individually or a standard such as DFI is used.

JP 2007-241799 A

  The physical layer and logical layer of the memory controller are preferably operated at the same operating frequency as the operating frequency of the memory device. This is because a buffer such as a FIFO (First-In First-Out) is not required at the boundary between domains of different frequencies if the operating frequency is the same, and an increase in latency can be suppressed.

  However, since the operating frequency of recent memory devices is high, it is difficult to operate the memory controller at the same operating frequency as the operating frequency of the memory device. In such a case, the memory controller operates at a low operating frequency that is 1 / n (n> 1) of the operating frequency of the memory device.

  When at least the logical layer of the memory controller operates at a memory device operating frequency of 1 / n (n> 1), the unit time (minimum interval) for issuing commands from the logical layer is n clocks of the memory device. From the perspective of the memory device, the command issuance period may be longer than necessary, and the bandwidth and latency may deteriorate.

  Although it may be possible to avoid such deterioration of bandwidth and latency by parallelizing command issuance to memory devices in n systems, the circuit configuration of the memory controller becomes complicated and the cost of the memory controller increases. End up.

  The present invention has been made in view of the above problems, and is capable of efficiently issuing commands even when the operating frequency is 1 / n (n> 1) of the operating frequency of the memory device at a low cost. The purpose is to obtain a memory controller that can control the system at high speed.

  In order to solve the above problems, the present invention is configured as follows.

A memory controller according to the present invention includes a device management unit that manages the state of a memory device, and a command issuing unit that issues a command to the memory device. The device management unit and the command issuing unit operate at a frequency that is 1 / n (n> 1) of the operating frequency of the memory device based on n that is the value of the operating frequency setting data. Then, the device management unit sets the timing parameter value for limiting the command issuance timing by the command issuing unit, and the timing parameter setting value when the device management unit and the command issuing unit operate at the operating frequency of the memory device. The command issuance unit issues a command so as not to violate the timing parameter set by the device management unit. Then, when a fraction occurs in the above division, the device management unit rounds up or rounds down the fraction according to the type of the timing parameter.

As a result, the value of the timing parameter becomes 1 / n, so that the command is easily issued in accordance with the operating frequency of the memory device. Therefore, even if the operating frequency is 1 / n (n> 1) of the operating frequency of the memory device, the command can be issued efficiently and the memory device can be controlled at high speed at low cost. Further, even when a fraction occurs in the above division, the command is issued without violating the timing rule when the device management unit and the command issuing unit operate at the operating frequency of the memory device.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the value of the above operating frequency setting data can be switched.

  Thus, the operating frequency of the memory controller can be set as appropriate according to the operating frequency of the memory device, and a value corresponding to the set operating frequency is set as the timing parameter.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the device management unit rounds down the above-mentioned fraction when the timing parameter specifies the upper limit value.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the device management unit rounds up the above-mentioned fraction when the timing parameter specifies the lower limit value.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the device management unit sets the first timing for the first timing parameter indicating the upper limit value of the time until the start of a certain period regarding the command issuance timing and the second timing parameter indicating the lower limit value of the length of the period. When rounding down the parameters, for the second timing parameter, the value obtained by adding the remainder of the division for the first timing parameter to the set value of the second timing parameter is divided by n described above. The command issuing unit issues a command so as not to violate the first timing parameter and the second timing parameter set by the device management unit.

  Thereby, the end of the above period is appropriately set as compared with the case where the second timing parameter indicating the lower limit value of the length of the above period is divided by n as it is.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the device management unit rounds up the first timing parameter with respect to the first timing parameter indicating the lower limit value of the time until the start of a certain period and the second timing parameter indicating the upper limit value of the length of the period. For the second timing parameter, a value obtained by subtracting the remainder of division for the first timing parameter from the set value of the second timing parameter is divided by n described above. The command issuing unit issues a command so as not to violate the first timing parameter and the second timing parameter set by the device management unit.

  Thereby, the end of the above-mentioned period is appropriately set as compared with the case where the second timing parameter indicating the upper limit value of the length of the above-mentioned period is divided by n as it is.

  In addition to the above memory controller, the memory controller according to the present invention may be as follows. In this case, the device management unit has a plurality of timings when the device management unit and the command issuing unit operate at the operating frequency of the memory device when the command issuance timing is limited by the value of the arithmetic expression including a plurality of timing parameters. The value of the arithmetic expression including the parameter setting value is divided by n described above. The command issuing unit issues a command so as not to violate the value of the division result by the device management unit.

  As a result, the command issue timing is appropriately regulated as compared with the case where each of the plurality of timing parameters is divided by n separately.

  According to the present invention, it is possible to obtain a memory controller that issues a command efficiently and controls a memory device at high speed at low cost even when the operating frequency is 1 / n (n> 1). Can do.

FIG. 1 is a block diagram showing a configuration of a memory controller according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the device management unit in FIG. FIG. 3 is a flowchart for explaining the setting of the timing parameter tRC by the device management unit shown in FIG. FIG. 4 is a flowchart for explaining the setting of the timing parameter tREFI by the device management unit shown in FIG. FIG. 5 is a flowchart for explaining a timing parameter set for ODT by the device management unit shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing a configuration of a memory controller according to an embodiment of the present invention. The memory controller shown in FIG. 1 has a logical layer 1 and a physical layer 2. The physical layer 2 directly controls an external memory device 3, and the logical layer 1 sends various signals to the physical layer 2. Then, the physical layer 2 is operated to control the memory device 3. The memory device 3 is an SDRAM type volatile memory such as DDR3-SDRAM. The logical layer 1 and the physical layer 2 are separate clock domains (frequency domains).

  The logical layer 1 includes a host interface 11, an arbitration unit 12, a strobe signal generation unit 13, a refresh controller 14, a transaction buffer 15, a device management unit 16, a command issue unit 17, a command output unit 18, and a physical layer interface 19.

  The host interface 11 receives an access request for the memory device 3 via the system bus and outputs the access request to the arbitration unit 12. In the case of a write access request, the host interface 11 accepts data to be written and outputs it to the strobe signal generation unit 13. In the case of a read access request, the host interface 11 receives the data to be read from the strobe signal generation unit 13 and outputs it to the issuer of the read access request via the system bus.

  The arbitration unit 12 arbitrates various requests such as an access request from the host interface 11 and a refresh request from the refresh controller 14 and registers these requests in the transaction buffer 15 in order.

  The strobe signal generator 13 generates a strobe signal and transmits / receives data to be accessed to / from the physical layer 2 via the physical layer interface 19.

  The refresh controller 14 periodically outputs a refresh request at a cycle set in a register (not shown).

  The transaction buffer 15 queues the requests registered by the arbitration unit 12 and outputs them in order.

  FIG. 2 is a block diagram showing a configuration of the device management unit 16 in FIG. The device management unit 16 includes a coefficient setting unit 21, a timing parameter setting unit 22, and a state monitoring unit 23.

  The coefficient setting unit 21 sets operating frequency setting data according to the type of the memory device 3, the operating frequency, and the like. The device management unit 16 and the command issuing unit 17 are in the logical layer 1 and are 1 / n (n> 1) of the operating frequency of the memory device 3 based on the value n (hereinafter referred to as coefficient n) of the operating frequency setting data. , N are integers).

  In the first embodiment, in the logical layer 1, the value of the operating frequency setting data can be switched.

  The timing parameter setting unit 22 sets the value of a timing parameter that limits the command issuance timing by the command issuance unit 17. The timing parameter setting unit 22 sets the timing parameter value as the above-described coefficient when the logical layer 1 (that is, the device management unit 16 and the command issuing unit 17) operates at the operating frequency of the memory device 3. Set to the value divided by n. The command issuing unit 17 issues a command so that the value does not violate the set timing parameter. The set value of the timing parameter is set from the host device via an interface (not shown), for example, and stored in advance in the logical layer 1.

  In the first embodiment, when a fraction occurs in the above division, the timing parameter setting unit 22 rounds up or rounds off the fraction depending on the type of the timing parameter. Specifically, the timing parameter setting unit 22 rounds down the fraction when the timing parameter designates the upper limit value, and rounds up the fraction when the timing parameter designates the lower limit value.

  The value of the timing parameter is expressed by the number of clocks, and division as an integer operation is executed.

  For example, the timing parameter tRC is determined by issuing an ACT (Active) command, a COL command (RD (Read) command, RDA (Read with auto-close) command, WR (Write) command, or WRA (Write with auto-close)). This is a timing parameter for DDR2-SDRAM and DDR3-SDRAM that defines the minimum time until the command is issued. Since this timing parameter tRC sets a lower limit value, when a fraction occurs in the division for the timing parameter tRC, the value of the division result obtained by rounding up the fraction is set as the timing parameter tRC.

  For example, the timing parameter tREFI is a timing parameter of DDR2-SDRAM and DDR3-SDRAM that defines the maximum interval of REF (Auto refresh) commands. Since this timing parameter tREFI sets the upper limit value of the average interval of a predetermined number of REF commands, when a fraction occurs in the division for the timing parameter tREFI, the value of the division result with the fraction rounded down is the timing. Set as parameter tREFI.

  In the first embodiment, the timing parameter setting unit 22 includes a first timing parameter indicating an upper limit value of the time until the start of a certain period regarding a command issuance timing, and a second timing parameter indicating a lower limit value of the length of the period. When the above-mentioned fraction is rounded down for the first timing parameter, the value obtained by adding the remainder of the division for the first timing parameter to the set value of the second timing parameter is divided by the above-mentioned coefficient n for the second timing parameter. The command issuing unit 17 issues a command so as not to violate the first timing parameter and the second timing parameter set by the timing parameter setting unit 22.

  For example, in the case of a first timing parameter indicating an upper limit value of a period from a read command and a write command to ODT (On Die Termination) on start, and a second parameter indicating a lower limit value of the ODT on period, the first timing parameter When a division result is generated when dividing by the above-mentioned coefficient n and the fraction is rounded down, the division result value is set in the first timing parameter, and when the division result value obtained by rounding down the fraction is set in the first timing parameter For the second timing parameter, a value obtained by adding the remainder of the division for the first timing parameter to the set value of the second timing parameter is divided by the above-mentioned coefficient n, and the division result (when the division result has a fraction) Is the value rounded up to the second time) It is set to grayed parameters.

  Similarly, in the first embodiment, the timing parameter setting unit 22 includes a first timing parameter indicating a lower limit value of a time until the start of a certain period and a second timing parameter indicating an upper limit value of the length of the period. When the fraction is rounded up for the first timing parameter, the value obtained by subtracting the remainder of the division for the first timing parameter from the set value of the second timing parameter is divided by the coefficient n described above. The command issuing unit 17 issues a command so as not to violate the first timing parameter and the second timing parameter set by the timing parameter setting unit 22.

  The state monitoring unit 23 measures the period from the issuance of a predetermined command based on the state transition command supplied from the command issuance unit 17 corresponding to the issuance of the command, and the value is set by the timing parameter setting unit 22. A flag indicating whether or not the measurement time satisfies the condition specified by the timing parameter is set, and the value of the flag is supplied to the command issuing unit 17 as device status information.

  Further, the command issuing unit 17 sequentially receives a ROW command request, a COL command request, a ROW address, and a COL address from the transaction buffer 15, and issues a command issue request for these commands together with their addresses to the command output unit 18. To supply. Further, the command issuing unit 17 supplies command issuing requests for various commands to the command output unit 18 together with their addresses so as to satisfy the above-described conditions based on the above-described device status information.

  When issuing a command issue request, the command issuing unit 17 supplies a notification (state transition command) indicating the type of the command to the device management unit 16.

  The command output unit 18 supplies various signals for executing the requested command to the physical layer interface 19 in accordance with the command issue request from the command issue unit 17. The command output unit 18 supplies a data transfer trigger to the strobe signal generation unit 13, and the strobe signal generation unit 13 performs data transfer according to the data transfer trigger.

  The physical layer interface 19 is an interface between the logical layer 1 and the physical layer 2 and transfers various signals between the logical layer 1 and the physical layer 2 belonging to different clock domains.

  Next, the operation of the memory controller will be described. Here, the operation of the device management unit 16 related to the above-described timing parameters regarding the timing parameters tRC, tREFI, and ODT will be described.

(1) Set timing parameter tRC

  FIG. 3 is a flowchart for explaining the setting of the timing parameter tRC by the device management unit 11 shown in FIG.

  In the device management unit 16, for the timing parameter tRC, the timing parameter setting unit 22 specifies the above-described coefficient n from the operating frequency setting data and specifies the set value of the timing parameter tRC (step S1).

  Next, the timing parameter setting unit 22 divides the set value of the timing parameter tRC by the coefficient n (step S2).

  The timing parameter setting unit 22 determines whether the division result has a fraction (that is, whether there is a remainder) (step S3). If the division result has a fraction, a value obtained by rounding up the division result Is the value of the timing parameter tRC (step S4).

  For example, when the set value tRCd of the timing parameter tRC is an odd number and the coefficient n is 2, a fraction is generated. Therefore, the set value of the timing parameter tRC is set to tRCd / 2 among integers larger than tRCd / 2. The closest integer.

  The timing parameter setting unit 22 sets the value of the timing parameter tRC in the state monitoring unit 23 (step S5). That is, when there is a fraction in the division result, the value after rounding is set, and when there is no fraction in the division result, the division result is set as it is.

(2) Set timing parameter tREFI

  FIG. 4 is a flowchart for explaining the setting of the timing parameter tREFI by the device management unit 11 shown in FIG.

  In the device management unit 16, for the timing parameter tREFI, the timing parameter setting unit 22 specifies the above-described coefficient n from the operating frequency setting data and specifies the set value of the timing parameter tREFI (step S11).

  Next, the timing parameter setting unit 22 divides the set value of the timing parameter tREFI by the coefficient n (step S12).

  The timing parameter setting unit 22 determines whether or not the division result has a fraction (that is, whether or not there is a remainder) (step S13). If the division result has a fraction, a value obtained by truncating the division result Is the value of the timing parameter tREFI (step S14).

  For example, when the set value tREFId of the timing parameter tREFI is an odd number and the coefficient n is 2, a fraction is generated. Therefore, the set value of the timing parameter tREFI is set to tREFId / 2 of integers smaller than tREFId / 2. The closest integer.

  The timing parameter setting unit 22 sets the value of the timing parameter tREFI in the state monitoring unit 23 (step S15). That is, when there is a fraction in the division result, a value after truncation is set, and when there is no fraction in the division result, the division result is set as it is.

(3) Timing parameter set for ODT

  FIG. 5 is a flowchart for explaining a timing parameter set for ODT by the device management unit 11 shown in FIG.

  In the device management unit 16, for the first timing parameter (upper limit value of the time until the start of ODT on) and the second parameter (lower limit value of the length of the ODT on period), the timing parameter setting unit 22 calculates from the operating frequency setting data. While specifying the above-mentioned coefficient n, the set values of the first and second timing parameters are specified (step S21).

  Next, the timing parameter setting unit 22 divides the set value of the first timing parameter by the coefficient n (step S22).

  The timing parameter setting unit 22 determines whether the division result has a fraction (that is, whether there is a remainder) (step S23). If the division result has a fraction, a value obtained by rounding down the division result Is the value of the first timing parameter (step S24).

  The timing parameter setting unit 22 sets the value of the first timing parameter in the state monitoring unit 23 (step S25). That is, when there is a fraction in the division result, a value after truncation is set, and when there is no fraction in the division result, the division result is set as it is.

  Next, the timing parameter setting unit 22 determines whether or not there is a fraction in the division result for the first timing parameter (step S26).

  If there is a fraction in the division result for the first timing parameter, the timing parameter setting unit 22 adds the remainder of the division for the first timing parameter to the setting value of the second timing parameter (step S27). The timing parameter setting unit 22 divides the sum of the set value and the remainder by the coefficient n (step S28). The timing parameter setting unit 22 determines whether the division result has a fraction (that is, whether there is a remainder) (step S29). If the division result has a fraction, a value obtained by rounding up the division result Is the value of the second timing parameter (step S30). The timing parameter setting unit 22 sets the value of the second timing parameter in the state monitoring unit 23 (step S31). That is, when there is a fraction in the division result, the value after rounding is set, and when there is no fraction in the division result, the division result is set as it is.

  On the other hand, when it is determined in step S26 that the division result for the first timing parameter has no fraction, the timing parameter setting unit 22 divides the set value of the second timing parameter by the coefficient n (step S32). The timing parameter setting unit 22 determines whether the division result has a fraction (that is, whether there is a remainder) (step S29). If the division result has a fraction, a value obtained by rounding up the division result Is the value of the second timing parameter (step S30). The timing parameter setting unit 22 sets the value of the second timing parameter in the state monitoring unit 23 (step S31). That is, when there is a fraction in the division result, the value after rounding is set, and when there is no fraction in the division result, the division result is set as it is.

(4) Operations of the state monitoring unit 23 and the command issuing unit 17 of the device management unit 16

  As described above, the value of each timing parameter is set in the state monitoring unit 23, and the state monitoring unit 23 sets each timing parameter according to the elapsed time (number of elapsed clocks) from the timing start timing corresponding to each timing parameter. Set the value of the flag corresponding to. Then, the command issuing unit 17 determines whether or not to issue a command corresponding to each timing parameter according to the value of the flag.

  For example, for the timing parameter tRC, the time (number of clocks) from the issuance of the ACT command is measured, and when the measurement time exceeds the timing parameter tRC, the value of the flag corresponding to the timing parameter tRC is a predetermined first value. To a predetermined second value. The command issuing unit 17 issues an RD command, an RDA command, a WR command, and a WRA command when the value of the flag is the first value. When the value of the flag is the second value, the command issuing unit 17 Issuing commands, RDA commands, WR commands, and WRA commands is prohibited.

  As described above, according to the first embodiment, the device management unit 16 and the command issuance unit 17 in the logical layer 1 have n memory operation frequencies n based on the value n of the operation frequency setting data. It operates at a frequency of 1 (n> 1). Then, the device management unit 16 sets the timing parameter value for limiting the command issuance timing by the command issuance unit 17 as the timing parameter when the device management unit 16 and the command issuance unit 17 operate at the operating frequency of the memory device 3. The set value is set to a value obtained by dividing the set value by n, and the command issuing unit 17 issues a command so as not to violate the timing parameter set by the device management unit 16.

  As a result, the value of the timing parameter becomes 1 / n, so that the command is easily issued in accordance with the operating frequency of the memory device. Therefore, even if the operating frequency is 1 / n (n> 1) of the operating frequency of the memory device 3, it is possible to efficiently issue commands and control the memory device 3 at high speed.

Embodiment 2. FIG.

  In the memory controller according to Embodiment 2 of the present invention, the device management unit 16 includes the setting values of the plurality of timing parameters when the command issue timing is limited by the value of the arithmetic expression including the plurality of timing parameters. The value of the arithmetic expression is divided by the above-mentioned n, and the command issuing unit 17 issues a command so as not to violate the value of the division result by the device management unit 16.

  For example, when the memory device 3 is a DDR2-SDRAM, the minimum time from issuance of a WR command to issuance of an RD command is defined by an arithmetic expression WL + BL / 2 + tWT of three timing parameters WL, BL, and tWTR.

  At this time, the timing parameter setting unit 22 divides the calculation result of the calculation formula (WL + BL / 2 + tWT) by the coefficient n described above. When a fraction occurs in this division, a value obtained by rounding up the division result is set in the state monitoring unit 23 as a value indicating the minimum time from issuance of the WR command to issuance of the RD command.

  Since the other configuration and operation of the memory controller according to the second embodiment are the same as those of the first embodiment, the description thereof is omitted.

  As described above, according to the second embodiment, the command issue timing is appropriately regulated as compared with the case where each of the plurality of timing parameters is divided by n separately.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

  For example, in each of the above embodiments, when the memory device 3 has a plurality of ranks, independent timing parameters may be set for each rank.

  In each of the above embodiments, for a timing parameter that specifies an upper limit value for a certain period (for example, the above-described tREFI), when a fraction is generated, the remainder of the division is calculated, and the value of the timing parameter itself is Without changing, the sum of the value of the timing parameter and the remainder of the division may be divided by the above-mentioned n at the next division. Thereby, the average of the upper limit values of the periods can be adjusted to the value of the timing parameter.

  Further, although the timing parameters are exemplified in the respective embodiments, values are similarly set for timing parameters that are not exemplified.

  In each of the above embodiments, when the value of the coefficient n is a fixed value, the value of the calculation result related to the coefficient n is held in advance, and the calculation is not performed without performing the calculation related to the coefficient n. You may make it use the value of the calculation result currently hold | maintained.

  The present invention is applicable to memory controllers such as DDR2-SDRAM and DDR3-SDRAM.

DESCRIPTION OF SYMBOLS 1 Logical layer 2 Physical layer 3 Memory device 16 Device management part 17 Command issuing part

Claims (7)

A device management unit for managing the state of the memory device;
A command issuing unit for issuing a command to the memory device;
The device management unit and the command issuing unit operate at a frequency of 1 / n (n> 1) of the operating frequency of the memory device based on n which is a value of operating frequency setting data,
The device management unit sets a timing parameter value for limiting a command issuance timing by the command issuing unit, and sets the timing parameter when the device management unit and the command issuing unit operate at an operating frequency of the memory device. Set the value to the value divided by n,
The command issuing unit issues the command so as not to violate the timing parameter whose value is set by the device management unit ,
The device management unit, when a fraction occurs in the division, rounds up or rounds down the fraction according to the type of the timing parameter,
A memory controller characterized by   2. The memory controller according to claim 1, wherein the value of the operating frequency setting data is switchable. The device management unit, when said timing parameter is used to specify the upper limit value, the memory controller of claim 1, wherein the truncating the fractional. The device management unit, when said timing parameter is used to specify the lower limit, the memory controller of claim 1, wherein the rounding up the fractional. The device management unit performs the first timing with respect to a first timing parameter indicating an upper limit value of a time until the start of a certain period regarding a command issuance timing and a second timing parameter indicating a lower limit value of the length of the period. When rounding down the fraction for a parameter, for the second timing parameter, the value obtained by adding the remainder of the division for the first timing parameter to the setting value of the second timing parameter is divided by the n,
The command issuing unit issues the command so as not to violate the first timing parameter and the second timing parameter set by the device management unit;
The memory controller of claim 1 Symbol mounting characterized. The device management unit performs the first timing with respect to a first timing parameter indicating a lower limit value of a time until the start of a certain period related to the issue timing of the command and a second timing parameter indicating an upper limit value of the length of the period. When rounding up the fraction for a parameter, for the second timing parameter, the value obtained by subtracting the remainder of the division for the first timing parameter from the set value of the second timing parameter is divided by the n,
The command issuing unit issues the command so as not to violate the first timing parameter and the second timing parameter set by the device management unit;
The memory controller of claim 1 Symbol mounting characterized. The device management unit, when the issue timing of the command is limited by a value of an arithmetic expression including a plurality of timing parameters, the device management unit and the command issue unit when operating at the operating frequency of the memory device Divide the value of the arithmetic expression including the set values of multiple timing parameters by the n,
The command issuing unit issues the command so as not to violate a value of the division result by the device management unit;
The memory controller according to claim 1.

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