JP5747406B2 - Method for evaluating crystal grain size and grain size distribution of metal layer and method for manufacturing semiconductor integrated circuit device using the same - Google Patents

Description

  The present invention relates to a method for evaluating the crystal grain size and grain size distribution of a metal layer widely used as a wiring conductor, and a method for manufacturing a semiconductor integrated circuit device using the same.

  Semiconductor integrated circuit devices are being highly integrated at a high speed, in which integration is quadrupled in three years, which is said by Moore's Law. The standard for improving the degree of integration is the International Technology Roadmap for Semiconductor, which is the MPU (Micro Processing Unit) wiring of the 2007 edition (ITRS 2007 Edition). In order to improve the degree of integration, the target value of the wiring width is 68 nm in 2007, 45 nm in 2010, 32 nm in 2013, 25 nm in 2015, and 18 nm in 2018. The target values of the rates are 3.43 μΩcm, 4.08 μΩcm, 4.83 μΩcm, 5.58 μΩcm, and 6.70 μΩcm, respectively.

  Thus, as the wiring width in the semiconductor integrated circuit device decreases, the resistance increases, and the operating characteristics, particularly the operating speed, are greatly reduced. The cause of the increase in resistance is considered to be a reduction in the cross-sectional area of the wiring and a refinement of the crystal grain size in the wiring, and the coarsening of the crystal grains is being studied to reduce the resistance. For this reason, it is important to evaluate the average particle size and the particle size distribution in the wiring, and an easy and accurate evaluation method is required. As a method for evaluating the particle size distribution in the wiring, a method of forming a cross section in a part of the wiring layer with a focused ion beam cross section processing apparatus and observing this with a scanning electron microscope (Patent Document 1), on a semiconductor chip A method in which currents having different current densities are applied to a provided wiring to be measured a plurality of times, the voltage of the wiring is measured by a voltage monitor to determine a resistance increase amount, and an average grain size is determined based on the current density and the resistance increase amount ( Patent Document 2) has been proposed.

JP-A-4-2844641 JP-A-9-210939

  In the method proposed in Patent Document 1, advanced processing techniques such as cutting and polishing of fine wiring using a focused ion beam are necessary for preparing a sample for observation with a scanning electron microscope. Problems such as the fact that a lot of time is spent on observation, the average evaluation of the entire wiring cannot be performed only by observing a part of the wiring, and that it is necessary to take out from the production line for evaluation. is there.

  In the method proposed in Patent Document 2, it is necessary to prepare in advance the relationship between the current density and the resistance increase amount for the wiring materials having different grain sizes, and it takes a lot of time and labor to prepare in advance. Because the wiring for measurement formed in 1 and the wiring material prepared in advance are not manufactured by the same process, there is a problem in measurement accuracy, and in order to flow currents with different current densities through the wiring for measurement There are problems such as the need to temporarily stop the line or take out the semiconductor chip from the production line.

An object of the present invention is to provide a method for evaluating the crystal grain size and grain size distribution of a metal layer, which has solved the problems of the prior art, and a method for manufacturing a semiconductor integrated circuit device using the same.
More specifically, an object of the present invention is to provide a nondestructive and online method for evaluating the crystal grain size and grain size distribution of a metal layer and a method for manufacturing a semiconductor integrated circuit device using the same.
Other objects of the present invention will become apparent from the description of the embodiments.

  A feature of the method for evaluating the crystal grain size and grain size distribution of the metal layer of the present invention that achieves the above object is that the metal layer has a crystal structure and has a diffraction peak with respect to X-rays in a specific plane orientation. A first step of obtaining a diffraction peak obtained by irradiating with, a second step of obtaining an area average column length and a volume average column length based on the diffraction peak, and a crystal from the area average column length and the volume average column length And a third step of obtaining a lognormal distribution of particle sizes. As the X-ray, a copper Kα ray using a copper tube is used to remove the diffraction peaks Kα1 and Kα2 included in the diffraction pattern obtained from the sample, and to correct the spread of the peak caused by the diffraction device. Evaluation accuracy is improved by processing. In the present invention, since aluminum, copper, and an alloy containing these as main components used as metal wiring of a semiconductor integrated circuit device have a crystal structure and have a diffraction peak with respect to X-rays, The calculation is performed by paying attention to the fact that the crystal grain size and the grain size distribution can be measured and evaluated.

  As a metal layer suitable for the crystal grain size and grain size distribution evaluation method of the metal layer of the present invention, copper, aluminum having peaks in the (111) orientation and (200) orientation of X-ray diffraction, and alloys containing them as main components It is desirable that the metal be selected from

  The manufacturing method of the semiconductor integrated circuit device of the present invention that achieves the above object is characterized in that it is divided into a large number of regions, and the divided regions become an element chip region and a monitor chip region, and at least the element chip region has a pn A step of preparing a semiconductor wafer having a bond formed thereon, and alternately forming wiring layers made of a metal having an insulating film and a crystal structure and having an X-ray diffraction peak in a specific plane orientation on an element chip region of the semiconductor wafer , A step of forming a necessary number of insulating films and metal layers on the monitor chip region, a crystal of the metal layer from an X-ray diffraction peak obtained by irradiating the metal layer formed on the monitor chip region of the semiconductor wafer with X-rays A step of evaluating a particle size and a particle size distribution, wherein the step of evaluating the crystal particle size and the particle size distribution includes a first step of obtaining a diffraction peak by irradiating the metal layer with X-rays; The second step is to obtain the area average column length and the volume average column length based on the peak, and the third step is to obtain the logarithmic normal distribution of the crystal grain size from the area average column length and the volume average column length. It is in. The insulating film and the metal layer formed on the monitor chip region are formed in the same dimensions by the same process using the same material as the insulating film and the wiring layer formed on the element chip region. Thus, the metal layer formed on the monitor chip region has the same crystal grain size and grain size distribution as the wiring layer, and the crystal grain size and the wiring layer are formed using the metal layer formed on the monitor chip region. The particle size distribution can be evaluated with high accuracy. As the monitor chip, the first monitor chip in which the first wiring layer in the element chip area is formed, and the second monitor chip in which the second wiring layer is formed, such as a monitor chip for each wiring layer. It is desirable to prepare.

Another feature of the method for manufacturing a semiconductor integrated circuit device of the present invention that achieves the above object is that the metal layer formed on the monitor chip region is formed in the same process as the metal layer formed on the element chip region. The total mass of the metal layer per unit area of the monitor chip region is 9 × 10 ⁻⁶ g / cm ² or more in the case of copper wiring, and 3.6 × 10 ⁻⁵ g / cm ² or more in the case of aluminum wiring. In the point. In order to analyze the diffraction peak, a predetermined peak intensity is required. For this purpose, the X-ray intensity needs to be increased. In the present invention, the total mass of the wiring metal as a sample is set to a certain value or more. Thus, it was found that a predetermined analysis peak was obtained. That is 9 × 10 ⁻⁶ g / cm ² or more in the case of copper wiring, and 3.6 × 10 ⁻⁵ g / cm ² or more in the case of aluminum wiring. The means for setting the total mass of the wiring to a certain value or more is that the interval between the wiring layers formed in the same insulating layer is different between the element chip region and the monitor chip region, that is, the wiring interval of the monitor chip region is different from that of the element chip region. It is narrowing. In other words, the number of wires in the monitor chip area is made larger than that in the element chip area. As a result, even if the wiring width and wiring thickness of the element chip region and the monitor chip region are formed to be the same, the total mass of the metal layers constituting the wiring of the monitor chip region can be made a certain value or more.

  Still another feature of the method of manufacturing a semiconductor integrated circuit device of the present invention that achieves the above object is that the metal layer is a wiring layer formed in a trench having a width of 100 nm or less formed in the insulating film. . When evaluating the grain size in the depth direction of wiring, the narrower the wiring width, the more difficult it is to polish in the width direction as a TEM sample. Therefore, the crystal grain size and grain size distribution can be determined non-destructively using X-ray diffraction peaks. The inventive method to be evaluated is excellent. Further, in a copper wiring having a line width of 100 nm or less, the size of crystal grains is considered as a dominant factor in increasing resistance. Furthermore, it has been reported that the proportion of crystal grains having a size of 40 nm or less, which is close to the mean free path in copper, has a greater influence on the resistance increase than the average value of the crystal grain size. Therefore, in the resistance evaluation of copper wiring, it is important to evaluate not only the average particle size but also the particle size distribution when the line width is 100 nm or less. This is also true for aluminum wiring. Therefore, the present invention is effective in evaluating the crystal grain size and grain size distribution of copper wiring and aluminum wiring with a line width of 100 nm or less.

  According to the present invention, a metal layer having a diffraction peak with respect to X-rays is irradiated with X-rays to obtain a diffraction peak from the metal layer, and a lognormal distribution of crystal grain sizes is calculated based on the diffraction peak. Thus, the crystal grain size and grain size distribution can be measured and evaluated accurately in a non-destructive manner in a short time. In addition, since the present invention can evaluate the crystal grain size and grain size distribution of the metal layer in a short time non-destructively and online, it can be applied to a semiconductor integrated circuit device production line to obtain a desired crystal grain size and grain size distribution. A semiconductor integrated circuit device including a metal layer having a wiring as a wiring can be realized.

It is a schematic process drawing explaining the crystal grain size and grain size distribution evaluation method of the metal layer of the present invention. It is a figure which shows the X-ray-diffraction pattern of a copper wiring layer. It is a figure which shows the relationship between A (L) and Sb. It is a figure which shows the relationship between column term L and term As (L) of the crystallite size of a Fourier coefficient. It is a particle size distribution map obtained by calculation from the diffraction peak of a copper wiring layer. It is a schematic plan view which shows one Example of the semiconductor wafer used with the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic sectional drawing which shows the condition of the wiring formed on the element chip area | region of the semiconductor wafer of FIG. It is the schematic sectional drawing and schematic plan view which show the condition of the metal layer formed on the monitor chip area | region of FIG. FIG. 6 is a schematic sectional view showing a modification of the monitor chip region. It is a schematic sectional drawing which shows the modified example from which a monitor chip area | region differs. It is a figure which shows the relationship between the mass of copper per unit area of a monitor chip area | region, and diffraction peak intensity.

  When manufacturing a semiconductor integrated circuit device, at least one monitor chip region having a wiring layer manufactured by the same size, material, and process as the element chip region is formed on a semiconductor wafer on which a large number of element chip regions are formed. After the formation, the crystal grain size and grain size distribution of the wiring layer in the monitor chip region are evaluated. The method for evaluating the crystal grain size and grain size distribution of a wiring layer is to obtain a diffraction peak obtained by irradiating a sample having a crystal structure and having a diffraction peak with respect to X-rays in a specific plane orientation. A step, obtaining an area average column length and a volume average column length based on the diffraction peak, and obtaining a logarithmic normal distribution of crystal grain sizes from the area average column length and the volume average column length. Thus, a semiconductor integrated circuit device including a wiring layer having a desired crystal grain size and grain size distribution can be evaluated on the production line without breaking the crystal grain size and grain size distribution of the wiring layer. Can be manufactured.

  FIG. 1 is a schematic process diagram for explaining a method for evaluating crystal grain size and grain size distribution of a metal layer of the present invention. The evaluation method of the present invention has a crystal structure and a diffraction peak with respect to X-rays in a specific plane orientation. Step A for obtaining a diffraction peak obtained by irradiating a metal layer with X-rays, Step B for obtaining an area average column length and a volume average column length based on the diffraction peak, and an area average column length and a volume average column length It consists of step C which calculates | requires the logarithmic normal distribution of a crystal grain diameter. A crystal grain is formed by an aggregate of columns composed of atomic bonds, and each column has various sizes. A value obtained by averaging the length of each column region in consideration of the area of the region is referred to as an area average column length, and a value obtained by averaging the length of each column region in consideration of the volume of the region is referred to as a volume average column length.

  Step A will be described in detail. This step A is a step of measuring a diffraction pattern of a copper wiring film having a line width of 100 nm, for example, using a copper Kα line (tube voltage 40 kV, tube current 40 mA) with an X-ray diffractometer. . As shown in FIG. 2, since the diffraction pattern of the copper wiring layer has a strong (111) orientation, only the (111) diffraction peak and the (222) diffraction peak are observed. (222) Since the diffraction intensity of the diffraction peak is weak, measurement is performed with a long counting time. Copper Kα rays have two types of X-rays called Kα1 and Kα2 having slightly different energies based on the X-ray generation mechanism, and the diffraction peaks include two types of peaks corresponding thereto. When this diffraction peak is used, the profile is not symmetric, and the processing in the Stokes method for correcting the spread of the peak by the apparatus becomes complicated. In order to avoid this, the profile resulting from the Kα2 line is removed from the diffraction pattern of the copper wiring layer using the Rachingen method, and only the profile resulting from the Kα1 line (hereinafter referred to as the Kα1 profile) is obtained. FIG. 2 shows the Kα1 profile. By a method similar to Step A, a Kα1 profile of a sufficiently annealed high-purity copper mesh is prepared as a standard sample with sufficiently large crystal grains and no influence of strain. This is used in the next step B to eliminate peak broadening depending on the diffractometer.

ここで、両辺の対数をとると、歪の項の対数はlnＡ_D(Ｌ)＝−２πＬ²＜ε _L ² ＞Ｓb²として表され、数式（２）に整理される。

ここで、ε _L はコラム長さ方向の歪（＝ΔＬ／Ｌ）、Ｓb²=(h²+k²+l²)/a²、hklは面指数、aは格子定数である。
（１１１）及び（２２２）回折ピークについては、Ｌ＝２．２〜７７．０Åにおける数式（２）の関係を図３に示す。それぞれのＬにおける直線の切片からＡｓ(Ｌ)が求められ、傾きからは<ε _L ² >が求められる。得られたＡｓ(Ｌ)とＬの関係が図４になる。
図４において、Ａs(Ｌ)−Ｌの関係でＬ＝０の近傍における接線と横軸の切片よりＬ（area）が実線で示したＡs(Ｌ)−Ｌの近似曲線と縦横軸間の面積の２倍としてＬ(Vol)がそれぞれ求められる。 Step B will be described in detail. First, the Kα1 profiles of the (111) and (222) diffraction peaks of the copper wiring layer and the standard sample are Fourier-analyzed, and the Fourier coefficient A (L) with respect to the column length L is obtained for each peak. . After correcting the peak spread by the diffractometer by the Stokes method, A (L) is corrected, and then the area average column length L ( area ) and the volume average column length L ( Vol ) are calculated by the Warren-Aberbach method. The Fourier coefficient A (L) is expressed as the product of the crystallite size term As (L) and the strain term _AD (L).

Here, taking the logarithm of both sides, the logarithmic distortion terms lnA _D (L) = - expressed as ^{_{2πL 2 <ε L 2> Sb}} 2, are organized in equation (2).

Here, ε _L is a strain in the column length direction (= ΔL / L), Sb ² = (h ² + k ² + l ² ) / a ² , hkl is a plane index, and a is a lattice constant.
For the (111) and (222) diffraction peaks, the relationship of Equation (2) at L = 2.2 to 77.0 Å is shown in FIG. As (L) is obtained from the straight line intercept at each L, and <ε _L ² > is obtained from the slope. The relationship between As (L) and L obtained is shown in FIG.
In FIG. 4, the area between the approximate curve of As (L) -L and the vertical and horizontal axes where L (area) is indicated by a solid line from the intercept of the tangent line and the horizontal axis in the vicinity of L = 0 in the relationship As (L) -L. Respectively, L (Vol) is obtained as 2 times.

ここで、Ｄ_０及びσはそれぞれ平均粒径及び標準偏差を表す。結晶粒を球と仮定すると、Ｄ_０及びσとＬ(area)及びＬ(Vol)の関係が数式（４）及び数式（５）で与えられる。

ステップＢで求めたＬ(area)及びＬ(V0l)から数式（４）及び数式（５）を用いてＤ_０及びσを決定し、結晶粒径の対数正規分布を求める。このようにして決定した線幅１００ｎｍの銅配線層の粒径分布を透過型電子顕微鏡による観察から求めた結果と比較して図５に示す。 Step C will be described in detail. Assuming that the size of the crystal grains has a log normal distribution, the log normal distribution g _{LN (} D) of the crystal grains having the size D is expressed by Expression (3).

Here, D ₀ and σ represent an average particle diameter and a standard deviation, respectively. Assuming that the crystal grains are spheres, the relationship between D ₀ and σ and L (area) and L (Vol) is given by equations (4) and (5).

D ₀ and σ are determined from L (area) and L (V0l) obtained in step B using equations (4) and (5) to obtain a lognormal distribution of crystal grain sizes. The particle size distribution of the copper wiring layer having a line width of 100 nm thus determined is shown in FIG. 5 in comparison with the results obtained from observation with a transmission electron microscope.

  The crystal grain size and grain size distribution evaluation method of the present invention can be applied to a metal layer having a crystal structure as described above and having a diffraction peak with respect to X-rays in a specific plane orientation. What is important in the present invention is that, for example, when a metal layer is formed, the seed layer serving as a base thereof has a crystal structure and has a specific plane orientation.

FIG. 5 is a particle size distribution diagram obtained by the crystal grain size and particle size distribution evaluation method of the present invention and a particle size distribution diagram obtained by TEM. The average particle size D ₀ evaluated by the present invention is 63 nm, and the particle size distribution σ is In contrast to 1.51, the average particle diameter D ₀ evaluated by TEM is 76 nm, and the particle diameter distribution σ is 1.57. This is because the crystal grain size and grain size distribution evaluation method of the present invention has the same high accuracy as the evaluation method combining FIB and TEM, and is nondestructive without processing the sample to be evaluated. This means that it is superior to the evaluation method combining FIB and TEM in that it can be evaluated over the entire sample.

  An embodiment of a method for manufacturing a semiconductor integrated circuit device to which the metal grain crystal grain size and grain size distribution evaluation method of the present invention is applied will be described. A semiconductor integrated circuit device includes a step of forming a large number of sections having desired circuit elements on a large-area semiconductor wafer, a step of forming a multilayer wiring layer on the semiconductor wafer, a section of the semiconductor wafer, and wiring formed thereon It is manufactured through a process of dividing into a large number of chips together with a layer and a process of sealing each package in a package, but in this embodiment, it is limited to the process of applying the method for evaluating the crystal grain size and grain size distribution of the wiring layer. I will explain.

  FIG. 6 is a schematic plan view of a semiconductor wafer. For example, a semiconductor wafer W having a disk shape with a diameter of 12 inches is divided into a large number of rectangular regions, and a white display region W11 is included in the large number of rectangular regions. An element chip region serving as a semiconductor integrated circuit device, a region W12 filled with black is a monitor chip region. In this figure, the monitor chip region W12 is formed with W12a at the center of the semiconductor wafer W and W12b at the periphery, but this position has no special meaning in this embodiment. However, the purpose of the semiconductor integrated circuit device manufacturer is to grasp whether the formation conditions of the wiring layer are slightly different between the central portion and the peripheral portion of the semiconductor wafer, and the difference in the grain size is caused accordingly. The position to be formed may be selected. In the present invention, the number of monitor chip regions and the positions to be provided are not specified, and any number can be provided at any position as necessary. For example, a plurality of monitor chip regions W12 may be provided in the central portion and the peripheral portion, or a plurality of monitor chip regions W12 may be provided in the peripheral portion at regular intervals.

  FIG. 7 is a schematic sectional view of a part of the element chip region W11, and shows an example in which the wiring layer has a two-layer structure for convenience of explanation. In the figure, 1 is a semiconductor substrate on which a large number of circuit elements (not shown) are formed by pn junction adjacent to one main surface 1a, and 2 is formed on one main surface 1a of the semiconductor substrate 1. For example, a first insulating layer made of a silicon oxide layer, 2a is a through hole formed in the first insulating layer 2, 3 is a plug made of, for example, tungsten formed in the through hole 2a, 3a is a through hole 2a and a plug 3 A barrier layer 4 made of, for example, TiN (titanium nitride) is formed between the first insulating layer 2 and the plug 3, for example, a silicon oxide layer 42 made of, for example, a silicon nitride layer 41. 2 insulating layers, 4a is a first trench formed in the second insulating layer 4, 5 is a first copper wiring layer formed in the first trench 4a, 5a is the first trench 4a and the first copper wiring layer 5, Shape between The barrier layer made of, for example, TaN (tantalum nitride) / Ta (tantalum), 6 is made of, for example, a silicon oxide layer 62 via the silicon nitride layer 61 on the second insulating layer 4 and the first copper wiring layer 5, for example. A third insulating layer, 6a is a contact hole formed in the third insulating layer 6, 7 is a fourth insulating layer made of, for example, a silicon oxide layer 72 via a silicon nitride layer 71 on the third insulating layer 6, and 7a is The second trench 8 formed in the fourth insulating layer 7 on the contact hole 6a is a second copper wiring layer formed in the contact hole 6a and the second trench 7a via the barrier layer 8a.

  The wiring layer in the element chip region W11 shown in FIG. 7 is manufactured using a dual damascene process as follows. First, a semiconductor substrate 1 having a large number of circuit elements (not shown) formed by pn junctions adjacent to one main surface 1a is prepared, and the first insulating layer 2 is formed on one main surface 1a of the semiconductor substrate 1. Is deposited by a CVD (Chemical Vapor Deposition) method, and a part of the first insulating layer 2 to be a region where a wiring layer is to be formed is etched to form a through hole 2a, and the barrier layer 3a is formed in the through hole 2a. The plug 3 is formed via Next, a second insulating layer 4 is deposited on the exposed surfaces of the first insulating layer 2, the barrier layer 3a, and the plug 3 by a CVD method, and the second insulating layer 4 that is a region where a wiring layer is to be formed is etched. Thus, the first trench 4a is formed. The first trench 4a has a value selected by a current carrying capacity from a range of a width of 100 nm or less and a depth of 50 to 300 nm. The silicon nitride layer 41 on the second insulating layer 4 is used as a stopper when the silicon oxide layer 42 is etched. A first copper wiring layer 5 is formed in the first trench 4a via a barrier layer 5a. The barrier layer 5a is formed by sputtering or CVD, and the first copper wiring layer 5 is electrolyzed using a copper sulfate plating bath on a very thin copper seed layer (not shown) formed on the barrier layer 5a and a copper electrode on the anode. It is formed by a plating method. Next, the copper layer exceeding the depth of the first trench 4a, and the second insulating layer 4 and the barrier layer 5a are removed by CMP (Chemical Mechanical Polishing) to remove the first copper only in the first trench 4a. The copper layer and the barrier layer 5a to be the wiring layer 5 are left. Next, the third insulating layer 6 and the fourth insulating layer 7 are sequentially deposited on the second insulating layer 4 and the first copper wiring layer 5 by the CVD method, and the fourth insulating layer 7 above the first copper wiring layer 5 is deposited. Etching forms a second trench 7a, and the third insulating layer 6 is removed by etching to form a contact hole 6a. Next, a barrier layer 8a made of, for example, a Ta / TaN / Ta stacked body is deposited in the second trench 7a and on the surface of the contact hole 6a by sputtering or CVD to a thickness of about several to 10 nm. A thin copper seed layer (not shown) is formed on the second trench 7a and the contact hole 6a by the same method as that of the first copper wiring layer 5, and a thickness exceeding the depth is formed on the thin copper seed layer (not shown). The copper layer is formed. Thereafter, the portion of the second trench 7a that exceeds the depth of the second trench 7a, and the copper layer and the barrier layer 7a on the fourth insulating layer 7 are removed by CMP, so that the second trench 7a is only in the second trench 7a. A copper layer having a two-layer structure is completed, leaving the copper layer and the barrier layer 7a to be the copper wiring layer 8. In this embodiment, the method for manufacturing a copper wiring having a two-layer structure has been described. However, when the wiring structure has three or more layers, it can be realized by repeating the process of forming the second copper wiring layer.

FIG. 8 is a schematic plan view and a schematic sectional view for explaining the monitor chip region W12. (A) corresponds to the monitor chip region W12a of FIG. 7, and (b) corresponds to the monitor chip region W12b of FIG. In the figure, 1, 2, 4, 6 and 7 are the same semiconductor substrate as in FIG. 7, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer, and 91 is formed in the second insulating layer 2. The first monitoring copper wiring layer 101 formed in the first trench 4a through the barrier layer 91a is formed in the second trench 7a formed in the fourth insulating layer 4 through the barrier layer 101a. In the second monitor copper wiring layer, these are formed simultaneously with the element chip region W11 by the same size, material and process. Therefore, the first monitor copper wiring layer 91 and the second monitor copper wiring layer 101 have the same line width, line thickness, and crystal state as the first copper wiring layer 5 and the second copper wiring layer 8 in the element chip region W11. It has become. As a matter of course, the barrier layers 91a and 101a are formed simultaneously with the barrier layers 5a and 8a of FIG. 6, and a copper seed layer (not shown) is formed thereon.
As can be seen from the figure, a first monitor copper wiring layer 91 is formed in the monitor chip region W12a, and a second monitor copper wiring layer 101 is formed in the monitor chip region W12b. In other words, the monitor chip region W12a has The crystal chip size and grain size distribution evaluation of the first copper wiring layer 5 in the element chip area W11, and the monitor chip area W12b are used for crystal grain size and grain size distribution evaluation of the second copper wiring layer 8 in the element chip area W11, respectively. Is done.

  In the manufacture of the semiconductor integrated circuit device, the monitor chip region W12a shown in FIG. 8 is formed in the semiconductor wafer W shown in FIG. 7, so that the first copper wiring layer 91 is completed when the first copper wiring layer 5 is completed. The X-ray diffraction peak is obtained, and the crystal grain size and grain size distribution evaluation method for the metal layer described above is used to evaluate the crystal grain size and grain size distribution of the first monitor copper wiring layer 91 in a nondestructive manner. It is determined whether or not one copper wiring layer 5 has a desired crystal grain size and grain size distribution. If it has the desired crystal grain size and particle size distribution, the process proceeds to the next manufacturing process, and if it does not have the desired crystal grain size and grain size distribution, the crystal grain size and grain size distribution are changed. Implement the process to correct, or dispose of if correction is difficult. When the second copper wiring layer 8 is completed, the X-ray diffraction peak of the second monitoring copper wiring layer 101 is obtained, and the non-destructive first method is used to evaluate the crystal grain size and grain size distribution of the metal layer described above. (2) The crystal grain size and grain size distribution of the monitoring copper wiring layer 101 are evaluated to determine whether or not the second copper wiring layer 8 has the desired crystal grain size and grain size distribution. The correspondence performed based on the determination result is the same as in the case of the first copper wiring layer 5. By preparing the monitor chip region corresponding to the number of wiring layers in this way, by repeating the crystal grain size and grain size distribution evaluation according to the number of wirings, a copper wiring layer having a desired crystal grain size and grain size distribution Can be realized.

  FIG. 9 is a schematic sectional view showing a modification of the monitor chip region W12 shown in FIG. (A) corresponds to the monitor chip region W12a of FIG. 7, and (b) corresponds to the monitor chip region W12b of FIG. 8 differs from the monitor chip region of FIG. 8 in that a plug 33 is formed below the first monitor copper wiring layer 91 and a contact hole 6a is formed below the second monitor copper wiring layer 101, respectively. The wiring structure is similar to the layer 5 and the second copper wiring layer 8. As a result, the crystal grain size and grain size distribution of the first monitor copper wiring layer 91 and the second monitor copper wiring layer 101 approximate to those of the first copper wiring layer 5 and the second copper wiring layer 8, and the high The advantage that the crystal grain size and the particle size distribution can be accurately evaluated can be expected.

  FIG. 10 is a schematic sectional view showing a modified example different from the monitor chip region W12 shown in FIGS. The feature of the monitor chip region W12 is that both the first monitor copper wiring layer 91 and the second monitor copper wiring layer 101 are provided. For this reason, the crystal grain size and grain size distribution of the first copper wiring layer 5 can be evaluated by the first monitor copper wiring layer 91 in the same way as in FIGS. When the evaluation is performed using the wiring layer 101, a wiring obtained by superimposing both the first monitoring copper wiring layer 91 and the second monitoring copper wiring layer 101 is evaluated. The advantage of using the monitor chip region W12 is that the number of manufacturing processes of the semiconductor integrated circuit device can be reduced by evaluating all together without forming each time the copper wiring layer is formed. (A) is easy to manufacture because no plug and contact hole are formed, and (b) is the same structure as the element chip region W11 in which the plug and contact hole are formed, and the element chip region can be evaluated. become.

An important point when the monitor chip region W12 shown in FIGS. 8, 9, and 10 is formed on a semiconductor wafer is that the total mass of the first monitor copper wiring layer 91 and the second monitor copper wiring layer 101 is a predetermined value. That's it. FIG. 11 shows the result of measuring the relationship between the total mass of copper forming the wiring layer per unit area in each wiring layer of the monitor chip region W12 and the X-ray diffraction peak intensity. According to this result, if the total mass of copper per unit area is 1 × 10 ⁻⁵ g / cm ² or more, analysis of the diffraction peak is possible, but if it is less than that, analysis may not be possible. Then, it was confirmed that the analysis was impossible when it was 3 × 10 ⁻⁶ g / cm ² or less. This requires that the total mass of the copper wiring layer is 1 × 10 ⁻⁵ g / cm ² or more when the crystal grain size and grain size distribution evaluation method of the metal film of the present invention is used. Therefore, in order to make the total mass of the copper wiring layer per unit area in each copper wiring layer of the monitor chip region W12 be 1 × 10 ⁻⁵ g / cm ² or more, the first monitor copper wiring layer 91 and the second monitor As shown in FIG. 8C, a large number of copper wiring layers 101 having a line width of 100 nm are provided at intervals of 1400 nm.

式（６）で考慮されている種々の因子を算出し、銅のＫα線を用いた場合の銅及びアルミニウムの（１１１）面の回折強度を求めてみると強度比がＩＣｕ：ＩＡｌ＝１００：２８となり、銅と同程度の回折強度を得るためにアルミニウムでは約３．６倍の質量が必要であることが分かる。従って、モニター用アルミニウム配線層を用いてＸ線回折ピークを利用して結晶粒径及び粒径分布評価するためには、単位面積当たりの総質量は３．６×１０−５ｇ／ｃｍ２以上にすることが望ましい。 The total mass of the monitoring aluminum wiring layer when aluminum is used as the wiring layer of the semiconductor integrated circuit device will be described. There is a general formula (6) for obtaining the diffraction intensity in a powder crystal sample, and the diffraction intensity I of the (111) plane of copper and aluminum can be estimated using this formula.

When various factors considered in the equation (6) are calculated, and the diffraction intensity of the (111) plane of copper and aluminum when copper Kα rays are used, the intensity ratio is ICu: IAI = 100: It can be seen that the mass of aluminum is about 3.6 times that of aluminum in order to obtain the same diffraction intensity as copper. Accordingly, in order to evaluate the crystal grain size and grain size distribution using the X-ray diffraction peak using the aluminum wiring layer for monitoring, the total mass per unit area should be 3.6 × 10 −5 g / cm 2 or more. It is desirable.

W Semiconductor wafer W11 Element chip region W12 Monitor chip region 1 Semiconductor substrate 1a One main surface 2 First insulating layer 2a Through hole 3 Plug 4 Second insulating layer 4a First trench 41 Silicon nitride layer 42 Silicon oxide layer 5 First Copper wiring layer 5a Barrier layer 6 Third insulating layer 6a Contact hole 61 Silicon nitride layer 62 Silicon oxide layer 7 Fourth insulating layer 7a Second trench 71 Silicon nitride layer 72 Silicon oxide layer 8 Second copper wiring layer 8a Barrier layer .
91 First monitor copper wiring layer 101 Second monitor copper wiring layer

Claims (4)

A step of preparing a semiconductor wafer which is divided into a plurality of regions, and the divided regions become an element chip region and a monitor chip region, and a pn junction is formed at least in the element chip region;
A wiring layer made of a metal having an insulating film and a crystal structure and having an X-ray diffraction peak in a specific plane orientation is alternately formed on the element chip region of the semiconductor wafer, and the insulating film is formed on the monitor chip region. And a step of forming the required number of metal layers,
Evaluating the crystal grain size and grain size distribution of the metal layer from an X-ray diffraction peak obtained by irradiating the metal layer formed on the monitor chip region of the semiconductor wafer with X-rays,
The step of evaluating the crystal grain size and the grain size distribution includes a first step of obtaining a diffraction peak by irradiating the metal layer with X-rays, and an area average column length and a volume average column length based on the diffraction peak. And a third step of obtaining a logarithmic normal distribution of crystal grain size from the area average column length and the volume average column length.
A method of manufacturing a semiconductor integrated circuit device. The metal layer is a metal selected from aluminum, copper, or an alloy based on them,
The method of manufacturing a semiconductor integrated circuit device according to claim 1 . The metal layer formed on the monitor chip region is formed in the same process as the metal layer formed on the element chip region, and the total mass of the metal layer per unit area of the monitor chip region is copper wiring. In the case of 9 × 10 −6 g / cm 2 or more, in the case of aluminum wiring, it is 3.6 × 10 −5 g / cm 2 or more.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein The metal layer is a wiring layer formed in a trench having a width of 100 nm or less formed in the insulating film.
The method of manufacturing a semiconductor integrated circuit device according to claim 1 , 2 or 3 .

Images