JP5745191B2 - 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け - Google Patents

複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け Download PDF

Info

Publication number
JP5745191B2
JP5745191B2 JP2014546181A JP2014546181A JP5745191B2 JP 5745191 B2 JP5745191 B2 JP 5745191B2 JP 2014546181 A JP2014546181 A JP 2014546181A JP 2014546181 A JP2014546181 A JP 2014546181A JP 5745191 B2 JP5745191 B2 JP 5745191B2
Authority
JP
Japan
Prior art keywords
memory
requests
request
stream
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014546181A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015500536A (ja
Inventor
ジェイソン・ローレンス・パナヴィッチ
ジェームズ・ノリス・ディーフェンダルファー
トーマス・アンドリュー・ザルトリウス
トーマス・フィリップ・スパイアー
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2015500536A publication Critical patent/JP2015500536A/ja
Application granted granted Critical
Publication of JP5745191B2 publication Critical patent/JP5745191B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
JP2014546181A 2011-12-09 2012-12-10 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け Expired - Fee Related JP5745191B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/315,370 US8782356B2 (en) 2011-12-09 2011-12-09 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
US13/315,370 2011-12-09
PCT/US2012/068820 WO2013086529A1 (en) 2011-12-09 2012-12-10 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015092810A Division JP5951844B2 (ja) 2011-12-09 2015-04-30 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Publications (2)

Publication Number Publication Date
JP2015500536A JP2015500536A (ja) 2015-01-05
JP5745191B2 true JP5745191B2 (ja) 2015-07-08

Family

ID=47472053

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2014546181A Expired - Fee Related JP5745191B2 (ja) 2011-12-09 2012-12-10 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
JP2015092810A Expired - Fee Related JP5951844B2 (ja) 2011-12-09 2015-04-30 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
JP2016114191A Expired - Fee Related JP6408514B2 (ja) 2011-12-09 2016-06-08 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2015092810A Expired - Fee Related JP5951844B2 (ja) 2011-12-09 2015-04-30 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
JP2016114191A Expired - Fee Related JP6408514B2 (ja) 2011-12-09 2016-06-08 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Country Status (7)

Country Link
US (1) US8782356B2 (enExample)
EP (1) EP2788882B1 (enExample)
JP (3) JP5745191B2 (enExample)
KR (1) KR101445826B1 (enExample)
CN (1) CN103975314B (enExample)
IN (1) IN2014CN04025A (enExample)
WO (1) WO2013086529A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104541248B (zh) 2012-07-27 2017-12-22 华为技术有限公司 计算系统对屏障命令的处理
US9411542B2 (en) * 2014-02-21 2016-08-09 Analog Devices Global Interruptible store exclusive
US9594713B2 (en) 2014-09-12 2017-03-14 Qualcomm Incorporated Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
CN106886504B (zh) * 2017-04-05 2020-12-04 上海弘矽半导体有限公司 基于ahb总线的多核soc中实现原子操作系统及方法
WO2020068948A1 (en) * 2018-09-28 2020-04-02 Intel Corporation Beam failure recovery and radio link failure association in fifth generation (5g)-new radio (nr)
US11321248B2 (en) * 2019-05-24 2022-05-03 Texas Instruments Incorporated Multiple-requestor memory access pipeline and arbiter
US11252108B2 (en) 2019-06-19 2022-02-15 Nxp Usa, Inc. Controller for ordering out-of-order transactions in SoC
WO2021000282A1 (en) * 2019-07-03 2021-01-07 Huaxia General Processor Technologies Inc. System and architecture of pure functional neural network accelerator
KR102300798B1 (ko) 2019-07-31 2021-09-13 주식회사 태성이엔지 젓갈용 해산물 선별장치
US10860333B1 (en) * 2019-10-14 2020-12-08 Western Digital Technologies, Inc. Interleaved host reset and next re-initialization operations
US11775467B2 (en) 2021-01-14 2023-10-03 Nxp Usa, Inc. System and method for ordering transactions in system-on-chips
KR102856424B1 (ko) 2022-12-27 2025-09-09 주식회사 포엠 양식 패류 분리 및 선별장치
KR20250098344A (ko) 2023-12-22 2025-07-01 주식회사 포엠 양식 패류 분리 및 세척장치
US12332811B1 (en) * 2024-03-19 2025-06-17 Qualcomm Incorporated Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832304A (en) 1995-03-15 1998-11-03 Unisys Corporation Memory queue with adjustable priority and conflict detection
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6275913B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
US6275914B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
US6549985B1 (en) 2000-03-30 2003-04-15 I P - First, Llc Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor
US6754751B1 (en) 2001-03-30 2004-06-22 Intel Corporation Method and apparatus for handling ordered transactions
US6801976B2 (en) * 2001-08-27 2004-10-05 Intel Corporation Mechanism for preserving producer-consumer ordering across an unordered interface
AU2003900733A0 (en) * 2003-02-19 2003-03-06 Canon Kabushiki Kaisha Dynamic Reordering of Memory Requests
US20050289306A1 (en) 2004-06-28 2005-12-29 Sridhar Muthrasanallur Memory read requests passing memory writes
US9026744B2 (en) * 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing
US7500045B2 (en) 2005-03-23 2009-03-03 Qualcomm Incorporated Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
US9495290B2 (en) * 2007-06-25 2016-11-15 Sonics, Inc. Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering
JP2010170609A (ja) * 2009-01-22 2010-08-05 Toshiba Corp 不揮発性半導体記憶装置
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
JP2010287058A (ja) * 2009-06-11 2010-12-24 Canon Inc メモリシステム

Also Published As

Publication number Publication date
IN2014CN04025A (enExample) 2015-07-10
JP2015158943A (ja) 2015-09-03
EP2788882B1 (en) 2016-04-13
JP6408514B2 (ja) 2018-10-17
JP2016157490A (ja) 2016-09-01
US20130151799A1 (en) 2013-06-13
KR20140102732A (ko) 2014-08-22
CN103975314B (zh) 2015-09-16
CN103975314A (zh) 2014-08-06
JP5951844B2 (ja) 2016-07-13
JP2015500536A (ja) 2015-01-05
US8782356B2 (en) 2014-07-15
WO2013086529A1 (en) 2013-06-13
KR101445826B1 (ko) 2014-09-29
EP2788882A1 (en) 2014-10-15

Similar Documents

Publication Publication Date Title
JP5745191B2 (ja) 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
US9021228B2 (en) Managing out-of-order memory command execution from multiple queues while maintaining data coherency
EP1999577B1 (en) Efficient execution of memory barrier bus commands
US10078470B2 (en) Signal transfer device that maintains order of a read request and write request in posted write memory access
EP2435919B1 (en) Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
US20180059987A1 (en) Method for reducing read buffer size requirements in nvme based solid state drives
US10268416B2 (en) Method and systems of controlling memory-to-memory copy operations
US20150212759A1 (en) Storage device with multiple processing units and data processing method
US10185684B2 (en) System interconnect and operating method of system interconnect
US10346328B2 (en) Method and apparatus for indicating interrupts
US10169235B2 (en) Methods of overriding a resource retry
US7240144B2 (en) Arbitration of data transfer requests
US20140136796A1 (en) Arithmetic processing device and method for controlling the same

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140813

A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20140620

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140813

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20140813

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20141107

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20141125

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150225

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150330

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150430

R150 Certificate of patent or registration of utility model

Ref document number: 5745191

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees