IN2014CN04025A - - Google Patents

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Publication number
IN2014CN04025A
IN2014CN04025A IN4025CHN2014A IN2014CN04025A IN 2014CN04025 A IN2014CN04025 A IN 2014CN04025A IN 4025CHN2014 A IN4025CHN2014 A IN 4025CHN2014A IN 2014CN04025 A IN2014CN04025 A IN 2014CN04025A
Authority
IN
India
Prior art keywords
memory
requests
ordered
accesses
access counter
Prior art date
Application number
Other languages
English (en)
Inventor
Jason Lawrence Panavich
James Norris Dieffenderfer
Thomas Andrew Sartorius
Thomas Philip Speier
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN04025A publication Critical patent/IN2014CN04025A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
IN4025CHN2014 2011-12-09 2012-12-10 IN2014CN04025A (enExample)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/315,370 US8782356B2 (en) 2011-12-09 2011-12-09 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
PCT/US2012/068820 WO2013086529A1 (en) 2011-12-09 2012-12-10 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions

Publications (1)

Publication Number Publication Date
IN2014CN04025A true IN2014CN04025A (enExample) 2015-07-10

Family

ID=47472053

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4025CHN2014 IN2014CN04025A (enExample) 2011-12-09 2012-12-10

Country Status (7)

Country Link
US (1) US8782356B2 (enExample)
EP (1) EP2788882B1 (enExample)
JP (3) JP5745191B2 (enExample)
KR (1) KR101445826B1 (enExample)
CN (1) CN103975314B (enExample)
IN (1) IN2014CN04025A (enExample)
WO (1) WO2013086529A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104541248B (zh) 2012-07-27 2017-12-22 华为技术有限公司 计算系统对屏障命令的处理
US9411542B2 (en) * 2014-02-21 2016-08-09 Analog Devices Global Interruptible store exclusive
US9594713B2 (en) 2014-09-12 2017-03-14 Qualcomm Incorporated Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
CN106886504B (zh) * 2017-04-05 2020-12-04 上海弘矽半导体有限公司 基于ahb总线的多核soc中实现原子操作系统及方法
WO2020068948A1 (en) * 2018-09-28 2020-04-02 Intel Corporation Beam failure recovery and radio link failure association in fifth generation (5g)-new radio (nr)
US11321248B2 (en) * 2019-05-24 2022-05-03 Texas Instruments Incorporated Multiple-requestor memory access pipeline and arbiter
US11252108B2 (en) 2019-06-19 2022-02-15 Nxp Usa, Inc. Controller for ordering out-of-order transactions in SoC
WO2021000282A1 (en) * 2019-07-03 2021-01-07 Huaxia General Processor Technologies Inc. System and architecture of pure functional neural network accelerator
KR102300798B1 (ko) 2019-07-31 2021-09-13 주식회사 태성이엔지 젓갈용 해산물 선별장치
US10860333B1 (en) * 2019-10-14 2020-12-08 Western Digital Technologies, Inc. Interleaved host reset and next re-initialization operations
US11775467B2 (en) 2021-01-14 2023-10-03 Nxp Usa, Inc. System and method for ordering transactions in system-on-chips
KR102856424B1 (ko) 2022-12-27 2025-09-09 주식회사 포엠 양식 패류 분리 및 선별장치
KR20250098344A (ko) 2023-12-22 2025-07-01 주식회사 포엠 양식 패류 분리 및 세척장치
US12332811B1 (en) * 2024-03-19 2025-06-17 Qualcomm Incorporated Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832304A (en) 1995-03-15 1998-11-03 Unisys Corporation Memory queue with adjustable priority and conflict detection
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6275913B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
US6275914B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
US6549985B1 (en) 2000-03-30 2003-04-15 I P - First, Llc Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor
US6754751B1 (en) 2001-03-30 2004-06-22 Intel Corporation Method and apparatus for handling ordered transactions
US6801976B2 (en) * 2001-08-27 2004-10-05 Intel Corporation Mechanism for preserving producer-consumer ordering across an unordered interface
AU2003900733A0 (en) * 2003-02-19 2003-03-06 Canon Kabushiki Kaisha Dynamic Reordering of Memory Requests
US20050289306A1 (en) 2004-06-28 2005-12-29 Sridhar Muthrasanallur Memory read requests passing memory writes
US9026744B2 (en) * 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing
US7500045B2 (en) 2005-03-23 2009-03-03 Qualcomm Incorporated Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
US9495290B2 (en) * 2007-06-25 2016-11-15 Sonics, Inc. Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering
JP2010170609A (ja) * 2009-01-22 2010-08-05 Toshiba Corp 不揮発性半導体記憶装置
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
JP2010287058A (ja) * 2009-06-11 2010-12-24 Canon Inc メモリシステム

Also Published As

Publication number Publication date
JP2015158943A (ja) 2015-09-03
EP2788882B1 (en) 2016-04-13
JP6408514B2 (ja) 2018-10-17
JP5745191B2 (ja) 2015-07-08
JP2016157490A (ja) 2016-09-01
US20130151799A1 (en) 2013-06-13
KR20140102732A (ko) 2014-08-22
CN103975314B (zh) 2015-09-16
CN103975314A (zh) 2014-08-06
JP5951844B2 (ja) 2016-07-13
JP2015500536A (ja) 2015-01-05
US8782356B2 (en) 2014-07-15
WO2013086529A1 (en) 2013-06-13
KR101445826B1 (ko) 2014-09-29
EP2788882A1 (en) 2014-10-15

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