JP5744829B2 - Organic light emitting display device and method for erasing afterimage - Google Patents

Description

  The present invention relates to an organic light emitting display device having an afterimage erasing function and an afterimage erasing method thereof.

  A pixel of the organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) which is a self-luminous element. The OLED has a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (ETL). An organic compound layer such as an Electron Injection layer (EIL) is laminated. In an OLED, light is emitted when electrons and holes are combined in an organic material layer so that a current flows through the fluorescent or phosphorous organic material thin film.

  In an organic light emitting diode display device, an afterimage may be seen after power off and the afterimage may be fixed for a long time. Such an afterimage problem is caused by the fact that the organic light emitting diode display device does not have a function of discharging the residual charge of the pixel when the power is turned off. The afterimage of the organic light emitting diode is observed even when the power is turned off, and is observed without disappearing for a certain time after the power is turned off and after the power is turned on and the display panel is driven again.

  An object of the present invention is to provide an organic light emitting display device capable of preventing an afterimage in a power-off sequence process and an afterimage erasing method thereof.

  In order to achieve the above object, an organic light emitting display device according to the present invention includes a display panel in which orthogonal data lines and gate lines, pixels including organic light emitting diodes are formed, and a panel drive for writing data to the display panel. A circuit and a power supply input signal are received to generate a logic power supply voltage necessary for driving the panel drive circuit, and within a predetermined power-off delay time after the power supply input signal drops from a high logic level to a low logic level. Includes a power supply unit that maintains the output of the logic power supply voltage and lowers the logic power supply voltage after the power-off delay time.

  The panel driving circuit detects a power-off start time by detecting a change in the power input signal, is driven by the logic power supply voltage during the power-off delay time, and supplies preset black data to the pixel. Alternatively, a gate signal is supplied to the pixel to discharge the pixel.

  As described above, the present invention discharges a pixel during a power-off delay time in which a panel driving circuit is driven from a power-off start time when a power-off sequence starts, and erases an afterimage of the organic light emitting display device in the power-off sequence process. be able to.

1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention. 3 is a flowchart showing step-by-step a control procedure of an afterimage erasing method of an organic light emitting display device according to an embodiment of the present invention. It is a wave form diagram which shows a logic power supply voltage delay time in a power-off sequence process. FIG. 2 is a circuit diagram illustrating an example of a pixel illustrated in FIG. 1. It is a wave form diagram which shows operation | movement of the pixel which displays an input image normally in a power-on state. FIG. 5 is a waveform diagram illustrating an operation of writing black data for erasing an afterimage in a pixel by the afterimage erasing method of the organic light emitting display device according to the first embodiment of the present invention. FIG. 6 is a waveform diagram for explaining an operation of erasing an afterimage by initializing pixels and suppressing light emission by an afterimage erasing method of an organic light emitting display device according to a second embodiment of the present invention. FIG. 6 is a waveform diagram for explaining an operation of erasing an afterimage by initializing pixels and suppressing light emission by an afterimage erasing method of an organic light emitting display device according to a second embodiment of the present invention. 1 is a block diagram illustrating a configuration of a timing controller for embodying an afterimage erasing method of an organic light emitting display device according to a first embodiment of the present invention; FIG. 6 is a block diagram illustrating a configuration of a timing controller for embodying an afterimage erasing method of an organic light emitting display device according to a second embodiment of the present invention. It is a wave form diagram which shows the example in which a gate signal is applied when a logic power supply voltage becomes low. It is a wave form diagram which shows the example by which the output of a gate signal is interrupted | blocked before logic power supply voltage becomes low.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  Throughout the specification, identical reference numbers refer to substantially identical components. In the following description, when it is determined that a specific description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted.

  Referring to FIG. 1, the OLED display according to an exemplary embodiment of the present invention generates a display panel 10, a panel driving circuit for writing data to the display panel 10, and a power source necessary for driving the panel driving circuit. A power supply unit 20 is included.

  The panel drive circuit includes a data drive circuit 12, a gate drive circuit 13, a timing controller 11, and the like. The panel drive circuit detects a change in the power input signal (EL_ON) and determines a power-off start time. The panel driving circuit is additionally driven by receiving the logic power supply voltage during the power-off delay time, and writes black data preset for erasing the afterimage regardless of the input image to the pixel or the power-off delay time. During this period, the pixel is initialized to suppress light emission of the pixel. The power-off delay time is a time during which the logic power supply voltage 12V is maintained after the power-off start time.

  In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 intersect. Pixels (P) are arranged in a matrix form defined by the intersection of the data lines 14 and the gate lines 15. The gate line 15 is divided into a scan line 15a, an emission line 15b, and an initialization line 15c. Each pixel (P) can be formed by a circuit including an OLED, a driving TFT (Thin Film Transistor), four switch TFTs, and two capacitors as shown in FIG. 4, but is not limited thereto. For example, the pixel P includes an OLED, a driving element that adjusts a current flowing through the OLED according to a data voltage, one or more switching elements and one or more capacitors, and the like. Any known circuit that emits light from an OLED in response to a light emission control signal after being supplied can be implemented.

  The timing controller 11 rearranges digital video data (RGB) input from an external host system so as to correspond to the pixel arrangement of the display panel 10 and supplies the data to the data driving circuit 12. The host system can be realized as any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system transmits timing signals (Vsync, Hsync, CLK, DE) synchronized with the data together with the digital video data of the input video to the timing controller 11.

  The timing controller 11 controls the operation timing of the data driving circuit 12 using timing signals such as a vertical synchronizing signal (Vsync), a horizontal synchronizing signal (Hsync), a main clock signal (CLK), and a data enable signal (DE). A source timing control signal (DDC) and a gate timing control signal (GDC) for controlling the operation timing of the gate driving circuit 13 are generated. The source timing control signal includes a source start pulse (Source Start Pulse, SSP), a source sampling clock (Source Sampling Clock, SSC), a source output enable signal (Source Output Enable, SOE), and the like. The gate timing control signal includes a gate start pulse (GSP) that defines the start timing of the gate signal, a shift clock (GSC) that defines the shift timing of the gate signal, and a gate output that defines the output timing of the gate signal. Includes enable signal (Gate Output Enable, GOE).

  The data driving circuit 12 converts the digital video data (RGB) input from the timing controller 11 into a gamma compensation voltage, generates an analog data voltage, and supplies the data voltage to the data line 14. The gate driving circuit 13 generates a gate signal under the control of the timing controller 11 and sequentially shifts the gate signal in units of row lines of the pixel array. As shown in FIG. 5, the gate signal may include a scan signal (SCAN), an emission control signal (EM), and an initialization signal (INIT), but is not limited thereto. Under the control of the timing controller 11, the gate driving circuit 13 sequentially supplies a scan signal (SCAN) synchronized with the data voltage to the scan line 15a and sequentially supplies an emission control signal (EM) to the emission line 15b. The gate driving circuit 13 sequentially supplies the initialization signal (INIT) to the initialization line 15c in a line sequential manner. Each of the scan signal (SCAN), the light emission control signal (EM), and the initialization signal (INIT) swings between a gate high voltage (VGH) and a gate low voltage (VGL). The gate high voltage (VGH) is set to a voltage higher than the threshold voltage of the switch TFT formed in the pixel (P), while the gate low voltage (VGL) is set to the threshold voltage of the switch TFT formed in the pixel (P). Set to a lower voltage.

  The power supply unit 20 generates a logic power supply voltage for driving the panel driving circuit when a power supply input signal (EL_ON) is input as a high logic voltage. The power supply unit 20 supplies a high potential power supply voltage (EVDD), a low potential power supply voltage (EVSS), a reference voltage (Vref), and an initialization voltage (Vinit) in a power-on state in which the power input signal (EL_ON) maintains a high logic level. Can be generated. When the power input signal (EL_ON) is lowered by the low logic voltage, the power supply unit 20 reduces the high potential power supply voltage (EVDD) to the ground potential or 0 V, and then the panel drive circuit during the power-off delay time (Toff in FIG. 3). After maintaining the output of the logic power supply voltage at 12V so as to operate normally, the logic power supply voltage is lowered to the ground potential or 0V. If the high-potential power supply voltage (EVDD) decreases to the ground potential, no current flows through the OLED of the pixel (P), so the pixel (P) cannot emit light.

  The power input signal (EL_ON) indicates the power state of the organic light emitting display device as a 3.3 VTTL (Transistor Transistor Logic) voltage that swings between 3.3 V and OV. The power input signal (EL_ON) is maintained at a high logic level of 3.3 V until the power of the organic light emitting display device is turned on and is turned on until the power is turned off. The power off state occurs when the power source of the organic light emitting display device is turned off by the user or other causes. In the power-off state, the driving voltage of the organic light emitting display device is sequentially turned off by a preset power-off sequence. When the power input signal (EL_ON) is switched to the power-off state, the power input signal (EL_ON) falls to the low logic level 0V.

  The logic power supply voltage is a 12V power supply. The power supply unit 20 maintains the logic power supply voltage 12V as it is for a power-off delay time (Toff) from when the power-off input signal (EL_ON) changes to a low logic level until a predetermined time elapses. The output of the power supply voltage 12V is shut off. Accordingly, the panel driving circuit operates normally during the power-off delay time (Toff) in the power-off sequence process, and is disabled when the logic power supply voltage 12V is not input thereafter, and stops its operation. The power-off delay time (Toff) is one frame period or longer and can be set to a time of about 50 msec or longer, but is not limited thereto.

  The timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13 to erase the afterimage remaining in the pixel array of the display panel 10 in the power-off sequence process. FIG. 2 is a flowchart showing step-by-step a control procedure of the afterimage erasing method of the organic light emitting display device according to the embodiment of the present invention.

  Referring to FIG. 2, the timing controller 11 detects a change in the power input signal (EL_ON), and determines that the power is off when the power input signal falls below a predetermined reference value. (S1 and S2) The timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13 during the power-off delay time (Toff) from the power-off start time, and erases the afterimage remaining in the pixel array. (S3) The afterimage can be erased by an afterimage erasing method as in the first and second embodiments below. Since the high potential power supply voltage (EVDD) is not applied to the pixel (P) after the power-off start time, the pixel (P) does not emit light because no current flows through the OLED. Accordingly, in the present invention, the afterimage is erased by discharging the pixel (P) in a state where the pixel is not emitting light. The user cannot recognize the phenomenon in which the pixel (P) is discharged after the power-off because the pixel appears black without being emitted after the power-off.

First embodiment

  In the first embodiment, the timing controller 11 transmits black data to the data driving circuit 12 for at least one frame period, drives the data driving circuit 12 and the gate driving circuit 13, and writes the black data to the pixel (P). . Black data written to the pixels in the power-off sequence is stored in the timing controller 11 for the purpose of erasing the afterimage in the power-off sequence regardless of the input video data. In the timing controller 11, black data for erasing the afterimage can be set as digital data “000000002” of the black gradation value and stored in the register. The black data can be set to a dark gradation near the black gradation, for example, “0000XXXX2”. Here, X is 0 or 1. The timing controller 11 reads black data from the register at the time of power-off start and transmits it to the data driving circuit 12. The data driving circuit 12 is additionally driven during the power-off delay time (Toff) in the first embodiment to convert black data input from the timing controller 11 into a gamma compensation voltage to generate a black data voltage, and the black data A voltage is supplied to the data line 14. The gate driving circuit 13 is additionally driven during the power-off delay time (Toff) in the first embodiment, and under the control of the timing controller 11, a scan signal (SCAN), a light emission control signal (EM), and an initialization signal (INIT) ). The pixel (P) discharges residual charges through the data line when the black data voltage is supplied within the power-off delay time (Toff). Therefore, the afterimage of the pixel (P) is erased within the power-off delay time (Toff).

  The timing controller 11 can also repeatedly write black data to the pixel (P) during the N (N is a positive integer) frame period allowed within the power-off delay time (Toff) in the power-off sequence process.

Second embodiment

  The timing controller 11 can suppress the light emission of the pixel (P) by modulating the gate timing control signal (GDC) in the second embodiment. The gate timing control signal (GDC) includes a start pulse that indicates the start timing of each of the scan signal (SCAN), the light emission control signal (EM), and the initialization signal (INIT), and a clock signal that indicates the shift timing of the signal. The timing controller 11 modulates the gate timing control signal (GDC) in the second embodiment to initialize the pixel (P) and suppress the light emission of the pixel (P).

  The timing controller 11 does not supply any data to the data driving circuit 12 in the second embodiment. According to the second embodiment, the data driving circuit 12 does not output a data voltage in the power-off sequence process. In the second embodiment, the gate drive circuit 13 sequentially supplies only signals necessary for initialization of the pixel (P) under the control of the timing controller 11 to control the light emission timing of the pixel (P). (EM (P2) in FIG. 5) is not output. When a signal necessary for initialization of the pixel (P), for example, EM and INIT in FIG. 7 is applied to the pixel (P), a part of the TFT is turned on at the pixel (P). The pixel (P) discharges the residual charge through the TFT turned on within the power-off delay time (Toff).

  FIG. 3 is a waveform diagram showing the power-off delay time (Toff) in the power-off sequence process.

  Referring to FIG. 3, the timing controller 11 transmits digital video data of an input image to the data driving circuit 12 in a power-on state where the power input signal (EL_ON) maintains a high logic level, and the data driving circuit 12 and the gate driving circuit. 13 is controlled by a normal method, and input video data is written to the pixel (P). The pixel (P) is updated with data every frame period. In FIG. 3, “normal frame” indicates one frame period in which input video data is written to the pixel (P) in the power-on state.

  The timing controller 11 determines the power off start time when the power input signal (EL_ON) changes to the low logic level, and the data driving circuit 12 and the gate driving circuit during the power off delay time (Toff) in which the logic power supply voltage 12V is maintained. 13 is erased, and the residual image remaining in the pixel array is erased. In FIG. 3, “Off frame” indicates one frame period in which black data is written to the pixel (P) during the power-off sequence or the emission of the pixel (P) is suppressed by blocking the emission control signal and the afterimage is erased. . One or more Off frame periods may be allocated within the power-off delay time (Toff).

  Each pixel (P) is connected to the data line 14, the scan line 15a, the emission line 15b, and the initialization line 15c as shown in FIG. Each pixel (P) is supplied with pixel drive power such as a high potential power supply voltage (EVDD), a low potential power supply voltage (EVSS), a reference voltage (Vref), and an initialization voltage (Vinit). The reference voltage (Vref) and the initialization voltage (Vinit) can be set lower than the low potential power supply voltage (EVSS). The reference voltage (Vref) is set higher than the initialization voltage (Vinit). The difference between the reference voltage (Vref) and the initialization voltage (Vinit) can be set to be larger than the threshold voltage of the driving TFT (DT). The high potential power supply voltage (EVDD), the low potential power supply voltage (EVSS), the reference voltage (Vref), and the initialization voltage (Vinit) can be generated by the host system or the power supply unit 20.

  If the input video data has been updated to the pixel (P) at the time when the power input signal (EL_ON) changes to the low logic level, the timing controller 11 writes the remaining image to the pixel (P) as shown in FIG. Can be erased.

  FIG. 4 is a circuit diagram showing an example of the pixel (P). FIG. 5 is a waveform diagram showing the operation of the pixel (P) that normally displays the input video in the power-on state.

  4 and 5, the pixel P includes an OLED, a driving TFT DT, first to fourth switch TFTs ST1 to ST4, a compensation capacitor Cgss, and a storage capacitor Cst.

  The OLED emits light by current supplied from the driving TFT (DT). An organic compound layer is laminated between the anode and cathode of the OLED. The organic compound layer of the OLED may include a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. However, any known OLED structure is applicable.

  The driving TFT (DT) adjusts a current flowing through the OLED by a voltage between its gate and source. The gate electrode of the driving TFT (DT) is connected to the node B, the drain electrode is connected to the input terminal of the high potential cell driving voltage (EVDD), and the source electrode is connected to the node C.

The first switch TFT (ST1) switches a current path between the node A and the node B in response to the light emission control signal (EM). The first switch TFT (ST1) is turned on to transmit the data voltage (Vdata) stored (stored) in the node A to the node B. The gate electrode of the first switch TFT (ST1) is connected to the emission line 15b, the drain electrode is connected to the node A, and the source electrode is connected to the node B.

  The second switch TFT (ST2) switches a current path between the input terminal of the initialization voltage (Vinit) and the node C in response to the initialization signal (INIT). The second switch TFT (ST2) is turned on to supply an initialization voltage (Vinit) to the node C. The gate electrode of the second switch TFT (ST2) is connected to the initialization line 15c, the drain electrode is connected to the input terminal of the initialization voltage (Vinit), and the source electrode is connected to the node C.

  The third switch TFT (ST3) switches a current path between the input terminal of the reference voltage (Vref) and the node B in response to the initialization signal (INIT). The third switch TFT (ST3) is turned on to supply the reference voltage (Vref) to the node B. The gate electrode of the third switch TFT (ST3) is connected to the initialization line 15c, the drain electrode is connected to the input terminal of the reference voltage (Vref), and the source electrode is connected to the node B.

  The fourth switch TFT (ST4) switches a current path between the data line 14 and the node A in response to the scan signal (SCAN). The fourth switch TFT (ST4) is turned on to supply the data voltage (Vdata) to the node A. The gate electrode of the fourth switch TFT (ST4) is connected to the scan line 15a, the drain electrode is connected to the data line 14, and the source electrode is connected to the node A.

  A compensation capacitor (Cgss) is connected between node B and node C. The compensation capacitor (Cgss) enables a source follower system when detecting the threshold voltage of the driving TFT (DT), and contributes to improvement of the compensation capability for the threshold voltage.

  A storage capacitor (Cst) is connected between node A and node C. The storage capacitor (Cst) accumulates (stores) the data voltage (Vdata) input to the node A and transmits it to the node C.

  The operation of the pixel (P) includes an initialization period (Ti) for initializing the nodes A, B, and C with a specific voltage, a sensing period (Ts) for detecting and storing a threshold voltage of the driving TFT (DT), and data writing Therefore, a driving period (Tp) driven by the data voltage (Vdata) that is not affected by a threshold voltage of the driving TFT (DT) and a programming period (Tp) in which the data voltage (Vdata) is applied to the pixel (P). The light emission period (Te) for supplying the current of the OLED through is divided. The light emission period (Te) is divided into first and second light emission periods (Te1, Te2).

  In the initialization period (Ti), the second and third switch TFTs (ST2, ST3) are turned on simultaneously in response to the initialization signal (INIT) at the high logic level. The first switch TFT (ST1) is turned on in response to the first pulse (P1) of the light emission control signal (EM) during the initialization period (Ti). The first pulse (P1) of the light emission control signal (EM) is superimposed on the initialization signal (INIT). The pulse of the initialization signal (INIT) is desirably set wider than the first pulse (P1) of the light emission control signal (EM) in order to stabilize the initialization. As a result, the initialization voltage (Vinit) during the initialization period (Ti) is supplied to the node C, and the reference voltage (Vref) is supplied to the node B. The reference voltage (Vref) is supplied to the node A via the first and third switch TFTs (ST1, ST3). The fourth switch TFT (ST4) is kept off in the initialization period (Ti). The reference voltage (Vref) is set higher than the initialization voltage (Vinit) in order to make the current path between the drain and source of the driving TFT (DT) higher than the source voltage by making the gate voltage of the driving TFT (DT) higher than the source voltage. Is done.

  The initialization voltage (Vinit) is appropriately set to a low value so that the OLED does not emit light in the remaining periods (Ti, Ts, Tp) excluding the light emission period (Te). For example, when the high potential cell drive voltage (EVDD) is set to 20V and the low potential cell drive voltage (EVSS) is set to 0V, the reference voltage (Vref) and the initialization voltage (Vinit) are set to -1V and -5V, respectively. Can be done.

  A scan signal (SCAN), an emission control signal (EM), and an initialization signal (INIT) as shown in FIG. 5 form a set, and a scan line 15a, an emission line 15b for selecting one line of the pixel array, and A set of gate lines including the initialization line 15c is supplied. Such signals (SCAN, EM, INIT) are supplied to the gate line 15 while shifting in units of row lines of the pixel array.

  In the sensing period (Ts), the light emission control signal (EM) and the initialization signal (INIT) are inverted to the low logic level. The scan signal (SCAN) is also maintained at a low logic level during the sensing period (Ts). As a result, the first to fourth switch TFTs (ST1, ST2, ST3, ST4) remain off during the sensing period (Ts), and the current (Idt) flowing through the driving TFT (DT) is gradually reduced. The When the gate-source voltage of the driving TFT (DT) reaches the threshold voltage (Vth) of the driving TFT (DT), the driving TFT (DT) is turned off. At this time, the threshold voltage of the driving TFT (DT) ( Vth) is detected by the source follower method, and the node C is charged.

  In the programming period (Tp), the fourth switch TFT (ST4) is turned on by a high logic level scan signal (SCAN) synchronized with the data voltage (Vdata) of the input video. At this time, the data voltage (Vdata) is supplied to the node A. The first to third switch TFTs (ST1, ST2, ST3) are kept off during the programming period (Tp). In the programming period (Tp), since the nodes B and C are separated from the node A by the TFT or the capacitor, the potential in the sensing period (Ts) is maintained almost as it is.

  In the first light emission period (Te1), the first switch TFT (ST1) is turned on by the second pulse (P2) of the light emission control signal (EM). At this time, the data voltage (Vdata) charged in the node A is transmitted to the node B. The second to fourth switch TFTs (ST2, ST3, ST4) are kept off during the first light emission period (Te1). The driving TFT (DT) supplies a current proportional to the data voltage (Vdata) transmitted to the node B to the OLED in the first light emission period (Te1). During the first light emission period (Te1), the potential of the node C rises according to the current flowing through the driving TFT (DT), and the OLED can be turned on when the potential rises above the threshold voltage of the OLED. Increased to "Voled", so that the OLED is turned on and emits light.

  In the second light emission period (Te2), the first to fourth switch TFTs (ST1, ST2, ST3, ST4) are kept off. The second light emission period (Te2) is set to prevent deterioration of the first switch TFT (ST1) to which the light emission control signal (EM) is applied. Therefore, the light emission control signal (EM) is inverted to a low logic level during the second light emission period (Te2) in order to compensate for the gate bias stress of the first switch TFT (ST1).

  The pixel (P) detects the threshold voltage of the driving TFT (DT) according to the source follower method when realized by a circuit as shown in FIG. In the source follower method, a compensation capacitor is connected between the gate and the source of the driving TFT (DT), and the source voltage of the driving TFT follows the gate voltage when the threshold voltage is detected. In addition, since the high potential cell drive voltage (EVDD) is supplied to the drain of the drive TFT (DT) separately from the gate, the source follower method uses only the threshold voltage of the drive TFT (DT) having a positive value. In addition, a threshold voltage having a negative value can be detected. The pixel (P) causes the gate of the driving TFT (DT) to float when the threshold voltage of the driving TFT (DT) is sensed, and drives the compensation capacitor (Cgss) connected between the gate and source of the driving TFT (DT). The threshold voltage compensation capability can be improved by using the parasitic capacitor of the TFT (DT). If the on-duty of the light emission control signal (EM) is reduced, the deterioration of the switch TFT (ST1) switched by the light emission control signal (EM) can be minimized.

  FIG. 6 is a waveform diagram illustrating an operation of writing black data for erasing an afterimage in a pixel by the afterimage erasing method of the OLED display according to the first exemplary embodiment of the present invention. In FIG. 6, the light emission control signal (EM) and the initialization signal (INIT) are omitted from the gate signal.

  Referring to FIG. 6, under the control of the timing controller 11, the gate driving circuit 13 sequentially supplies scan signals (SCAN1 to SCANn) synchronized with the data voltage of the input video to the scan line 15a in the power-on state. Therefore, input video data is written to the pixel (P) in the power-on state.

  The timing controller 11 receives the digital black data set for the purpose of erasing the afterimage regardless of the input video data within the power-off delay time (Toff) after the power input signal (EL_ON) changes to the low logic level. Transmit to. The digital black data is set for the purpose of erasing the afterimage regardless of the input video data and is generated by the timing controller 11. The digital black data induces the discharge of the pixel (P) within the power-off delay time (Toff) after the power-off start.

  The data driving circuit 12 converts the digital black data into a gamma compensation voltage to generate a black data voltage, and supplies the black data voltage to the data line 14. The gate driving circuit 13 sequentially supplies scan signals (SCAN1 to SCANn) synchronized with the black data voltage to the scan line 15a under the control of the timing controller 11 within the power-off delay time (Toff). Therefore, black data unrelated to the input video is written to the pixel (P) in the power-off sequence process. Since black data is written in the pixel (P), the afterimage is erased.

  The reference voltage (Vref) and the initialization voltage (Vinit) are changed to the ground voltage or 0 V at the time of power off start. This is because if the reference voltage (Vref) and the initialization voltage (Vinit) are maintained at a negative voltage or a positive voltage after the power-off start, unnecessary charges can be accumulated on the pixel (P). Therefore, after the power-off start, the nodes A, B and C of the pixel (P) are discharged to the ground potential.

  7 and 8 are waveform diagrams illustrating an operation of initializing a pixel (P) and suppressing light emission and erasing the afterimage by the afterimage erasing method of the organic light emitting display device according to the second embodiment of the present invention. .

  Referring to FIGS. 7 and 8, the timing controller 11 detects the second pulse (P2) of the light emission control signal (EM) and the scan signal (SCAN) at the power-off start time when the power input signal (EL_ON) is changed to the low logic level. ) Is modulated such that the gate timing control signal (GDC) is not generated.

  Since no data is input from the timing controller 11 during the power-off delay time (Toff), the data driving circuit 12 does not output a data voltage. The gate drive circuit 13 controls the first pulse (P1) of the light emission control signal (EM) and the initialization signal (INIT) for initializing the pixel (P) during the power-off delay time (Toff) under the control of the timing controller 11. ) And the signals are sequentially shifted as shown in FIG. The gate driving circuit 13 does not output the second pulse (P2) of the light emission control signal (EM) during the power-off delay time (Toff) under the control of the timing controller 11, and the scan signal (SCAN) synchronized with the data voltage is output. Does not generate a pulse.

  The pixel (P) is discharged in response to signals (EM (P1), INIT) as shown in FIGS. 7 and 8 during the power-off delay time (Toff). At this time, in each pixel (P), the nodes A, B, and C are connected to the ground voltage source and discharged. The OLED of the pixel (P) remains off during the power-off delay time (Toff) and does not emit light.

  FIG. 9 is a block diagram showing a configuration of a timing controller for realizing the afterimage erasing method of the OLED display according to the first exemplary embodiment of the present invention.

  Referring to FIG. 9, the timing controller 11 includes a power detection unit 111, a data alignment unit 112, a register 113, and a timing control signal generation unit 114.

  The power detection unit 111 detects a voltage change of the power input signal (EL_ON) and outputs a power on / off signal indicating the power on state or the power off state.

  The data alignment unit 112 receives the digital video data of the input video and the digital black data for erasing the afterimage. The data alignment unit 112 aligns data so as to correspond to the pixel arrangement of the display panel 10. In response to the first logic level of the power on / off signal input from the power detection unit 111, the data alignment unit 112 selects the digital video data of the input image in the power on state and transmits the selected digital video data to the data driving circuit 12. On the other hand, in response to the second logic level of the power on / off signal input from the power detection unit 111, digital black data for afterimage erasing is selected and transmitted to the data driving circuit 12 in the power off delay time (Toff). . The digital black data is set regardless of the input video and is stored in the built-in register 113 of the timing controller 11.

  The timing control signal generator 114 receives the timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the main clock signal (CLK), and the data enable signal (DE), and counts the timing signals. A data timing control signal (DDC) and a gate timing control signal (GDC) are generated. In the afterimage erasing method of the OLED display according to the first exemplary embodiment of the present invention, the data timing control signal (DDC) and the gate timing control signal (GDC) are not modulated in the power-off sequence process. Accordingly, in the method for erasing an afterimage of the organic light emitting display device according to the first embodiment of the present invention, the data driving circuit 12 and the gate driving circuit 13 are normally operated in a power-on state during the power-off delay time (Toff). In operation, black data is written to the pixel (P) to erase the afterimage.

  FIG. 10 is a block diagram showing a configuration of a timing controller for realizing the afterimage erasing method of the organic light emitting display device according to the second embodiment of the present invention.

  Referring to FIG. 10, the timing controller 11 includes a power detection unit 117, a data alignment unit 115, and a timing control signal generation unit 116.

  The power detection unit 117 detects a voltage change of the power input signal (EL_ON) and outputs a power on / off signal indicating the power on state or the power off state.

  The data alignment unit 115 receives the digital video data of the input video, arranges the data so as to correspond to the pixel arrangement of the display panel 10, and transmits the data to the data driving circuit 12.

  The timing control signal generator 116 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (CLK), and a data enable signal (DE), and counts the timing signals. A data timing control signal (DDC) and a gate timing control signal (GDC) are generated so that a waveform as shown in FIG. 5 is generated in a power-on state in which the first logic level of the power-on / off signal is maintained. The timing control signal generator 116 is responsive to the second logic level of the power on / off signal input from the power detector 117 so that the gate timing is generated so that the signals shown in FIGS. Modulate the control signal (GDC). As an example of the modulation method, a start pulse of the scan signal (SCAN) is not generated, only the first pulse is generated from the start pulse of the light emission control signal (EM), and the second pulse is not generated. The start pulse of the light emission control signal (EM) includes first and second pulses (P1, P2) such as the light emission control signal (EM) in a power-on state. If only the first pulse is included in the modulated start pulse of the light emission control signal (EM), as shown in FIGS. 7 and 8, the light emission control signal (EM) is the first pulse for initializing the pixel (P) ( Only P1) is included.

  When the gate drive circuit 13 outputs the gate signal until the logic power supply voltage decreases as shown in FIG. 11, the output of the gate drive circuit 13 varies abnormally due to the fluctuation of the logic power supply voltage, and any line of the display panel 10 Therefore, waveform distortion of the gate signal may occur, and charges may be accumulated in the pixel (P) by the gate signal voltage. As a result, unnecessary charges are accumulated in the pixel (P), and such charges may increase the stress of the TFT in the pixel (P), resulting in threshold voltage fluctuations and deterioration. Thus, when the output of the gate drive circuit 13 is generated even after the logic power supply voltage is lowered or the logic power supply voltage is lowered to 0 V (see the inclined line pattern in FIG. 11), the organic light emitting diode display device Is turned on again and an image is displayed on the display panel 10, stripe noise is observed in any line of the display panel.

  The present invention allows a gate signal to be normally output from the gate driving circuit 13 only while the logic power supply voltage is maintained at 12 V within the gate power-off delay time (Toff) when the power input signal is lowered. Before the voltage starts to drop, the output of the gate drive circuit 13 is cut off. Specifically, the timing controller 11 counts the gate-on time (Tgon) set in a time shorter than the time from the power-off start time to the power-off delay time (Toff), and when the time (Tgon) is reached The output of the gate timing control signal (GDC) is stopped. As a result, the gate drive circuit 13 does not receive the gate timing control signal (GDC), that is, the gate start pulse (GSP), the gate shift clock (GSC), and the gate output enable signal (GOE). Does not occur.

  The above-described afterimage erasing method of the present invention can also be applied to a method of writing black gradation data to a pixel for driving black data insertion in a power-on state. In the black data insertion drive, black data is written after a predetermined time after writing the input video data to the pixel.

  The afterimage erasing method of the present invention can also be applied to a method of writing black data to a pixel in order to reduce 3D crosstalk in a power-on state of a shutter glass type stereoscopic image display device. . 3D crosstalk refers to a phenomenon in which a viewer's one eye (left eye or right eye) can see both a left-eye image and a right-eye image, and the left-eye image and the right-eye image appear to overlap. The shutter glasses type stereoscopic image display device time-divides a left-eye image and a right-eye image displayed on the display panel, and turns on / off the left-eye shutter and the right-eye shutter of the shutter glasses in synchronization with image data displayed on the display panel. In order to reduce 3D crosstalk, the shutter glasses-type stereoscopic video display device performs black gradation on pixel data during a reset frame period inserted between a frame period in which left-eye video data is written and a frame period in which right-eye video data is written. Write data. The afterimage erasing method of the present invention can be applied to a reset frame period in a shutter glasses type stereoscopic image display device to display a black gradation on a pixel.

Claims (11)

A display panel;
A panel drive circuit for writing data to the display panel;
A logic power supply voltage necessary for driving the panel driving circuit is generated upon receiving a power input signal, and after the power input signal has dropped from a high logic level to a low logic level, the logic is within a predetermined power-off delay time. A power supply unit that maintains a power supply voltage output and reduces the logic power supply voltage after the power-off delay time;
The display panel includes pixels including orthogonal data lines and gate lines, and organic light emitting diodes,
The gate line is divided into a scan line, an emission line, and an initialization line.
The pixel is
A fourth switching transistor having a gate connected to the scan line and a drain connected to the data line;
A first switching transistor having a gate connected to the emission line and a drain connected to the source of the fourth switching transistor;
A third switching transistor having a gate connected to the initialization line and a source connected to the source of the first switching transistor;
A second switching transistor having a gate connected to the initialization line and a source connected to the anode of the organic light emitting diode;
A driving transistor having a gate connected to a source of the first switching transistor and a source connected to an anode of the organic light emitting diode;
A storage capacitor connected between a source of the fourth switching transistor and a source of the second switching transistor;
Comprising
The panel drive circuit is
A change in the power supply input signal is detected to determine a power-off start time. At the power-off start time, the drains of the second switching transistor and the third switching transistor are set to a ground voltage, and the power-off delay is detected. The storage capacitor is driven by the logic power supply voltage for a time and rewrites a pixel by supplying preset black data to the storage capacitor, or supplies a gate signal to the pixel emission line and the initialization line. An organic light emitting display device characterized by discharging electric charges accumulated in the organic light emitting display device. The panel drive circuit is
A data driving circuit for supplying a data voltage to the data line;
A gate driving circuit for sequentially supplying the gate signals to the gate lines;
The operation timing of the data driving circuit and the gate driving circuit is controlled, the change of the power input signal is detected, and the data driving circuit and the gate driving circuit are driven during the power-off delay time to discharge the pixel. The organic light emitting display device according to claim 1, further comprising a timing controller that controls the display. In the case where the panel driving circuit supplies the black data,
The timing controller transmits digital black data set in advance for erasing an afterimage regardless of an input image during the power-off delay time to the data driving circuit,
The data driving circuit converts the digital black data into a gamma compensation voltage during the power-off delay time, generates a black data voltage, and supplies the black data voltage to the data line.
3. The organic light emitting display device according to claim 2, wherein the gate driving circuit sequentially supplies the gate signal including the scan signal synchronized with the black data voltage during the power-off delay time to the gate line. .   4. The organic light emitting display device according to claim 3, wherein the gate driving circuit stops the gate signal output before the logic power supply voltage starts to fall within the power-off delay time.   The timing controller outputs a gate timing control signal for controlling the operation timing of the gate driving circuit when a gate on time set to a time shorter than a time from the power off start time to the power off delay time is reached. The organic light emitting display device according to claim 4, wherein the organic light emitting display device is stopped. The panel drive circuit is
The gate signal is divided into a scan signal sequentially supplied to the scan line, first and second pulses of a light emission control signal sequentially supplied to the emission line, and an initialization signal sequentially supplied to the initialization line. And
4. The organic light emitting display device according to claim 3, wherein the initialization signal is superimposed on a first pulse of the light emission control signal. The timing controller is
Generating a data timing control signal for controlling the operation timing of the data driving circuit and a gate timing control signal for controlling the operation timing of the gate driving circuit;
Modulating the gate timing control signal at the power off start time,
The gate driving circuit outputs a remaining gate signal excluding a second pulse of the scan signal and the light emission control signal during the power-off delay time in response to the modulated gate timing control signal. The organic light emitting display device according to claim 6.   8. The organic light emitting display device according to claim 7, wherein the data driving circuit does not output a data voltage during the power-off delay time.   8. The organic light emitting display device according to claim 7, wherein the gate driving circuit stops the gate signal output before the logic power supply voltage starts to decrease within the power-off delay time.   The timing controller receives a gate timing control signal for controlling the operation timing of the gate driving circuit when the gate on time set to a time shorter than the time from the power off start time to the power off delay time is reached. 10. The organic light emitting display device according to claim 9, wherein output is stopped. A display panel;
A panel drive circuit for writing data to the display panel;
Including power supply,
An afterimage erasing method for an organic light emitting display device comprising:
The display panel includes pixels including orthogonal data lines and gate lines, and organic light emitting diodes,
The gate line is divided into a scan line, an emission line, and an initialization line,
The pixel is
A fourth switching transistor having a gate connected to the scan line and a drain connected to the data line;
A first switching transistor having a gate connected to the emission line and a drain connected to the source of the fourth switching transistor;
A third switching transistor having a gate connected to the initialization line and a source connected to the source of the first switching transistor;
A second switching transistor having a gate connected to the initialization line and a source connected to the anode of the organic light emitting diode;
A driving transistor having a gate connected to a source of the first switching transistor and a source connected to an anode of the organic light emitting diode;
A storage capacitor connected between a source of the fourth switching transistor and a source of the second switching transistor;
Comprising
The method
In the power supply unit, receiving a power input signal and generating a logic power supply voltage necessary for driving the panel drive circuit;
Maintaining the output of the logic power supply voltage for a predetermined power-off delay time after the power input signal is inverted from the high logic level to the low logic level, and driving the panel driving circuit;
Detecting a change in the power input signal to determine a power off start time;
Setting drains of the second switching transistor and the third switching transistor to a ground voltage at the power-off start time;
Supplying black data set in advance using the panel driving circuit driven by the logic power supply voltage during the power-off delay time to the pixel to rewrite the pixel, or changing the gate signal to the pixel emission line And an afterimage erasing method of the organic light emitting display device, comprising: discharging the charge stored in the pixel storage capacitor by being supplied to the initialization line.

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