JP5740222B2 - Manufacturing method of liquid crystal display device - Google Patents

Description

  Embodiments described herein relate generally to a method for manufacturing a liquid crystal display device, a liquid crystal display device, and a counter substrate.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In recent years, liquid crystal display panels in a fringe field switching (FFS) mode and an in-plane switching (IPS) mode have been put into practical use. Such an FFS mode or IPS mode liquid crystal display panel has a configuration in which a liquid crystal layer is held between an array substrate including a pixel electrode and a common electrode and a counter substrate. Since the conductive film is hardly arranged on the counter substrate, a configuration for shielding an electric field from the outside has been proposed.

JP 2009-116309 A

  An object of the present embodiment is to provide a manufacturing method of a liquid crystal display device, a liquid crystal display device, and a counter substrate capable of suppressing a decrease in yield and display quality.

According to this embodiment,
A first substrate having a common electrode formed over a plurality of pixels and a pixel electrode formed in each pixel is prepared on a first insulating substrate, and a first conductive layer formed on the outer surface of the second insulating substrate is prepared. A second substrate comprising a layer and a dielectric thin film formed on the inner surface of the second insulating substrate, and forming an alignment film material on the dielectric thin film of the second substrate; There is provided a method for manufacturing a liquid crystal display device, characterized in that an orientation treatment is performed on a material, and the first substrate and the second substrate are bonded together.

According to this embodiment,
A first insulating substrate; a common electrode formed over a plurality of pixels on the first insulating substrate; an insulating film covering the common electrode; and the common electrode formed on each pixel on the insulating film; A first substrate having a pixel electrode facing each other and having a slit formed thereon, a first alignment film covering the pixel electrode, a second insulating substrate, and an organic conductive layer formed on an outer surface of the second insulating substrate And a dielectric thin film formed on the inner surface of the second insulating substrate, and a liquid crystal layer held between the first substrate and the second substrate. A liquid crystal display device is provided.

According to this embodiment,
A counter substrate constituting a liquid crystal display device, comprising: an insulating substrate; an organic conductive layer formed on an outer surface of the insulating substrate; a black matrix and a color filter formed on an inner surface of the insulating substrate; There is provided a counter substrate comprising an overcoat layer covering the color filter and an alignment film covering the overcoat layer.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel constituting the liquid crystal display device of the present embodiment. FIG. 2 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel shown in FIG. FIG. 3 is a flowchart for explaining a method of manufacturing the liquid crystal display panel of this embodiment. FIG. 4 is a schematic cross-sectional view for explaining the manufacturing method of the liquid crystal display panel of the present embodiment.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN is held between an array substrate (first substrate) AR, a counter substrate (second substrate) CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. The active area ACT is composed of a plurality of pixels PX arranged in a matrix of m × n (where m and n are positive integers).

  In the active area ACT, the array substrate AR includes n gate wirings G (G1 to Gn) and n capacitance lines C (C1 to Cn) that extend in the first direction X in the first direction X, respectively. M source lines S (S1 to Sm) each extending along the intersecting second direction Y, and mxn switching elements electrically connected to the gate line G and the source line S in each pixel PX SW, m × n pixel electrodes PE electrically connected to the switching element SW in each pixel PX, a common electrode CE which is a part of the capacitor line C and faces the pixel electrode PE, and the like. The storage capacitor CS is formed between the capacitor line C and the pixel electrode PE.

  The common electrode CE is formed in common across the plurality of pixels PX. The pixel electrode PE is formed in an island shape in each pixel PX.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. Each capacitance line C is drawn outside the active area ACT and connected to the third drive circuit CD. The first drive circuit GD, the second drive circuit SD, and the third drive circuit CD are formed on the array substrate AR and connected to the drive IC chip 2. In the illustrated example, the driving IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN as a signal source necessary for driving the liquid crystal display panel LPN.

  In the present embodiment, the driving IC chip 2 includes an image signal writing circuit 2A that performs control necessary for writing an image signal to the pixel electrode PE of each pixel PX in an image display mode in which an image is displayed in the active area ACT. ing. In addition to the image signal writing circuit 2A, the drive IC chip 2 has a capacitance (for example, a capacitance touch) of a capacitance touch sensing wiring in a touch sensing mode for detecting contact of an object on the detection surface. You may provide the detection circuit 2B which detects the change of the electrostatic capacitance between the capacitive line C and the source wiring S) as a sensing wiring.

  Further, the liquid crystal display panel LPN of the illustrated example has a configuration applicable to the FFS mode or the IPS mode, and includes a pixel electrode PE and a common electrode CE on the array substrate AR. In the liquid crystal display panel LPN having such a configuration, a horizontal electric field (for example, an electric field substantially parallel to the main surface of the substrate in the fringe electric field) formed between the pixel electrode PE and the common electrode CE is mainly used. The liquid crystal molecules constituting the liquid crystal layer LQ are switched.

  FIG. 2 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN shown in FIG.

  That is, the array substrate AR is formed by using a first insulating substrate 10 having light transparency such as a glass substrate. The array substrate AR includes a switching element SW, a common electrode CE, a pixel electrode PE, and the like on an inner surface (that is, a surface facing the counter substrate CT) 10A of the first insulating substrate 10.

  The switching element SW shown here is a thin film transistor (TFT). The switching element SW includes a polysilicon semiconductor layer and an amorphous silicon semiconductor layer. Such a switching element SW is covered with the first insulating film 11.

  The common electrode CE is formed on the first insulating film 11. The common electrode CE is covered with the second insulating film 12. The second insulating film 12 is also disposed on the first insulating film 11. The pixel electrode PE is formed on the second insulating film 12. The pixel electrode PE is connected to the switching element SW through a contact hole that penetrates the first insulating film 11 and the second insulating film 12. Further, the pixel electrode PE has a slit PSL facing the common electrode CE through the second insulating film 12. Both the common electrode CE and the pixel electrode PE are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE is covered with the first alignment film AL1. The first alignment film AL1 is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate. The counter substrate CT has a black matrix 31, a color filter 32, an overcoat layer 33, and the like that partition each pixel PX as a dielectric thin film on the inner surface (that is, the surface facing the array substrate AR) 30 A of the second insulating substrate 30. It has.

  The black matrix 31 is formed on the inner surface of the second insulating substrate 30 so as to face the gate wiring G and the source wiring S provided on the array substrate AR, and further to the wiring section such as the switching element SW. The color filter 32 is formed on the inner surface of the second insulating substrate 30 and is formed of a resin material colored in a plurality of different colors, for example, three primary colors such as red, blue, and green. The resin material colored red is arranged corresponding to the red pixel. Similarly, the resin material colored blue is arranged corresponding to the blue pixel, and the resin material colored green corresponds to the green pixel. Are arranged.

  The overcoat layer 33 covers the black matrix 31 and the color filter 32. The overcoat layer 33 flattens the unevenness of the surfaces of the black matrix 31 and the color filter 32. Such an overcoat layer 33 is covered with the second alignment film AL2. The second alignment film AL2 is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a spacer (not shown) (for example, a columnar spacer integrally formed on one substrate with a resin material) is disposed between the array substrate AR and the counter substrate CT, thereby forming a predetermined gap. Is done. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a predetermined gap is formed. The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules enclosed in a gap formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT. .

  A backlight (not shown) is arranged on the back side of the liquid crystal display panel LPN having such a configuration. A first optical element OD1 including a first polarizing plate PL1 is arranged on one outer surface of the liquid crystal display panel LPN, that is, the outer surface 10B of the first insulating substrate 10 constituting the array substrate AR. The second optical element OD2 including the conductive layer CDF and the second polarizing plate PL2 is disposed on the other outer surface of the liquid crystal display panel LPN, that is, the outer surface 30B of the second insulating substrate 30 constituting the counter substrate CT. .

  The conductive layer CDF is a transparent conductive layer, and functions as an antistatic layer (or shield electrode) that prevents undesired charges from entering the liquid crystal display panel LPN from the outside. Such a conductive layer CDF may be directly formed on the outer surface 30B of the second insulating substrate 30, or may be formed on the surface of the second polarizing plate PL2.

  The first alignment film AL1 and the second alignment film AL2 are aligned in directions parallel to each other in a plane parallel to the main surface of the substrate. Therefore, in a state where no electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules included in the liquid crystal layer LQ are aligned in the plane with the alignment layers AL1 and AL2. Initial orientation in the processing direction. In a state where a fringe electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are aligned in a different direction from the initial alignment direction in the plane.

  In the liquid crystal display panel LPN having the above configuration, the array substrate AR is provided with various electrodes and various wirings, while the counter substrate CT is not provided with electrodes, and the black matrix 31, the color filter 32, and the overcoat layer 33. And a dielectric thin film such as a second alignment film AL2. For this reason, the counter substrate CT is more easily charged than the array substrate AR. About this point, the inventor confirmed by performing the following experiment.

  That is, the array substrate AR and the counter substrate CT before being bonded to each other were subjected to a discharge process for forcibly charging them, and the transition of the surface potential of each was measured. When the array substrate AR was subjected to a discharge treatment, the surface potential of the array substrate was maintained at almost zero volts even when it was forcibly charged, and there was no significant change. When the counter substrate CT was subjected to the discharge treatment, it was confirmed that the surface potential of the counter substrate CT was attenuated as time passed, and the surface potential of the counter substrate CT was attenuated as time passed. Further, it was confirmed that the surface potential of the counter substrate CT and the attenuation rate thereof depend on the material of the dielectric thin film that constitutes the counter substrate CT. From this experiment, it was confirmed that the counter substrate CT is more easily charged than the array substrate AR.

  When the counter substrate CT is charged in the process of manufacturing the counter substrate CT, the charge accumulated in the counter substrate CT is confined when bonded to the array substrate AR, and the charge may be released to the outside. It becomes impossible. When the electric charge accumulated in the counter substrate CT is localized, dielectric polarization of the dielectric thin film of the counter substrate CT occurs.

  For example, the second alignment film AL2 originally has an alignment regulating force that aligns liquid crystal molecules along the alignment treatment direction. However, when local dielectric polarization occurs in the second alignment film AL2, there may be an alignment regulating force that aligns liquid crystal molecules in a direction different from the alignment processing direction in that region. For this reason, in the liquid crystal layer LQ, alignment defects in which the alignment of liquid crystal molecules is locally disturbed may occur, and display unevenness may be induced. The inventor confirmed this phenomenon by conducting the following experiment.

  That is, the liquid crystal display panel LPN in which display unevenness is confirmed is disassembled, the counter substrate CT is taken out, and washed to remove the liquid crystal material. The liquid crystal material was dropped on the counter substrate CT when the counter substrate CT was charged and when it was not charged, and the alignment state of the liquid crystal molecules was observed with a polarizing microscope.

  When the counter substrate CT was not charged, a good dark field was observed when the polarizing plane was observed with a polarizing microscope under the condition of crossed Nicols. Thereby, it was confirmed that the liquid crystal molecules on the counter substrate CT were aligned along the alignment processing direction by the original alignment regulating force of the second alignment film AL2.

  On the other hand, when the counter substrate CT is charged, the polarization plane is observed with a polarizing microscope under a crossed Nicols condition. Immediately after the charging, alignment defects in which liquid crystal molecules are aligned in various directions occur, and light leakage occurs. Was confirmed. Further, although the surface potential of the counter substrate CT is attenuated as time elapses, even after the surface potential is sufficiently attenuated, the alignment defect of the liquid crystal molecules remains locally, and a minute bright spot (in the pixel) (Bright spot) was confirmed.

  The generation mechanism of such a bright spot is presumed as follows. First, as the counter substrate CT is once charged, dielectric polarization occurs in the second alignment film AL2, and alignment failure of liquid crystal molecules occurs. Light leakage occurs in a region in which the liquid crystal molecules are aligned in a direction different from the alignment direction that should be aligned. The dielectric polarization generated in such a small region of the second alignment film AL2 is maintained regardless of the attenuation of the surface potential. In a very small region where dielectric polarization occurs, it is presumed that the alignment failure of the liquid crystal molecules is difficult to alleviate over time, and the light leakage state continues and is observed as a fine bright spot.

  From the experiments by the inventors as described above, it is necessary to prevent the counter substrate CT from being charged as much as possible (or to be sufficiently discharged even if it is charged) before it is bonded to the array substrate AR. Therefore, in the present embodiment, the liquid crystal display panel LPN is manufactured by the following method.

  FIG. 3 is a flowchart for explaining a manufacturing method of the liquid crystal display panel LPN of this embodiment.

  First, an array substrate AR including a switching element SW, a common electrode CE, a pixel electrode PE, a first alignment film AL1, and the like is prepared on the first insulating substrate 10 (ST1).

  On the other hand, dielectric thin films such as the first conductive layer CDF1 formed on the outer surface 30B of the second insulating substrate 30 and the black matrix 31, the color filter 32, and the overcoat layer 33 formed on the inner surface 30A of the second insulating substrate 30. The counter substrate CT provided with is prepared (ST2). At this time, the formation order of the first conductive layer CDF1 and the dielectric thin film is not particularly limited, but in order to prevent charging in the process of forming the dielectric thin film, the first conductive layer is formed prior to the formation of the dielectric thin film. It is effective to form the layer CDF1.

  The first conductive layer CDF1 is an organic conductive layer, for example, and is formed by coating the outer surface 30B of the second insulating substrate 30 in the step of preparing the counter substrate CT. As a material for forming the organic conductive layer, for example, a material obtained by mixing a binder resin and a dispersant with polythiophene, which is a conductive substance, is applicable. The film thickness of the first conductive layer CDF1 formed by coating such a material is, for example, 0.2 to 0.3 μm. The first conductive layer CDF1 may be electrically connected to a specific terminal such as being grounded. However, the first conductive layer CDF1 is in an electrically floating state in order to prevent local charging (or equalize charge). It may be.

  Then, the counter substrate CT prepared in this way is introduced into the transport system, and is introduced into the cleaning process or the like as necessary.

  Subsequently, an alignment film material is formed on the dielectric thin film of the counter substrate CT (ST3). As such an alignment film material, for example, polyimide or the like is applicable. Thereafter, the formed alignment film material is fired.

  Subsequently, an alignment process is performed on the alignment film material (ST4). The alignment process may be a rubbing process or a photo-alignment process. Thereby, the second alignment film AL2 subjected to the alignment process in a predetermined direction is formed. Such a second alignment film AL2 is also one of the dielectric thin films. Then, the counter substrate CT that has already been formed up to the second alignment film AL2 is introduced into a cleaning process or the like.

  Subsequently, the array substrate AR and the counter substrate CT are bonded together using a sealing material (ST5). The liquid crystal layer LQ may be formed by dropping a suitable amount of liquid crystal material into the array substrate AR or the counter substrate CT before the array substrate AR and the counter substrate CT are bonded together. It may be formed by injecting a liquid crystal material from a liquid crystal injection port formed by a sealing material after being bonded to the counter substrate CT.

  In the manufacturing process shown in FIG. 3, the counter substrate CT is formed by the first conductive layer CDF <b> 1 formed on the second insulating substrate 30 in all steps including manufacturing the counter substrate CT and bonding the substrate to the array substrate AR. It becomes possible to prevent electrification of CT or to localize charges in the counter substrate CT. For this reason, it is not necessary to reinforce equipment such as an ionizer, and capital investment can be suppressed.

  FIG. 4 is a schematic cross-sectional view for explaining the manufacturing method of the liquid crystal display panel LPN of this embodiment.

  That is, in the step shown in (a), first, an array substrate AR formed up to the first alignment film AL1 and a counter substrate CT formed up to the second alignment film AL2 are prepared. The prepared counter substrate CT includes a first conductive layer CDF1 on the outer surface 30B of the second insulating substrate 30. Then, in the step shown in (b), the array substrate AR and the counter substrate CT are bonded together while the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT.

  In the step shown in (c), the first insulating substrate 10 constituting the array substrate AR and the second insulating substrate 30 constituting the counter substrate CT are polished. At this time, as a matter of course, the first conductive layer CDF1 on the outer surface 30B of the second insulating substrate 30 is also removed. Such polishing may be mechanical polishing, chemical polishing, or a combination thereof. By such polishing, the thickness of the first insulating substrate 10 and the second insulating substrate 30 becomes half or less before the polishing. For example, the thickness of the first insulating substrate 10 and the second insulating substrate 30 before polishing is 0.5 mm, and the thickness of the first insulating substrate 10 and the second insulating substrate 30 after polishing is 0.2 mm.

  In the step shown in (d), a transparent second conductive layer CDF2 is formed on the outer surface 30B of the second insulating substrate 30. The second conductive layer CDF2 may be an organic conductive layer similar to the first conductive layer CDF1, or may be formed using ITO or IZO for forming the pixel electrode PE or the like. The second conductive layer CDF2 thus formed corresponds to the conductive layer CDF described with reference to FIG.

  Thereby, the liquid crystal display panel LPN is completed. The thickness of the liquid crystal display panel LPN manufactured through such processes is thinner than the thickness at the stage shown in FIG. 5B by the amount of polishing of the first insulating substrate 10 and the second insulating substrate 30.

  In the manufacturing process shown in FIG. 4, since the first conductive layer CDF1 or the second conductive layer CDF2 is formed on the outer surface 30B of the second insulating substrate 30 except for the polishing step, the counter substrate CT is charged. It becomes possible to prevent or localize electric charges in the counter substrate CT.

  Therefore, in the liquid crystal display panel LPN manufactured in this way, it is possible to suppress the occurrence of alignment failure due to the dielectric polarization of the dielectric thin film of the counter substrate CT. Thereby, it is possible to suppress a decrease in yield and a decrease in display quality.

  In the manufacturing process described above, the first conductive layer CDF1 formed on the outer surface 30B of the second insulating substrate 30 preferably has a surface resistance value of 1 GΩ / □ or less. When the liquid crystal display panel LPN is formed through the series of steps shown in FIGS. 3 and 4, the first conductive layer CDF1 is removed in the polishing step. In other words, the first conductive layer CDF1 realizes prevention of charging of the counter substrate CT or prevention of localization of electric charges during the period from the manufacturing process of the counter substrate CT to the polishing process. In order to realize these, the first conductive layer CDF1 only needs to have a conductivity sufficient to diffuse the charge that has entered the counter substrate CT into the surface. It was confirmed that even a high resistance was acceptable, and as a result of various experiments, the upper limit value of the surface resistance value of the first conductive layer CDF1 was set to 1 GΩ / □.

  The manufacturing method of the liquid crystal display panel LPN described in the present embodiment is also applicable to a case where so-called multiple chamfering in which a plurality of liquid crystal display panels LPN are collectively formed using a large substrate is employed.

  That is, the series of steps shown in FIG. 3 is performed using a mother substrate. In step ST1, a first mother substrate for forming an array substrate is prepared. The first mother substrate has a first effective area corresponding to a plurality of array substrates. Each of the first effective areas includes a pixel electrode, a common electrode, and the like.

  In step ST2, a second mother substrate for forming a counter substrate is prepared. The second mother substrate has a second effective area corresponding to a plurality of counter substrates. Each of the second effective regions includes a dielectric thin film such as a black matrix 31, a color filter 32, and an overcoat layer 33. A first conductive layer CDF1 is formed on the outer surface of the second mother substrate.

  In step ST3 and step ST4, the second alignment film AL2 is formed on the dielectric thin film formed in each second effective region of the second mother substrate. In step ST5, a mother substrate pair in which the first mother substrate and the second mother substrate are bonded together is created.

  Then, the mother substrate pair that has undergone the series of steps shown in FIG. 4 is cleaved to cut out a single liquid crystal display panel LPN. In the liquid crystal display panel LPN manufactured in this way, as in the above example, it is possible to suppress the occurrence of alignment failure due to dielectric polarization, and to suppress the decrease in yield and display quality. It becomes possible.

  In addition, in step ST2 shown in FIG. 3, when the counter substrate CT is prepared using the already-thinned second insulating substrate 30, the polishing step shown in (c) may be omitted. In this case, the first conductive layer CDF1 remains on the outer surface 30B of the second insulating substrate 30 without being removed, and becomes an antistatic film. For this reason, the formation process of the 2nd conductive layer shown in (d) can be omitted. In this case, a transparent conductive layer is applied as the first conductive layer CDF1.

  As described above, according to the present embodiment, it is possible to provide a method for manufacturing a liquid crystal display device, a liquid crystal display device, and a counter substrate that can suppress a decrease in yield and a decrease in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate ACT ... Active area PX ... Pixel SW ... Switching element PE ... Pixel electrode PSL ... Slit CE ... Common electrode LQ ... Liquid crystal layer OD1 ... First optical element OD2 ... Second optical Element CDF ... conductive layer (CDF1 ... first conductive layer CDF2 ... second conductive layer)

Claims (5)

On the first insulating substrate, a first mother substrate including a plurality of first substrates including a common electrode formed over a plurality of pixels and a pixel electrode formed in each pixel is prepared,
A first substrate comprising a plurality of second substrates each including a first conductive layer formed on the outer surface of the second insulating substrate and a dielectric thin film formed on the inner surface of the second insulating substrate after forming the first conductive layer . Prepare two mother boards ,
Forming an alignment film material on the dielectric thin film of the second mother substrate;
An alignment treatment is performed on the alignment film material,
The first mother substrate and the second mother substrate are bonded together ,
After the bonding, the first mother substrate and the second mother substrate are polished, the first conductive layer is removed, and the thickness of each of the first insulating substrate and the second insulating substrate is reduced to a half before polishing. A method for manufacturing a liquid crystal display device, comprising:   The method of manufacturing a liquid crystal display device according to claim 1, wherein the first conductive layer is an organic conductive layer.   The method for manufacturing a liquid crystal display device according to claim 1, wherein the first conductive layer has a surface resistance value of 1 GΩ / □ or less. A liquid crystal material is dropped on the first mother substrate or the second mother substrate before the bonding, or a liquid crystal material is injected between the first mother substrate and the second mother substrate after the bonding. The method for manufacturing a liquid crystal display device according to claim 1, wherein: 2. The method of manufacturing a liquid crystal display device according to claim 1 , further comprising forming a transparent second conductive layer on the outer surface of the second insulating substrate after the polishing.

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