JP5733943B2 - Method for manufacturing dielectric device - Google Patents

Description

  The present invention relates to a method for manufacturing a dielectric device such as a piezoelectric element.

In recent years, MEMS (Micro Electro Mechanical Systems) technology has been further developed, and the application range of MEMS technology such as inkjet printer heads, acceleration sensors, and HDD (Hard Disk Drive) head microactuators has expanded. For example, ferroelectrics such as lead zirconate titanate (Pb (Zr, Ti) O ₃ , PZT) having excellent piezoelectric properties have been actively studied for application to MEMS as mechanical-electrical conversion elements. .

This type of piezoelectric element has a structure in which a ferroelectric is sandwiched between a pair of electrodes. As the electrode material, a noble metal such as Pt (platinum) or Ir (iridium), or a conductive oxide such as lanthanum nickelate (LNO: LaNiO ₃ ) or strontium ruthenate (SRO: SrRuO ₃ ) is used. For electrode processing, wet etching with a chemical solution is mainly used (see Patent Document 1). A method of etching an LNO electrode by dry etching using a mixed gas of chlorine and argon is also known (see Patent Document 2).

JP 2007-227752 (paragraph [0035]) JP 2009-206329 A (paragraph [0042])

  However, since the electrode material of the piezoelectric element has a low etching rate and low selectivity with a mask, there is a problem that workability is very poor. In particular, LNO has a problem in that it is difficult to secure an etching rate, and oxygen in the film is released during etching, thereby increasing the etching rate of the resist.

  In view of the circumstances as described above, an object of the present invention is to provide a dielectric device manufacturing method capable of obtaining good etching selectivity with respect to a mask while ensuring an etching rate.

In order to achieve the above object, a method for manufacturing a dielectric device according to an aspect of the present invention includes a step of forming an electrode layer including a conductive oxide layer and a metal layer on a dielectric layer.
A resist mask is formed on the electrode layer.
The electrode layer is etched through the resist mask by plasma of an etching gas containing at least one of a chlorine-based gas and a fluorocarbon-based gas.

It is a schematic process drawing explaining the manufacturing method of the dielectric device which concerns on one Embodiment of this invention. It is the schematic of the dry etching apparatus used in one Embodiment of this invention. It is one experimental result which shows the relationship between chlorine-type etching gas and a LNO etching rate. It is one experimental result which shows the gas type dependence of the etching gas which influences the LNO etching rate and the etching selectivity with a resist mask. It is one experimental result which shows the gas species dependence of the etching gas which affects the etching rate of LNO, SRO, and a resist mask.

The manufacturing method of the dielectric device which concerns on one Embodiment of this invention includes the process of forming the electrode layer containing a conductive oxide layer and a metal layer on a dielectric material layer.
A resist mask is formed on the electrode layer.
The electrode layer is etched through the resist mask by plasma of an etching gas containing at least one of a chlorine-based gas and a fluorocarbon-based gas.

  In the above dielectric device manufacturing method, an etching gas containing at least one of a chlorine-based gas and a fluorocarbon-based gas is used as an etching gas. By performing dry etching using plasma of this etching gas, the metal layer and the conductive oxide layer constituting the electrode layer are sequentially etched. Further, by using this kind of etching gas, it is possible to obtain good etching selectivity with respect to the resist mask while ensuring the etching rate of the electrode layer.

  The conductive oxide layer is formed of, for example, lanthanum nickelate (LNO), strontium ruthenate (SRO), or the like. The metal layer is made of, for example, platinum (Pt), iridium (Ir), or the like. By forming the conductive oxide layer between the dielectric layer and the metal layer, the conductive oxide layer functions as a barrier film that prevents the reducing action of the dielectric layer due to these interface reactions.

The etching gas may be a mixed gas of a chlorine-based gas and a fluorocarbon-based gas. For example, BCl ₃ can be used for the chlorine-based gas, and C ₄ F ₈ can be used for the fluorocarbon-based gas, for example. These may be mixed with an inert gas such as argon. Thereby, a high etching rate and a high mask selectivity of the electrode layer can be obtained.

  By setting the mixing ratio of the fluorocarbon-based gas in the mixed gas to 50% or less, the etching rate of the electrode layer and the etching selectivity with respect to the resist mask can be greatly improved.

The dielectric layer is formed of lead zirconate titanate (PZT: Pb (Zr, Ti) O ₃ ), so that a piezoelectric element having excellent piezoelectric characteristics can be manufactured. In addition to this, the dielectric layer includes bismuth strontium tantalate (SBT: SrBi ₂ Ta ₂ O ₉ ), bismuth titanate (BTO: Bi ₄ Ti ₃ O ₁₂ ), bismuth lanthanum titanate (BLT: (Bi, Other ferroelectrics such as La) ₄ Ti ₃ O ₁₂ ) and lanthanum-doped lead zirconate titanate (PLZT: (PbLa) (ZrTi) O ₃ ) may be used.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic process diagram illustrating a method for manufacturing a dielectric device according to an embodiment of the present invention. In the present embodiment, a piezoelectric element having a structure in which a ferroelectric layer is sandwiched between a pair of electrodes will be described as an example of a dielectric device.

  The method for manufacturing a piezoelectric element according to the present embodiment includes a laminate manufacturing process, an upper electrode layer etching process, and a ferroelectric layer etching process.

[Manufacturing process of laminate]
FIG. 1A illustrates a manufacturing process of a substrate. In this step, a laminated body L having a laminated structure of the lower electrode layer 2, the dielectric layer 3, and the upper electrode layer 4 is produced on the substrate 1. The substrate 1 may be a glass substrate or a semiconductor substrate such as a silicon substrate.

  The lower electrode layer 2 is composed of a laminated film of a metal layer 2a and a conductive oxide layer 2b. The metal layer 2a is formed of Pt (platinum), Ir (iridium) or the like. The conductive oxide layer 2b is formed of LNO (lanthanum nickelate), SRO (strontium ruthenate), or the like. The conductive oxide layer 2b is formed of the dielectric layer 3 and the metal layer 2a, and functions as a barrier film that prevents the reducing action of the dielectric layer 3 due to these interface reactions. The metal layer 2a and the conductive oxide layer 2b are formed by a thin film forming method such as a sputtering method or a CVD method. The thickness of the lower electrode layer 2 is not particularly limited and is, for example, 0.05 to 0.30 μm.

The dielectric layer 3 is made of PZT (lead zirconate titanate). In addition, bismuth strontium tantalate (SBT: SrBi ₂ Ta ₂ O ₉ ), bismuth titanate (BTO: Bi ₄ Ti ₃ O ₁₂ ), bismuth lanthanum titanate (BLT: (Bi, La) ₄ Ti ₃ O ₁₂ ) The dielectric layer 3 may be formed of other ferroelectric materials such as lanthanum-doped lead zirconate titanate (PLZT: (PbLa) (ZrTi) O ₃ ). The dielectric layer 3 is formed by a thin film forming method such as a sputtering method, a CVD method, or a sol-gel method. The thickness of the dielectric material layer 3 is not specifically limited, For example, it is 0.5-5.0 micrometers.

  The upper electrode layer 4 is composed of a laminated film of a conductive oxide layer 4b and a metal layer 4a. The conductive oxide layer 4b is formed of LNO (lanthanum nickelate), SRO (strontium ruthenate), or the like. The metal layer 4a is formed of Pt (platinum), Ir (iridium) or the like. The conductive oxide layer 4b functions as a barrier film that prevents the reducing action of the dielectric layer 3 due to the interface reaction by forming the dielectric layer 3 and the metal layer 4a. The metal layer 4a and the conductive oxide layer 4b are formed by a thin film forming method such as a sputtering method or a CVD method. The thickness of the upper electrode layer 4 is not particularly limited, and is 0.05 to 0.30 μm, for example.

[Upper electrode layer etching process]
1B and 1C show the etching process of the upper electrode layer 4. As shown in FIG. 1B, a resist mask 5 having a predetermined shape is formed on the upper electrode layer 4. The resist mask 5 is patterned into a predetermined shape through processing such as application of a photosensitive organic photoresist (PR), exposure, and development. The photoresist may be a dry film resist. The thickness of the resist mask 5 is not specifically limited, For example, it is 1.0-10.0 micrometers. The resist mask 5 only needs to have a thickness necessary for etching the upper electrode layer 4.

  Next, as shown in FIG. 1C, the upper electrode layer 4 is etched through the resist mask 5. For the etching process of the upper electrode layer 4, a dry etching apparatus having a configuration as shown in FIG. 2 is used.

  The dry etching apparatus 10 has a vacuum chamber 11. The vacuum chamber 11 is connected to a vacuum pump 12 and can maintain the inside in a predetermined reduced pressure atmosphere. Inside the vacuum chamber 11, a stage 13 for supporting the substrate 1 on which the laminate L is formed is installed. The stage 13 is connected to the high frequency power supply 15 via the matching circuit 14 so that a predetermined bias power can be input to the stage 13. A chiller 16 is further connected to the stage 13, and the substrate 1 on the stage 13 can be cooled to a predetermined temperature by the cooled He gas.

  The top surface portion of the vacuum chamber 11 facing the upper surface of the stage 13 is covered with a window 17 made of a dielectric material such as quartz, and an antenna coil 18 is installed immediately above the window 17. The antenna coil 18 is supplied with power from the high-frequency power source 20 via the matching circuit 19 and generates plasma of the etching gas introduced into the vacuum chamber 11 via the gas introduction line 21. Thereby, the surface of the substrate 1 on the stage 13 is etched. Around the stage 13, an adhesion preventing plate 22 for preventing the adhesion of the etching reaction product to the inner wall surface of the vacuum chamber 11 is installed.

  For the etching of the upper electrode layer 4, an etching gas containing at least one of a chlorine-based gas and a fluorocarbon-based gas is used. The etching conditions are not particularly limited. For example, the pressure is 0.5 Pa, the gas introduction amount is 20 sccm, the antenna power (power supplied to the antenna coil 18) is 600 W, and the bias power (power supplied to the stage 13) is 500 W. The chiller temperature (substrate temperature) is 20 ° C.

Examples of the chlorine-based gas include Cl ₂ and BCl ₃ . Examples of the fluorocarbon-based gas include fluorocarbon-based gases such as CF ₄ and C ₄ F ₈ and hydrofluorocarbon-based gases such as CHF ₃ . As an etching gas, an inert gas such as argon may be mixed with these gases. The metal layer 4a and the conductive oxide layer 4b can be sequentially etched by these etching gases. At this time, the metal layer 4a is etched at a higher etching rate than the conductive oxide layer 4b.

FIG. 3 shows an experimental result when LNO used as the constituent material of the conductive oxide layer 4b is etched with a chlorine-based etching gas. Using a mixed gas of BCl ₃ and Ar as an etching gas, the relationship between the flow rate ratio of BCl ₃ and the etching rate was confirmed. The etching conditions were a pressure of 0.3 Pa, a total gas flow rate of 50 sccm, an antenna power of 600 W, a bias power of 500 W, and a chiller temperature of 20 ° C.

As shown in FIG. 3, a high etching rate of 80 nm / min or more can be obtained at a flow rate ratio of BCl ₃ of 50% or more.

  The etching gas may be a mixed gas of a chlorine-based gas and a fluorocarbon-based gas. These may be mixed with an inert gas such as argon. Thereby, a high etching rate and a high mask selectivity of the electrode layer can be obtained.

When a mixed gas of a chlorine-based gas and a fluorocarbon-based gas is used as an etching gas, the mixing ratio of the fluorocarbon-based gas in the mixed gas can be 50% or less. For example, when the chlorine-based gas is BCl ₃ and the fluorocarbon-based gas is C ₄ F ₈ , the etching rate of the electrode layer and the etching selectivity with respect to the resist mask can be reduced by setting the mixing ratio of C ₄ F ₈ to 50% or less. Can be greatly improved.

FIG. 4 is a result of an experiment showing the dependency of the etching gas on the etching rate of LNO and the etching selectivity with the resist mask 5. As gas types, various mixed gases of Ar / SF ₆ (flow rate ratio 1: 1), Ar / BCl ₃ (flow rate ratio 1: 1) and C ₄ F ₈ / BCl ₃ (flow rate ratio 1: 1) were used. . The etching conditions were a pressure of 0.3 Pa, a total gas flow rate of 50 sccm, an antenna power of 600 W, a bias power of 500 W, and a chiller temperature of 20 ° C.

As shown in FIG. 4, regarding the etching rate of LNO, it is found that the Ar / BCl ₃ mixed gas and the C ₄ F ₈ / BCl ₃ mixed gas are much higher than the Ar / SF ₆ mixed gas. It can also be seen that the etching selectivity with the resist mask 5 is higher in the C ₄ F ₈ / BCl ₃ mixed gas than in the Ar / BCl ₃ mixed gas. By using a C ₄ F ₈ / BCl ₃ mixed gas as an etching gas, a high mask selection ratio of 0.25 or more can be obtained.

  As described above, the etching rate of LNO and the selection ratio with the resist mask differ greatly depending on the type of etching gas. In particular, a chlorine-based gas is highly effective in improving the etching rate, and a fluorocarbon-based gas is highly effective in improving the selection ratio with a resist mask. Therefore, a mixed gas of a chlorine-based gas and a fluorocarbon-based gas is used as an etching gas. Therefore, it is possible to achieve both the LNO etching rate and the mask selection ratio. In this case, the target etching rate and mask selection ratio can be obtained by appropriately adjusting the flow rate ratio between the chlorine-based gas and the fluorocarbon-based gas.

Next, FIG. 5 shows an experimental result of an etching rate and a resist mask selection ratio when SRO used as a constituent material of the conductive oxide layer 4b is etched with various etching gases. As the gas species, a single gas or a mixed gas of CF ₄ , CHF ₃ , BCl ₃ and C ₄ F ₈ / BCl ₃ (flow rate ratio 1: 1) was used. The etching conditions were a pressure of 0.5 Pa, a total gas flow rate of 20 sccm, an antenna power of 600 W, a bias power of 500 W, and a chiller temperature of 20 ° C.

As shown in FIG. 5, with respect to the etching rate of SRO, a constant etching rate is ensured even with a relatively low rate of 40 to 50 nm / min with fluorocarbon gases (CF ₄ and CHF ₃ ). . The mask selectivity was 0.10 for CF ₄ gas and 0.18 for CHF ₃ gas. When the etching rate of LNO by the same gas was confirmed, it was the same level as SRO.

On the other hand, with respect to the etching rate of SRO when a chlorine-based gas (BCl ₃ , C ₄ F ₈ / BCl ₃ ) is used, a relatively high rate of 70 to 80 nm / min can be obtained. 0.16 ₃ gas was relatively high and so C ₄ F ₈ / BCl ₃ gas mixture at 0.23.

  From the above results, it was confirmed that a constant etching rate and mask selectivity can be obtained with chlorine-based gas and / or fluorocarbon-based gas even for SRO. In particular, by using a mixed gas of a chlorine-based gas and a fluorocarbon-based gas as an etching gas, a high etching rate of 70 nm or more and a high mask selectivity of 0.2 or more can be obtained.

[Dielectric layer etching process]
After the etching process of the upper electrode layer 4 is completed, the etching process of the dielectric layer 3 is performed. FIG. 1D shows an etching process of the dielectric layer 3. In this step, the resist mask 5 used as an etching mask for the upper electrode layer 4 may be used as an etching mask for the dielectric layer 3, or a resist mask formed separately may be used. Alternatively, the patterned upper electrode layer 4 may be used as an etching mask for the dielectric layer 3.

A dry etching method is employed for etching the dielectric layer 3, but a wet etching method may be employed. In this embodiment in which the dielectric layer 3 is formed of PZT, for example, a C ₄ F ₈ / SF ₆ mixed gas is used as the etching gas for the dielectric layer 3. As an etching apparatus, the dry etching apparatus 10 shown in FIG. 2 is applicable. The etching conditions are not particularly limited. For example, the pressure is 0.5 Pa, the total gas flow rate is 22.5 sccm, the antenna power is 600 W, the bias power is 300 W, and the chiller temperature is 20 ° C.

  After the etching process of the dielectric layer 3 is completed, the resist mask is removed, so that the piezoelectric element P (FIG. 1D) is manufactured on the substrate 1. The lower electrode layer 2 may be patterned as necessary. Alternatively, the dielectric layer 3 may be annealed after the dielectric layer 3 is etched. The piezoelectric element P is used for, for example, an inkjet nozzle head, a micro mirror, a vibration power generation element, an acceleration sensor, an angular velocity sensor, and the like.

  The embodiment of the present invention has been described above, but the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

  For example, in the above-described embodiment, the piezoelectric element is described as an example of the dielectric device. However, the present invention is not limited to this, and the present invention can be applied to various electronic devices such as a ferroelectric memory element and a capacitor.

  In the above embodiment, the lower electrode layer 2 of the piezoelectric element has a laminated structure of the metal layer 2a and the conductive oxide layer 2b. However, the lower electrode layer may be formed of a single metal layer.

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Lower electrode layer 3 ... Dielectric layer 4 ... Upper electrode layer 5 ... Resist mask 10 ... Dry etching apparatus

Claims (2)

On the dielectric layer, a conductive oxide layer made of either lanthanum nickelate (LNO) or strontium ruthenate (SRO), and any one of platinum (Pt) or iridium (Ir) Forming an electrode layer including a metal layer;
Forming a resist mask on the electrode layer;
The etching selectivity of the resist mask and the electrode layer is set to 0.2 or more by plasma of an etching gas containing BCl ₃ and C ₄ F _{8 in} which the mixing ratio of C ₄ F ₈ is 50% or less. A method for manufacturing a dielectric device, wherein the electrode layer is etched. A method of manufacturing a dielectric device according to claim 1,
The dielectric layer is formed of lead zirconate titanate Dielectric device manufacturing method.

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