JP5729707B2 - Semiconductor device on substrate coated with diffusion barrier and method of forming the same - Google Patents

Description

  The present invention relates generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to a semiconductor device formed on a metal substrate covered with a diffusion barrier and a method for forming the same.

[Priority information]
This application claims the priority of US Provisional Application No. 61/181953 filed on May 28, 2009 (Attorney Docket Number IDR3021), the contents of which are hereby incorporated by reference. Incorporated.

  A semiconductor product can be flexibly manufactured by forming a semiconductor device using a metal foil substrate (for example, stainless steel, aluminum, copper, etc.). In addition, by using a metal foil substrate, it is possible to perform high temperature processing of electronic device layers, structures and / or formed devices without significantly degrading the properties of the metal foil substrate. However, if the composition of the metal foil substrate (for example, in the case of a stainless steel substrate, iron and atoms of alloy elements such as chromium, nickel, molybdenum, niobium, etc.) has a sufficiently high diffusivity, the metal foil substrate may be During the temperature process, constituent atoms diffuse from the metal foil substrate to one or more electronic device (eg, semiconductor or dielectric) layers, structures, and / or devices formed therein, which degrades electrical properties. There was a case where I was allowed to.

  FIG. 1 shows a thin film transistor (TFT) 5 as an example of a semiconductor device. The insulating layer 20 is disposed between the metal foil substrate 10 and the semiconductor unit 30. The semiconductor portion 30 has a source region 60 and a drain region 70 formed therein, and the gate stack includes a gate dielectric 40 and a gate electrode 50. In the annealing step, the TFT 5 on the substrate 10 is heated to a temperature sufficient to activate the dopant in the source region 60 and the drain region 70 and / or to at least partially crystallize the semiconductor portion 30. Also good. Thus, by making the temperature high (for example, a temperature exceeding 350 ° C., particularly a temperature exceeding 600 ° C.), the mobility of the metal atoms in the metal foil substrate 10 can be increased, and the diffusion distance of the metal atoms can be reduced. It is possible to make it the same as the thickness of the insulator. The active region (for example, the channel region and / or the source / drain region 60, 70 of the semiconductor part 30) and / or the gate of the TFT 5 passing through the insulating layer 20 from the substrate 10 as indicated by the arrow 80 in the figure. If metal atoms diffuse into the dielectric region 40, it is considered that the operating characteristics of the TFT 5 (for example, the threshold voltage of the TFT 5, the gradient below the threshold, the leakage current, and / or the on-current) are deteriorated. Therefore, the metal substrate 10 and the semiconductor layer 30 (or other device layers) are required to prevent diffusion of metal atoms from the substrate 10 through the insulating layer 20 and into the active region and / or the gate dielectric region 40 of the TFT 5. It is desirable to form a diffusion barrier between the two. In addition, even when metal atoms are added, the characteristics of the device layer change, which is undesirable, and the metal substrate 10 and device layers of other devices such as capacitors, diodes, inductors, resistors, etc. It is desirable to provide a diffusion barrier between them.

  In one aspect, the invention relates to an electrical device formed on a diffusion barrier that covers a metal substrate, the electrical device comprising a metal substrate, one or more diffusion barrier layers on the metal substrate, and one on the diffusion barrier layer. The above insulating layer and a semiconductor or other device layer on the insulating layer are provided.

  In another aspect, the invention relates to a method of forming an electrical device on a metal substrate, the method comprising forming one or more diffusion barrier layers on the metal substrate and one or more insulating layers on the diffusion barrier layer. And a step of forming a semiconductor or other device layer on the insulating layer.

  The present invention provides an electrical device formed on a metal substrate covered with a diffusion barrier and a method for forming the same. The diffusion barrier prevents diffusion of metal atoms from the metal substrate to the electrical device formed therein. These and other advantages of the present invention will become apparent from the detailed description set forth below.

A TFT formed on a metal substrate coated with an insulator is shown. It is the figure which illustrated the structure formed by the method of manufacturing TFT on the metal substrate coat | covered with the diffusion barrier which concerns on embodiment of this invention. It is the figure which illustrated the structure formed by the method of manufacturing TFT on the metal substrate coat | covered with the diffusion barrier which concerns on embodiment of this invention. It is the figure which illustrated the structure formed by the method of manufacturing TFT on the metal substrate coat | covered with the diffusion barrier which concerns on embodiment of this invention. It is the figure which illustrated the structure formed by the method of manufacturing TFT on the metal substrate coat | covered with the diffusion barrier which concerns on embodiment of this invention. It is the figure which illustrated the structure formed by the method of manufacturing TFT on the metal substrate coat | covered with the diffusion barrier which concerns on embodiment of this invention. It is the figure which illustrated another method of forming a diffusion barrier layer on a metal substrate. It is the figure which illustrated another method of forming a diffusion barrier layer on a metal substrate. It is the figure which illustrated another method of forming a diffusion barrier layer on a metal substrate. FIG. 6 illustrates a structure formed in a further example of a method of manufacturing a metal substrate covered with a diffusion barrier according to an embodiment of the present invention. FIG. 6 illustrates a structure formed in a further example of a method of manufacturing a metal substrate covered with a diffusion barrier according to an embodiment of the present invention. Expressed in function of the thickness of the SiO ₂ layer is a graph showing the decrease in the reflectivity of the AlN layer and the TiN layer under the SiO ₂ layer.

  Various embodiments of the invention will now be described in detail with reference to the examples illustrated in the accompanying drawings. While the invention will be described in conjunction with the following embodiments, it is to be understood that these descriptions are not intended to limit the invention to these embodiments. The invention is intended to cover alternatives, modifications and equivalents that fall within the spirit and scope of the invention as defined by the appended claims. In the following detailed description, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these details. In other instances, well known methods, processes, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

  In one aspect, the invention relates to an electrical device formed on a diffusion barrier that covers a metal substrate, the electrical device comprising: a metal substrate; at least one diffusion barrier layer on the metal substrate; and at least on the diffusion barrier layer. One insulating layer and at least one device layer (for example, a semiconductor layer) on the insulating layer are provided. In another aspect, the invention relates to a method of forming an electrical device on a metal substrate, the method comprising forming at least one diffusion barrier layer on the metal substrate and at least one insulating layer on the diffusion barrier layer. And forming at least one device layer (for example, a semiconductor layer) on the insulating layer.

  The present invention is described in detail with reference to examples of methods of forming electrical devices on a metal substrate coated with a diffusion barrier in various aspects of the present invention.

[Example of device on metal substrate coated with barrier]
FIG. 2A shows stainless steel (which can be any grade of stainless steel, eg, type 304, type 316, etc.) or typical processing temperatures associated with the manufacture of electrical devices (eg, above about 350 ° C. Metal substrate 210 composed of a slab, foil, or sheet of a metal or alloy of any other suitable element having a softening temperature that can sufficiently withstand a temperature or a temperature that is 350 ° C. or higher and lower than the softening temperature of the substrate. It is shown. In one embodiment, the metal is type 304 stainless steel, but any stainless steel alloy can be used. Alternatively, the metal substrate 210 may be made of, for example, a slab, foil, or sheet of aluminum, copper, titanium, or molybdenum. The metal substrate 210 may have a thickness of about 10 μm to about 1000 μm (eg, 10 μm to 500 μm, 50 μm to 200 μm, or other values and ranges of other values included in the above ranges). The metal substrate 210 may basically have any shape, and may be, for example, a square, a circle, an oval, an ellipse, or the like. Alternatively, the metal substrate 210 may have a predetermined irregular and / or patterned shape. In some embodiments, the metal substrate 210 may be square or rectangular, or a sheet containing xxy square or rectangular units, or 1 (eg, a display device, solar cell, ID tag, etc.). It may be a roll of a sheet having a width of x units with individual substrates corresponding to one integrated circuit as a unit.

  In general, the metal substrate 210 is cleaned before the diffusion barrier layer 220 is deposited. By cleaning, the diffusion barrier layer 220 such as residue, organic material residue, particles and / or other contaminants attached in the process of preparing the metal substrate 210 from stock is adhered to the surface of the metal substrate 210. Residues that can adversely affect the process can be removed. The cleaning of the metal substrate 210 may include wet cleaning and / or dry cleaning. In one example, the cleaning includes etching the surface of the metal substrate 210, and the etching may be followed by rinsing and / or drying of the metal substrate 210 as needed.

  Suitable etching techniques may include wet etching processes (eg, wet chemical etching) or dry etching (eg, reactive ion etching (RIE) or sputter etching). In one embodiment, after cleaning the metal substrate 210 by immersing the substrate in a liquid phase cleaning agent (eg, a cleaning agent that removes organic residues) and / or rinsing the substrate with the liquid phase cleaning agent, the diluted substrate is diluted. Wet etching is performed using an acidic aqueous solution (for example, dilute hydrofluoric acid aqueous solution buffered with ammonia and / or ammonium fluoride). Other acids that can be used to wet etch the substrate 210 include nitric acid, sulfuric acid, hydrochloric acid, etc., selected according to the grade of steel or other metal used and the temperature at which the metal substrate 210 is processed. Is done. In another embodiment, the metal substrate 210 may be cleaned by sputter etching. The choice of gas used for dry etching for cleaning the metal substrate 210 is not particularly limited. Any gas and combination of gases may be employed that removes substantially all undesirable contaminants from the surface of the metal substrate 210 and leaves no residue that cannot be removed. For example, an inert gas such as argon may be used for sputter cleaning of the metal substrate 210.

After the etching, the metal substrate 210 is rinsed (for example, with pure water) and, if necessary, further immersed in an organic solvent or solvent mixture and / or rinsed with an organic solvent or solvent mixture to remove the metal substrate 210. Undesirable organic residues that may be present on the surface may be removed. Alternatively, further cleaning may be performed (after rinsing with pure water) by immersing in and / or rinsing with an aqueous solution or suspension of surfactant. For example, as a further cleaning, the metal substrate 210 may be treated with a cleaning solvent that does not chemically damage the steel. Examples of washing solvents include C ₆ -C ₁₂ alkanes (substituted with one or more halogens), C ₁ -C ₆ alkyl esters of C ₂ -C ₂₀ alkanoic acids, C ₂ -C ₆ dialkyl ethers, methoxy C _4- C ₆ alkanes, C ₂ -C ₄ alkylene glycols and C ₁ -C ₄ alkyl ethers and / or their C ₁ -C ₄ alkyl esters, (one or more C ₁ -C ₄ alkyl groups, C ₁ -C C ₆ -C ₁₀ arenes substituted with ₄ alkoxy groups, and / or halogen), and C ₂ -C ₆ alkylene or dialkylene ethers, thioethers (including sulfoxides and sulfone derivatives of thioethers), and esters (eg, tetrahydrofuran) , Dioxane, γ-propiolactone, δ-butyrolactone, and tetramethylene sulfone ). In one example, the cleaning solvent may include dipropylene glycol methyl ether acetate (DPGMEA) and / or tetramethylene sulfone (eg, KWIK STRIP cleaner from AZ Electronic Materials, Branchburg, NJ). Contains 65-70% DPGMEA and 35-40% tetramethylene sulfone).

  In some embodiments, the cleaning of the metal substrate 210 may be performed in a roll or sheet before the metal substrate 210 is cut or formed into a final shape to facilitate processing and handling. However, in other embodiments, the metal substrate 210 may be cut or formed prior to cleaning.

As shown in FIG. 2B, after the metal substrate 210 is cleaned, a diffusion barrier layer 220 is formed on the substrate. The diffusion barrier layer 220 preferably has a thickness that is greater than the total diffusion length (from the metal substrate 210) of the diffusion species at a given time and temperature. For example, the diffusion total length is formed between (1) a diffusion barrier layer of a diffusion species (at a specific / predetermined processing temperature), and a layer containing the diffusion species and a protective layer (eg, a layer covering the device layer). Measured by the product of the diffusivity through the other layers formed and (2) the length of time the structure is exposed to a specific / predetermined processing temperature. In various embodiments, the thickness of the diffusion barrier layer 220 is at least 5%, 10% or more greater than the diffusion length to which each diffusion species relates. This configuration minimizes the cost and overall manufacturing process impact so that the diffusion barrier layer 220 properly prevents the adverse effects of diffusion species even at relatively low processing temperatures. Thus, a diffusion barrier layer can be designed. One specific function of the diffusion barrier is that it is relatively significantly larger (typically more than an order of magnitude) compared to the diffusion rate of the diffusion species in the device layer located above the diffusion barrier. The diffusion rate can be lowered. The diffusion barrier layer 220 may include, for example, tungsten or a titanium alloy such as a tungsten-tantalum alloy or a tungsten-titanium alloy, or titanium or an aluminum compound such as titanium nitride, aluminum nitride, or titanium aluminum nitride. Instead, the diffusion barrier layer 220 includes silicon oxide, silicon nitride, silicon oxynitride (ie, Si _x O _y N _z , where x = 2y + [4z / 3]), alumina, titania (titanium oxide), Insulation including germania (germanium oxide) (GeO ₂ ), hafnia (hafnium oxide), zirconia (zirconium oxide), ceria (cerium oxide), and / or other rare earth oxides, combinations thereof, and nanolaminates thereof A partition may be included.

A compound containing titanium nitride and / or aluminum nitride can provide a relatively inexpensive barrier layer that is compatible with many different deposition methods. In some embodiments, the diffusion barrier layer 220 includes a titanium compound represented by Ti _x N _y and the ratio of x to y is about 3: 4 to about 3: 2. In one example, x and y are each about 1. In other embodiments, the diffusion barrier layer 220 includes titanium aluminum nitride represented by Ti _a Al _b N _c , where the ratio of (a + b) to c is from about 3: 4 to about 3: 2. It is. Usually, the ratio of a to b is about 1:10 to about 10: 1. In one example, a + b≈c and c = 1. Suitable compound conditions for use in the diffusion barrier layer 220 generally include (i) high resistance to diffusion of the compound from the metal substrate 210, and (ii) maximum processing for the device and / or structure being formed. Thermal stability below temperature (eg, temperatures above about 350 ° C. or any temperature above 350 ° C. and below the softening temperature of the metal substrate), (iii) for example, diffusion barrier layer 220 is metal substrate Adhesion to 210 and adhesion of insulating layer 230 to diffusion barrier layer 220; (iv) optical properties that allow simple inspection and / or establishment and / or detection of process windows (eg, optical constants) And / or reflectivity), (v) residual stress and thickness to the extent that the diffusion barrier layer 220 does not peel during high temperature processing (eg,> 350 ° C.). Accordingly, the stoichiometry (eg, x and y values, a, b and c values) of the employed tungsten alloy or titanium and / or aluminum compound is selected to optimize one or more of the above conditions. May be.

The diffusion barrier layer 220 is formed using well-known techniques such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition of a suitable precursor to the metal substrate 210 in a deposition chamber. Also good. In some embodiments, the diffusion barrier layer 220 deposits titanium and nitrogen from precursors such as, for example, TiCl ₄ , NH ₃ , Ti (NMe ₂ ) ₄ (TDMAT), or Ti (NEt ₂ ) ₄ (TDEAT). Including titanium nitride formed by atomic layer growth. In another embodiment, titanium nitride is formed by sputtering deposition from a titanium target under an atmosphere containing nitrogen and / or ammonia. Alternatively, titanium nitride can be formed by chemical vapor deposition from precursors such as TiMe ₄ or TiEt ₄ and N ₂ and / or NH ₃ . The titanium and nitrogen precursors introduced into the deposition chamber during the deposition of the diffusion barrier layer 220 using a CVD formed titanium nitride (ie, Ti _x N _y ) stoichiometry (eg, x and y values). It may be controlled by controlling the relative amount of.

In another embodiment, the diffusion barrier layer 220 comprises, for example, a mixture of the above titanium and nitrogen precursors and an aluminum precursor represented by AlH _n R _m (and optionally N ₂ and / or Or titanium aluminum nitride formed by alternating atomic layer deposition (ALD) of NH ₃ ), where R is a C ₁ -C ₄ alkyl group and n + m = 3. Suitable aluminum precursors include alane (AlH ₃ ), an alane-ammonia complex (AlH ₃ .NH ₃ ), an alane-trimethylamine complex (AlH ₃ .NMe ₃ ), triisobutylaluminum (TIBAL), and trimethylaluminum (TMA). , Triethylaluminum (TEA), or dimethylaluminum hydride (DMAH). The stoichiometry of titanium aluminum nitride (ie, the values of a, b and c in the formula Ti _a Al _b N _c ) is the precursor of titanium, aluminum and nitrogen introduced into the deposition chamber during the deposition of the diffusion barrier layer 220. It may be controlled by controlling the relative amount of the body.

  The diffusion barrier layer 220 (see FIG. 2B) has a thickness of about 1 nm to about 1 μm (eg, about 5 nm to 500 nm, about 10 nm to 250 nm, or other values and ranges of other values within the above ranges). . In one embodiment, the diffusion barrier layer 220 has a thickness of about 30 nm to about 150 nm. Alternatively, if the diffusion barrier layer 220 includes layers of titanium nitride and aluminum nitride deposited alternately by ALD, 2 to 10,000 layers (any value range included in the above range) are present. Each of the formed titanium nitride and aluminum nitride layers may have a thickness of 5 to 1200 inches. In further embodiments, layers in which conductor and insulator diffusion barrier materials are alternately deposited, or layers in which two or more different insulating diffusion barrier materials are alternately deposited, may be used. Alternately deposited with properties sufficient to prevent metal atoms from diffusing into the layers formed in the device layer formed by the methods disclosed herein or other methods known in the art. Any combination of layers or nanolaminates may be employed.

  In certain embodiments, the metal substrate 210 is substantially sealed by the diffusion barrier 220. For example, as shown in FIG. 2B, if the metal substrate 210 is diced, cut, or formed before or after the cleaning process and before the diffusion barrier layer 220 is deposited, the diffusion barrier layer 220. However, it may be formed so as to substantially seal the metal substrate 210 including the edge (in addition to the main surface) of the substrate.

If desired, an antireflective coating (not shown) may be deposited over the entire substrate (eg, on the metal substrate 210 or on the diffusion barrier layer 220) before or after the diffusion barrier layer 220 is deposited. Good. Examples of the antireflection film include silicon oxide, silicon nitride, silicon oxynitride, titania (titanium oxide), germania (germanium oxide) (GeO ₂ ), hafnia (hafnium oxide), zirconia (zirconium oxide), ceria (cerium oxide), Or an inorganic insulator such as one or more other metal oxides, or combinations and / or nanolaminates, from the preferred precursors described above, physical vapor deposition (PVD), chemical The deposition may be by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The antireflective coating may have a thickness of 50 to 1000 mm (eg, 50 to 200 mm, or any value within the above range). In one embodiment, the anti-reflective coating comprises a layer of silicon dioxide deposited by ALD. (See Oct. 10, 2008, U.S. Patent Application Publication No. 12 / 249,841 (Attorney Docket IDR1583), the related description is incorporated herein by reference).

Further, a stress relaxation layer (not shown) may be deposited on the entire substrate 210 before depositing the diffusion barrier layer 220 and the antireflection film. The stress relieving layer may include an organic material or an inorganic material capable of reducing the stress applied to the substrate 210, and an insulating film or a layer of a material (such as the barrier layer 220) is coated thereon. An antireflection film may be formed. The stress relaxation layer spin-codes, prints organic polymers such as poly (acrylic acid ester), poly (methacrylic acid ester), or copolymers thereof (using olefins such as ethylene, propylene, butylene). Alternatively, the film may be deposited by dip coating or the like. Instead, the stress relaxation layer is made of an oxide-based insulator (for example, silicon dioxide, aluminum oxide) and / or a single metal such as aluminum, titanium, or copper (and alloys thereof). Alternatively, it may be deposited from a suitable precursor as described above by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). . Oxide-based insulators and inorganic materials such as elemental metals and alloys are preferred because they are suitable for high temperature processing. Each of the stress buffer layers may have a thickness of 5 to 1000 inches (eg, 10 to 250 inches, or any range of values included in the above range). In one embodiment, the stress buffer layer includes a SiO ₂ : Al insulating layer (also known as a mixed oxide of SiO ₂ : Al ₂ O ₃ ) having a thickness of 10 to 250 inches. In another embodiment, the stress buffer layer comprises aluminum deposited by PVD (eg, sputtering) and has a thickness of 50 to 100 inches (any value range included in the above range). In one example, the combined thickness of the antireflection film and the stress buffer layer is about 150 mm.

  As shown in FIG. 2C, an insulating layer 230 is formed on the diffusion barrier layer 220. Insulating layer 230 may be comprised of any material that electrically insulates diffusion barrier layer 220 from adjacent electrical device structures and / or devices that may be subsequently formed. For example, the insulating layer 230 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, or a combination thereof. In one embodiment, the insulating layer 230 includes silicon dioxide and aluminum oxide.

The insulating layer 230 is formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or liquid deposition (eg, spin coating and curing as used in spin-on-glass processes). Also good. For example, in certain embodiments, the insulating layer 230 comprises silicon dioxide, tetraethylorthosilicate (TEOS) or silane (eg, SiH ₄ or SiCl ₂ H ₂ ) and an oxygen source (eg, O ₂ , O ₃ , N _2). O, NO, etc.) may be formed by chemical vapor deposition (eg, plasma CVD). In other embodiments, the insulating layer 230 includes silicon nitride, and chemical vapor deposition from a silicon source (eg, SiH ₄ or SiCl ₂ H ₂ ) and a nitrogen source (eg, NH ₃ and / or N ₂ ). May be formed. In further embodiments, the insulating layer 230 comprises silicon oxynitride and is a silicon source (eg, SiH ₄ ), a nitrogen and oxygen source (eg, NO ₂ , NO and / or N ₂ O), or a nitrogen source (eg, , NH ₃ and / or N ₂ ) and an oxygen source (O ₂ , O ₃ and / or N ₂ O) may be formed by chemical vapor deposition. In yet another embodiment, the insulating layer 230 includes aluminum oxide and / or aluminum nitride, an aluminum source (eg, trimethylaluminum, or other aluminum source as described herein), and an oxygen source ( For example, atomic layer deposition from O ₂ , O ₃ and / or water), nitrogen source (eg, NH ₃ and / or N ₂ ) and / or nitrogen / oxygen source (NO ₂ , NO and / or N ₂ O) May be formed. The insulating layer can be formed by atomic layer growth as described in US Patent Application Publication No. 12 / 249,841 (Attorney Docket IDR1583), filed Oct. 10, 2008, and related description. Is incorporated herein by reference.

  The insulating layer 230 can be formed in the same deposition chamber used to deposit the diffusion barrier layer 220, and may be formed immediately after the diffusion barrier layer 220 is deposited, if desired. Alternatively, the insulating layer 230 may be formed in a separate process and / or in a chamber separate from the diffusion barrier layer 220. The insulating layer 230 (see FIG. 2C) has a thickness of about 10 nm to about 10 μm (eg, about 50 nm to 5 μm, about 100 nm to 2 μm, or other values and ranges of other values within the above ranges). In one embodiment, the insulating layer 230 has a thickness of about 1 μm.

  The insulating layer 230 can also be coated or printed (e.g., spin coating, ink jet, drop casting, gravure printing, flexographic printing, spray coating, screen printing, offset printing, spin coating, slit coating, extrusion coating, dip coating, meniscus coating, Micro spotting, pen coating, stencil, stamp, syringe discharge, pump discharge, etc., filed on November 24, 2009, see US Patent Application Publication No. 12/625492 (Attorney Docket No. IDR0872), see related description Incorporated herein by reference). In some embodiments, the insulating layer 230 is formed by printing ink or a composition comprising an insulator or an insulator precursor (eg, screen printing, gravure printing, offset printing, inkjet printing, etc.). Also good. In many cases, after printing an ink or composition comprising an insulator ink and / or an insulator precursor to form the insulating layer 230, the printed layer is (optionally under vacuum). Heat to a temperature of about 50-150 ° C. to remove the solvent from the printed inks and compositions, and further (eg, at a temperature of about 300-600 ° C., optionally in an oxidizing or inert atmosphere) Heat or cure.

  In a further embodiment (not shown), the coated substrate may further comprise a configuration in which diffusion barrier layers and insulating layers are alternately deposited in succession. In such an embodiment, the coated substrate includes at least two diffusion barrier layers and at least two insulating layers that are interleaved (e.g., the bottommost diffusion barrier layer is disposed thereon, on which A lower insulating layer, an upper diffusion layer, and an upper insulating layer are formed in this order). In further embodiments, there may be three or more (eg, up to 100, 1000, or 10,000) structures in which diffusion barrier materials and insulating materials are alternately stacked. Each diffusion barrier layer may be the same as or different from another diffusion barrier, and each insulating layer may be the same as or different from another insulating layer. . Each diffusion barrier layer and each insulating layer has a thickness of about 0.5 nm to about 2 μm (eg, about 2 nm to about 1 μm, about 5 nm to about 250 nm, or other values, or other values within the above range). You may have. The diffusion barrier layer and insulating layer may be deposited by ALD, PVD (eg, sputtering), CVD, or other deposition methods described herein, or methods known in the art.

  As shown in FIG. 2D, the method further includes forming a device layer (eg, semiconductor layer) 240 on the insulating layer 230. If the device on the substrate 210 includes CMOS transistors (ie, includes at least one NMOS transistor and at least one PMOS transistor), the device layer 240 includes one or more first transistor island regions 240a and 1 You may have the above 2nd transistor island-like area | region 240b. The first transistor island region 240a is made of a semiconductor material of a first conductivity type (for example, one of NMOS or PMOS), and the second transistor island region 240b is made of the same or different semiconductor material, but the second conductivity type. It is made of a material having (for example, the other of NMOS or PMOS). Alternatively, the device layer 240 may include one or more gate electrodes (that is, a bottom gate structure), and the first gate electrode 240a includes a first semiconductor (eg, a first semiconductor having a first conductivity type). Material) or a first set of properties (eg, a metal having a first pattern or a first set of dimensions) and the second gate electrode 240b is a second composition (eg, a second having a second conductivity type). Semiconductor material) or a second set of properties (eg, a metal having a second pattern or second set of dimensions). In further embodiments, the device layer 240 may include one or more capacitor plates, one or more diode layers, one or more resistors, wiring, or the like.

  In certain embodiments, device layer 240 includes silicon and / or germanium. However, if the device layer 240 includes a semiconductor material, the device layer 240 is not limited to silicon and / or germanium, and a III-V type semiconductor (eg, GaAs, InP, and related compounds and / or alloys), II-VI type semiconductors (eg ZnO, ZnS, ZnS, ZnSe, CdTe and related compounds and / or alloys), organic semiconductors (eg poly [thiafulvalene-based semiconductors]) or compatible with the method of the invention It may be formed of other suitable semiconductor materials. In some embodiments, device layer 240 may include amorphous, microcrystalline, and / or polycrystalline silicon, germanium, or silicon germanium. If device layer 240 includes silicon germanium, the ratio of silicon to germanium may be from about 10,000: 1 to about 1: 1 (or other value range within the above range). The device layer 240 may further include a dopant such as B, P, As, or Sb. In one embodiment, the device layer 240 comprises polysilicon doped with boron or phosphorous. In another embodiment, device layer 240 includes a first polysilicon island region 240a doped with phosphorus and a second polysilicon island region 240b doped with boron.

  In certain embodiments, device layer 240 may be formed by printing (as described herein). Undoped and / or doped semiconductor precursors comprising, for example, undoped and / or doped polysilanes, heterocyclosilanes, and / or undoped and / or doped semiconductor nanoparticles Ink may be deposited or printed on the insulating layer 230 in a desired pattern using a suitable printing method (eg, inkjet printing, offset lithography, screen printing, etc.), after which the device layer 240 is formed. It may be cured and / or annealed as desired. For semiconductor precursor inks containing polysilanes, US Pat. Nos. 7,422,708, 7553545, 7498015, and 7485691, US Patent Application Publication No. 11 / 867,578 filed Oct. 4, 2007 (Attorney Docket No. IDR0884). And the relevant description part of each specification is hereby incorporated by reference. Regarding the semiconductor precursor ink containing heterocyclosilane, US Pat. No. 7,314,513, US Patent Application Publication No. 10/950373 filed Sep. 24, 2004 (Attorney Docket No. IDR0301) and 2004/10 No. 10/957144 (Attorney Docket No. IDR0303) filed on Jan. 1, the relevant description of each specification is incorporated herein by reference. Semiconductor precursor inks containing doped polysilanes are described in US patent application Ser. No. 11 / 867,487 filed on Oct. 4, 2007 (Attorney Docket No. IDR0884). The described portions are incorporated herein by reference. Semiconductor precursor inks containing undoped and / or doped semiconductor nanoparticles are described in U.S. Pat. Nos. 7,422,708 and 7553545, the relevant description of each specification is hereby incorporated by reference. Incorporated herein. Alternatively, the device layer 240 can be formed by one or more conventional thin film processes or techniques.

  FIG. 2E shows a thin film transistor (TFT) 245a-b, which is an example of a semiconductor device formed according to the method of the present invention. Each TFT 245a-b typically includes a semiconductor layer (eg, including a transistor channel 242a-b, a first source / drain terminal 244a-b, and a second source / drain terminal 246a-b), at least a portion of the semiconductor layer. Gate insulating layer 250a-b provided on top, gate metal layer 260a-b provided on gate insulating layer 250a-b, one or more dielectric layers provided on semiconductor layer and gate metal layer 260a-b, and gate A plurality of metal conductors (not shown) electrically connected to the metal layers 260a-b and the source / drain terminals 244a-b, 246a-b are included. Examples of suitable semiconductor, dielectric and metal layers for TFTs, and materials and methods for forming TFTs are described in US Pat. No. 7,619,248, filed August 11, 2005 and October 3, 2005, respectively. June 12, 2006, August 3, 2007, August 3, 2007, June 12, 2007, August 21, 2007, July 17, 2008, May 2, 2008 May 30, 2008, Oct. 1, 2008, U.S. Patent Application Publication Nos. 11/203563, 11/43460, 11/452108, 11/888949, 11/888942, 11/818078, 11/842848, 12/175450, 12/114741, 12/131002 and 12/243880 (Attorney Docket Number IDR0213, IDR 272, IDR0502, IDR0742, IDR0743, IDR0813, IDR0982, IDR1052, IDR1102, IDR1263, IDR1574) are described in, related description parts of the specification, they are incorporated herein by reference.

  In the TFTs 245a-b, gate dielectrics 250a-b are formed in the semiconductor island regions 240a-b. In some embodiments, the gate dielectric 250a-b prints a printing process (eg, a silicon dioxide precursor, such as hydrosiloxane or hydrosilicic acid, eg, US Pat. No. 7,709,307, November 2009. US Patent Application Publication No. 12/625492, filed 24 days, as described in Attorney Docket No. IDR0872, the relevant description part of each specification being incorporated herein by reference. The gate dielectrics 250a-b may be suitable dielectric precursors such as precursors of molecules, organometallics, polymers and / or nanoparticles in a mixed solution of solvent or solvent in which the dielectric precursor is soluble. Alternatively, the gate dielectric 250 may be formed by printing a housing, and the gate dielectric 250 is deposited over the entire semiconductor layer 240 (eg, , By CVD or PVD) and / or by thermally oxidizing the semiconductor layer 240. For example, the gate dielectrics 250a-b may be formed by conventional methods (eg, silicon oxide). An oxide film is formed by chemical vapor deposition or oxidation of the surface of the semiconductor island regions 240a-b to form an oxide film.The semiconductor layer 240 has a first dopant having a first conductivity type (for example, , Phosphorous) doped first polysilicon island region 240a and a second polysilicon island region 240b doped with a second dopant having a second conductivity type (eg, boron). The gate dielectric layer 250a has a slightly different thickness than the gate dielectric layer 250b due to the different oxidation rates of the semiconductor island regions that are formed. It may be.

  A gate electrode 260a-b may then be formed on the gate dielectric 250a-b. The gate electrodes 260a-b are formed by applying a Group 4, 5, 6, 7, 8, 9, 10, 11 or 12 metal or semiconductor material (eg, silicon, germanium, etc.) to a conventional deposition method (eg, chemical Vapor Deposition, Physical Vapor Deposition, Sputtering, Atomic Layer Growth, etc.) may be formed by depositing on the gate dielectric layer 250a-b, followed by photolithography. In some embodiments, forming the gate electrode 260 includes printing or coating an ink component that includes a metal precursor, the metal precursor being a solvent or solvent suitable for coating or printing the metal precursor. It includes one or more Group 4, 5, 6, 7, 8, 9, 10, 11 or 12 metal salts, metal complexes, metal clusters, and / or nanoparticles in the mixture. In certain embodiments, the metal precursor comprises a metal salt, compound and / or complex, which is gaseous or volatile upon reduction of the metal salt, compound and / or complex to an elemental metal and / or alloy. It has one or more ligand bonds that produce by-products. The metal precursor further includes one or more additives (eg, one or more additives) that can produce gaseous or volatile byproducts upon reduction of metal salts, compounds and / or complexes to elemental metals and / or alloys. A reducing agent). With such a metal formulation, pure metal can be printed using a metal precursor and a reducing agent, which usually has impurities and / or residues that can affect the film. Never leave. Further details can be found in U.S. Patent Application Publication No. 12 / 131,002 (Attorney Docket No. IDR 1263) filed May 30, 2008, the relevant description of which is incorporated herein by reference. Incorporated in the description. Following coating or printing of the ink composition, the metal precursor may be further patterned by photolithography.

  Subsequently, source and drain regions 244a-b and 246a-b may be formed in the semiconductor layer 240 by any of a number of methods. (For example, after ion implantation, ion shower, gas immersion laser deposition (GILD), printing or depositing a heavily doped semiconductor layer on the semiconductor layer 240 and the gate 260, performing a curing and / or activation process, or 1 The above dopant layers (eg, two different layers, 270a and 270b, each containing complementary dopants) are printed or deposited on semiconductor layer 240 and gate 260, followed by a drive-in process. Are described in U.S. Pat. Nos. 7,619,248 and 7,701,011, and U.S. Patent Application Publication No. 11/888942 filed on August 3, 2007 (Attorney Docket No. IDR0742). The relevant description portion of is incorporated herein by reference.) Source regions 244a-b and After forming the drain region 246a-b, the channel region 242a-b remains below the gate electrode 260a-b.

  Before or after forming the source and drain regions 244a-b and 246a-b, the gate dielectric layer 250a-b in the region exposed from the gate 260a-b (ie, not covered by the gate) is selectively It may be removed by wet etching or dry etching. If source and drain regions 244a-b and 246a-b are formed by printing or depositing a dopant layer over semiconductor layer 240 and gate 260, followed by a drive-in and / or activation process, further Prior to performing the process (if necessary, before removing the exposed gate dielectric layer), the dopant layer is typically removed.

  One or more dielectric layers 270 (eg, first and second interlayer dielectrics 270a and 270b) are then often deposited over the gates 260a-b and source and drain regions 244a-b and 246a-b, often over the entire surface. Or deposited by printing (as described herein). In some embodiments, the dielectric layer is formed by printing an ink that includes one or more dielectric precursors and one or more solvents. Typically, the dielectric precursor includes silicon dioxide, silicon nitride, silicon oxynitride, aluminate, titanate, titanium silicate, zirconia (zirconium oxide), hafnia (hafnium oxide), or ceria (cerium oxide). . In another embodiment, the dielectric precursor is an organic polymer or an organic polymer precursor (eg, acrylic acid, methacrylic acid, and / or an ester of acrylic acid, and / or a polymer or copolymer of methacrylic acid). ). After printing, the dielectric ink is dried and cured. Drying the printed ink is heated under vacuum or in an inert or oxidizing atmosphere at a temperature of 50 ° C. to 150 ° C. for a time sufficient to remove substantially all of the solvent from the printed ink. You may include that. Curing of the dried dielectric precursor can be accomplished by applying the precursor to the desired dielectric under an inert or oxidizing atmosphere, for example, at a temperature of 200 ° C. to 500 ° C. (or any value within this range). Heating may be included for a time sufficient to convert to a material.

  In addition, contact holes (not shown) may be provided in the dielectrics 270a-b and may be provided in one or more additional devices (eg, TFT 245) gate 260a / b, source / drain terminals 244a / b and 246a / b. Metal wires and / or wirings (not shown) for connection may be formed. Alternatively, when the dielectric layer 270a-b is formed by printing, the printed pattern has a plurality of surfaces exposing the surfaces of the gates 260a-b and the source / drain terminals 244a-b and 246a-b, respectively. A contact hole may be included. In one embodiment, the metal line / wiring is formed by printing. (U.S. Patent Application Publication No. 12/175450 filed on July 17, 2008 (Attorney Docket Number IDR1052), U.S. Patent Application Publication No. 12/131002 filed on May 30, 2008 (See Attorney Docket IDR 1263), the relevant description part of the specification is incorporated herein by reference.) In one example, a conductive material seed layer is printed on the pattern of metal lines and / or wiring, Bulk metal or metal alloy is plated on the pattern (eg, by electroplating or electroless plating). Alternatively, metal lines and / or wires may be formed by conventional thin film and / or deposition and photolithography processes.

  The TFT 245 is an NMOS transistor or a PMOS transistor, and may be configured and / or electrically connected to function as a transistor, a diode, a resistor, a capacitor, or a TFT connected in an off state. FIG. 2E illustrates a TFT 245 having a dome shape. (See, eg, US Patent Application Publication No. 12/243880 (Attorney Docket No. IDR1574) filed on Oct. 1, 2008, the relevant description of which is incorporated herein by reference. .) Typically, semiconductor island regions (eg, 240a and / or 240b in FIG. 2D) and gates (eg, 260a and / or 260b in FIG. 2E) have a dome shape when formed by printing. It may be. Each manufacturing process in the “full printing” method for forming a TFT such as the TFT 245 can be variously changed, and the dimensions, boundaries, and surface of the TFT 245 may be changed accordingly. Accordingly, the cross-section and / or layout shape and / or outline (viewed from above) of the printed structure may vary from structure to structure.

  Thus, in one embodiment, TFT 245 may be formed by a “full print” process. In embodiments where one or more layers of TFT 245 are formed by printing, the printed precursor ink is typically dried and cured. The length of time and temperature at which the ink is dried and the dried precursor is cured will vary depending on the ink formulation and the precursor contained, but in many cases, the ink will have a solvent from the printed ink. For a precursor that has been dried for a length of time and at a temperature sufficient to remove substantially all of the precursor, convert the precursor to the final film material (eg, semiconductor, dielectric or metal). Curing is carried out for a sufficient length of time and temperature to do. For further description of printed TFT examples and methods of forming such printed TFTs, see US Patent Application Publication No. 11/805620, filed May 23, 2007 (Attorney). No. IDR0712) and US Patent Application Publication No. 12/243880 (Attorney Docket No. IDR1574) filed on Oct. 1, 2008, the relevant description part of which is incorporated by reference Incorporated herein. Alternatively, the TFT 245 may be formed using printing and mixing with conventional manufacturing processes, or using only conventional manufacturing techniques (eg, thin film technology).

  As described above, “bottom gate” type devices can be formed on a coated substrate. After forming the gate electrodes 240a-b (FIG. 2D), a gate dielectric layer can be formed over the gate electrodes by one or more methods described with reference to the layers 250a-b of FIG. 2E. A transistor body (similar to layers 260a-b in FIG. 2E) can be formed over the gate dielectric layer and can be doped by well known processes. (Application date 11/243460 filed on Oct. 3, 2005 (Attorney Docket No. IDR0272) and US Patent Application Publication No. 12/109338 filed April 24, 2008). (See Attorney Docket IDR1322), the relevant description portion of the specification is hereby incorporated by reference.) Disclosed herein is a bulk dielectric layer similar to layers 270a-b in FIG. 2E. The device layer (eg, the gate electrode and the source / drain terminal of the transistor body) that forms the contact hole and is disposed below as described above. The wiring can be formed in contact with the.

  In yet another embodiment, a device on a metal substrate coated with a diffusion barrier layer can include one or more capacitors, diodes, resistors, and wiring. The capacitor typically includes a dielectric material between the first and second capacitor plates and the first and second capacitor plates. The diode typically includes multiple (eg, 2 to 5) diode layers of conductor or semiconductor material having different doping types and amounts. For example, in a two-layer diode, the first layer includes a P-type semiconductor or is mainly composed of a P-type semiconductor, and the second layer includes an N-type semiconductor or is mainly composed of an N-type semiconductor. Also good. In the three-layer diode, the first layer includes a heavily doped P-type semiconductor or is mainly composed of a heavily doped P-type semiconductor, and the second layer is an intrinsic semiconductor or a lightly doped semiconductor. A third layer comprising or mainly heavily doped N-type semiconductor comprising or mainly composed of P-type or N-type semiconductor doped with It may be constituted by. In the illustrated diode, the P-type or N-type semiconductor layer may include a plurality of sublayers having different doping concentrations or may be mainly constituted by a plurality of sublayers (for example, one or more high concentrations). Doped layers or very heavily doped layers and one or more lightly doped layers or very lightly doped layers). Resistors and / or wires are typically formed on a coated substrate and / or device layer in a pattern. Capacitor plates, resistors and / or wires may include semiconductor and / or conductor materials as disclosed herein, and diode layers typically include semiconductor materials as disclosed herein. The capacitor plate, diode layer, resistor, and / or wiring may be formed by any process disclosed herein.

  In another embodiment, as shown in FIGS. 3A-3C, the metal substrate 310 is a diffusion barrier layer 320 deposited on one major surface of the metal substrate 310 (see FIG. 3B) by one or more processes as described above. You may have. In further embodiments (not shown), at least one (but not all) surface of the metal substrate 310 may be covered by a diffusion barrier layer 320. For example, when processing a roll or sheet before the metal substrate 310 is formed, the opposite surface of the metal substrate 310 is covered with a diffusion barrier layer 320 (for example, a semiconductor structure or device is formed later). The main surface of the metal substrate 310 to be formed) and one or more side edges of the metal substrate 310 may not be covered. Alternatively, before or after the cleaning step, the metal substrate 310 may be formed or cut out, and the diffusion barrier layer 320 may be formed so as to cover one main surface and the edge of the metal substrate 310.

  As shown in FIG. 3C, in an embodiment in which the diffusion barrier layer 320 is deposited on one major surface of the metal substrate 310, the present specification covers the portion of the metal substrate 310 that is covered with the diffusion barrier layer 320. The insulating layer 330 may be deposited by one or more steps as described in the document. In a further embodiment (not shown) where at least one but not all surfaces of the metal substrate 310 are coated with the diffusion barrier layer 320, the region covered with the diffusion barrier layer 320 is Subsequently, the insulating layer 330 may be covered (for example, the upper surface and the side surface of the metal substrate 310 may be covered with the diffusion barrier layer 320 and the insulating layer 330).

[Example of metal substrate coated with a barrier layer having antireflection properties]
A problem in using a metal foil substrate is the relatively high reflectance of the metal substrate and / or the barrier layer (see FIGS. 4A-4B). Optical constants and thicknesses of a laminate of composition films (eg, a metal-barrier-insulator laminate typically comprising a metal foil 410, one or more diffusion barrier materials 420/425 and one or more insulating layers 430). Is related to absorbing and reflecting light to varying degrees, and at least to the angle of incident light, depending on the wavelength of light used in manufacturing the device.

  Specifically, the wavelength range of visible light (such as lasers and / or other flash bulbs, etc.) is used to crystallize silicon or other electrical device layer 440 deposited on a metal-barrier-insulator stack. Most of the light can be transmitted through the silicon film 440. Light that passes through the silicon film 440 is at least partially reflected by the metal foil 410 and / or the barrier layer (eg, 420 in FIG. 4A). The film thickness of the silicon film 440 and the film thickness of the layers constituting the metal-barrier-insulator stack are not optimized and / or non-uniform and relative to the interaction with light In particular, the light absorption of the silicon film 440 may change due to high sensitivity (for example, direct absorption of light and / or absorption of light reflected by an underlying layer). Such sensitivity of the silicon film 440 to light interaction may greatly change the crystallinity uniformity and grain structure (eg, within the same processing lot) between a different substrate and a given substrate. Lead to undesirable device variations. In particular, when aluminum nitride (which is a high-quality diffusion barrier) and a laser emitting light in the visible light wavelength range (for example, the green wavelength range) are used in combination, the silicon crystallization is greatly affected.

  One or more anti-reflective layers (eg, the layer of FIG. 4B) to reduce, minimize or eliminate the effects of light absorption variations caused by the relatively high sensitivity to interaction with light in the silicon film. 425) may be formed on the first barrier layer 420 as part of the metal-barrier-insulator stack. Alternatively, the antireflection layer 425 may be formed on the metal substrate 410 or the insulating layer 430. The material of the antireflection layer 425 may be selected so that the reflectance is low at the wavelength of light used for silicon crystallization. Alternatively, the material of the antireflection layer 425 may be selected such that the reflectance is low at wavelengths useful for solar cells (PV cells). The anti-reflective layer 425 may be deposited as part of the diffusion barrier 420 (eg, a barrier layer / anti-reflective layer 420/425), which can enhance the use of the anti-reflective layer and allow crystallization processes. The window can be widened to improve device yield and / or performance. Ideally (although not necessarily), the antireflective layer 425 may be the same film growth apparatus (eg, atomic layer growth apparatus, integrated) that forms the barrier layer 420 and / or the insulating film 430. CVD sputter cluster equipment, spin-on-glass and curing equipment, etc.).

It would be beneficial if one layer had both an anti-reflective function and a diffusion barrier function (eg, functioning as a barrier to prevent outward diffusion of impurities from the underlying metal substrate 410) This configuration is not essential to the invention. That is, the barrier layer in the metal-barrier-insulator stack includes (i) one or more layers having only diffusion barrier properties and at least one layer having antireflection properties, and (ii) 1 having only antireflection properties. And at least one layer having only the above layers and diffusion barrier properties, (iii) one or more layers having both diffusion barrier properties and reflection properties, or (iv) a combination thereof. An anti-reflective coating (ARC) layer may be insulating at the same time, depending on the desired optical properties for the layer (eg, silicon oxynitride (where the Si: O: N ratio is selected) Possible), films with a high dielectric constant k, such as TiO ₂ , alumina, ZrO ₂ and / or other metal oxides).

  Specifically, titanium nitride (or silicon oxynitride, for example) alone can be used as the antireflection film 425, or an antireflection film can be combined with the aluminum nitride film 420. The film may be deposited as a double layer barrier stack (e.g., a stack composed of a metal substrate 410-AlN 420-TiN 425-insulating layer 430, or a metal substrate-TiN-AlN-insulating layer). Layered structure), or an aspect of alternately stacked nanolaminates (for example, a laminate composed of metal substrate-nanolaminate-insulating layer, where each layer of the nanolaminate is one or more A single layer of AlN and one or more single layers of TiN, and the number of layers of the nanolaminate may be anywhere from 1 to 10,000). The thickness that maximizes the efficiency of the nanolaminate used as a barrier and antireflective coating may be determined empirically. The typical thickness of the nanolaminate is 1-100 nm (or any range of values within the above range). As shown in FIG. 5, by using a TiN-AlN nanolaminate, the reflectivity can be reduced by 75%, laser crystallization compared to pure AlN alone (or similar material). The optical coupling between and the sensitivity of the laminate can be reduced. Further, since the optical coupling and the sensitivity of the laminated body are reduced, the silicon film can be crystallized more uniformly and / or the quality of the silicon film can be further improved.

  The use of an antireflective material (such as titanium nitride) used at the visible light wavelength (eg, green) of the light source for crystallization of silicon or other device layers will allow any wavelength of light (or light source). The wavelength may be specially adjusted with respect to the area. Wavelength tuning also includes the use of suitable materials having the desired anti-reflective properties that fit within the overall integrated structure of the device.

[Example of metal substrate coated with a barrier having stress relaxation properties]
Another problem that can arise when using a metal foil substrate is often the granular high-brightness region of the metal substrate that is generated by stress. The granular high-intensity region may affect the next processing step. Some barrier materials have high intrinsic stress, and the laminate and / or composition of the barrier layer may be optimized taking this intrinsic stress into account.

  Efficiently passivate a substrate containing a metal foil (eg, substrate 210 in FIG. 2A) and directly contaminate (via external diffusion) or unencapsulated metal (eg, with processing equipment, solution layers, etc.) To prevent indirect contamination (due to contact with the foil substrate 210), the diffusion barrier (eg, layer 220 in FIG. 2A) needs to seal all exposed surfaces of the substrate 210 including the side edges of the substrate. . The size, composition, and / or physical, chemical and / or mechanical properties of the diffusion barrier 220 may be optimized to enable the metal substrate 210 and / or one or more barrier layers (eg, 420 and / or in FIGS. 4A-4B). 425), the degree of problems that occur in the manufacturing process due to the optical reflectivity can be reduced.

A titanium nitride film as a metal diffusion barrier (eg, layer 220 in FIG. 2A) may be deposited directly on stainless steel 210 to completely seal all surfaces and side edges of substrate 210. In some embodiments (eg, when the barrier film is deposited by ALD), an adhesive layer may be formed on the substrate 210 before depositing the barrier layer 220, depending on process conditions. Thereafter, sealing with an insulating layer 230 (eg, a silicon dioxide layer having a nominal thickness of 1 micron) may be performed in a similar manner. It is desirable to perform cleaning of the substrate 210 (for example, removal of residues, organic substances, particles, and the like) before deposition of the barrier layer 220. By performing cleaning, the adhesion of the barrier layer 220 at high temperature is improved. be able to. At high temperatures (eg, several hours of time, tested at 850 ° C. with multiple thermal cycles), the TiN barrier 220 is effectively made of iron and chromium (the main and fastest diffusing component of the steel substrate 210). Diffusion to the active silicon TFT device formed on the surface of the SiO ₂ insulating layer 230 is prevented (see, for example, FIG. 5). It also prevents nickel and other alloy components in stainless steel such as Co, Mo, Ti, Nb from diffusing into the surface of the insulating layer 230 (and the device layer formed thereon). Is done.

In one embodiment, the barrier layer includes a first layer of AlN that functions as an adhesion layer, a layer of SiO ₂ : Al that functions as a stress relaxation layer, and a layer of AlN that functions as a diffusion barrier. A typical AlN first layer has a thickness of 10-100 mm, but can be any thickness in the range of 10-5000 mm. Stress relaxation layer (e.g., _SiO 2: Al) may have a thickness of 10-500A, be in the range of 10-5000A, may be of any thickness. Preferably, the stress relaxation layer is deposited by ALD. A typical AlN second layer has a thickness of 200-2000 mm, but can be any thickness in the range of 50-10,000 mm. Alternative configurations for the adhesion and stress relaxation layers cited in this paragraph include Al ₂ O ₃ , silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and oxides of zirconium, hafnium or rare earth metals, or These combinations, or alloys thereof, including those formed in the same thickness range as described above. The choice of materials and dimensions may be made depending on the desired material properties and suitability for the overall manufacturing process integration scheme.

As described above, other materials that function as diffusion barriers include TiN and TiAlN (where the ratio of Ti to Al depends on the application, for example, stress and reflectivity of the stack of diffusion barrier films). Can be adjusted by changing the ratio of Ti to Al). TiN and / or TiAlN films can be sputtered (sputter etch of the steel surface may or may not be performed as needed prior to deposition), or chemical vapor deposition (CVD). It may be deposited by various methods, with atomic layer deposition (ALD) deposition being particularly preferred. The stress relaxation layer and / or additional diffusion barrier layer can provide suitable protection for the device (eg, TFT 245 of FIG. 2E) during multiple thermal cycles where the temperature is up to 850 ° C. This method combines an insulating film (eg, SiO ₂ and / or Al ₂ O ₃ ) to electrically isolate the substrate 210 and barrier layer 220 from the device layer (eg, 240 in FIGS. 2D-2E). Preferably, it is coated with an insulating film in the same deposition apparatus (or in another deposition process).

  The diffusion barrier layer may solve one or more processing problems. For example, a metal nitride film (or alternatively, a metal carbide, silicon nitride, or silicon carbide film) may have a high stress or may apply a high stress to other layers in the device. This stress can lead to delamination of the film or deformation of the underlying steel substrate. By including one or more additional materials in the film stack, this stress can be significantly reduced. For example, by adding an oxide layer under the metal nitride or forming a laminate such as TiN: AlN (TiN: AlN represents the ratio of TiN layer to AlN layer in the nanolaminate). Can be relaxed. In one example, eight monolayers of TiN are formed, followed by a block of three monolayers of AlN (and the process is repeated until a predetermined total film thickness is achieved), to relieve stress and diffuse. Any number of configurations in which TiN and AlN monolayers are alternately arranged may be provided (for example, 5-100 monolayers of TiN and 1-monolayers of AlN may be provided). 50 layers). If such a stress relaxation oxide layer is not formed underneath, the AlN film (eg, 420 in FIG. 4A) may peel off from the substrate 410 at a high temperature. Accordingly, in one embodiment, a TFT device on a stainless steel substrate (eg, 245 in FIG. 2E) is formed of sputtered TiN having a thickness of about 1 nm to about 1000 nm (eg, in one embodiment, about 100 mm). And a layer of TiAlN formed by ALD (described above) having a thickness of about 10 nm to about 1500 nm (eg, in one embodiment about 300 nm).

  The steel substrate particles and the high reflectivity of the steel substrate make it difficult to inspect with light or align the steel foil substrate in the next step. The high reflectivity of the substrate has also caused problems in the laser process in the crystallization process. Also, the high reflectivity of the substrate causes the reflected laser energy to interfere with the incident laser energy and cause standing waves at high / low energy nodes, resulting in Variations in radiation dose may occur. In order to suppress the influence of such effects, the thickness and composition of the diffusion barrier layer are optimized to be optically opaque, and the reflection from the surface of one or more underlying layers and / or the surface of the metal substrate Can be minimized.

  TiN and its alloys are relatively inexpensive, often formed as a single layer film, and are suitable for various deposition methods (eg, double-sided deposition in many embodiments). Other than TiN, the metal film used for the diffusion barrier coated substrate according to the present invention is described in Afentakis et al., IEEE Transactions on Electron Devices, vol. 53, no. 4 (April 2006), p. 815, the relevant description is hereby incorporated by reference.

[Conclusion / Summary]
Accordingly, the present invention provides a semiconductor device formed on a substrate coated with a diffusion barrier layer. The present invention prevents metal atoms from diffusing from a metal substrate on which a diffusion barrier layer is formed into a semiconductor device formed on the metal substrate.

The particular embodiments of the invention described above have been presented for purposes of illustration and description. The above description is not intended to be exhaustive or to limit the invention to the precise form disclosed, and many variations and modifications are possible in light of the above teaching. it is obvious. The embodiments described above are described in order to best explain the principle and practical application of the present invention, and those skilled in the art can make good use of the present invention, and various modifications can be made. The various embodiments involved can be considered to suit a particular implementation. The scope of the present invention is defined by the appended claims and their equivalents.
[Item 1]
a) a metal substrate;
b) one or more diffusion barrier layers on the metal substrate;
c) one or more insulating layers on the diffusion barrier layer;
d) A device comprising a device layer on the one or more insulating layers.
[Item 2]
Item 2. The device of item 1, wherein the metal substrate is sealed by at least one of the diffusion barrier layers and at least one of the insulating layers.
[Item 3]
The device of claim 1, wherein at least one surface of the metal substrate is covered by at least one of the diffusion barrier layers and at least one of the insulating layers.
[Item 4]
Item 2. The device according to Item 1, wherein the metal substrate includes aluminum, copper, titanium, stainless steel, or molybdenum.
[Item 5]
Item 2. The device according to Item 1, wherein the metal substrate has a thickness of about 10 µm to about 1000 µm.
[Item 6]
The device of item 1, wherein at least one of the diffusion barrier layers comprises a titanium compound.
[Item 7]
Said titanium compound comprises _Ti x _{N y,} or _Ti a _Al b _{N c,} wherein, according to claim 6 and x + y = 1 or a + b + c = 1 device.
[Item 8]
The device of item 1, wherein the one or more diffusion barrier layers have a thickness of about 10 nm to about 1 μm.
[Item 9]
The device of item 1, wherein the one or more insulating layers comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof.
[Item 10]
10. The device of item 9, wherein the one or more insulating layers have a thickness of about 100 nm to about 10 μm.
[Item 11]
The device according to Item 1, wherein the device layer includes a semiconductor layer.
[Item 12]
Item 12. The device according to Item 11, wherein the semiconductor layer includes at least one of silicon and germanium.
[Item 13]
Item 13. The device according to Item 12, wherein the semiconductor layer includes at least one of polycrystalline silicon and polycrystalline germanium.
[Item 14]
14. The device according to item 13, wherein the semiconductor layer further includes a dopant selected from the group consisting of B, P, As, and Sb.
[Item 15]
A gate electrode is further provided on or below the semiconductor layer,
Item 12. The device of item 11, wherein the gate electrode comprises a gate and a gate dielectric layer.
[Item 16]
The semiconductor layer has a first dopant of a first conductivity type,
The device further comprises a second semiconductor layer above or above the semiconductor layer,
Item 12. The device according to Item 11, wherein the second semiconductor layer has a second dopant of a second conductivity type.
[Item 17]
The device layer has a first conductive layer,
The device according to item 1, wherein the first conductive layer is selected from the group consisting of a first metal layer and a first highly doped semiconductor layer.
[Item 18]
A dielectric layer on the first conductive layer;
A second conductive layer on the first conductive layer,
18. The device according to item 17, wherein the second conductive layer is selected from the group consisting of a second metal layer and a second highly doped semiconductor layer.
[Item 19]
Item 2. The device according to Item 1, further comprising an antireflection layer on or above the metal substrate.
[Item 20]
Item 20. The device according to Item 19, wherein the device layer is located above the antireflection layer.
[Item 21]
Item 2. The device according to Item 1, further comprising a stress relaxation layer on or above the metal substrate.
[Item 22]
A method of forming a device on a metal substrate, comprising:
a) forming one or more diffusion barrier layers on the metal substrate;
b) forming one or more insulating layers on the diffusion barrier layer;
c) forming a device layer on the one or more insulating layers.
[Item 23]
24. The method of item 22, wherein the metal substrate is sealed by at least one of the diffusion barrier layers and at least one of the insulating layers.
[Item 24]
24. The method of item 22, wherein at least one surface of the metal substrate is covered by at least one of the diffusion barrier layers and at least one of the insulating layers.
[Item 25]
23. The method of item 22, further comprising the step of cleaning the metal substrate before forming the one or more diffusion barrier layers.
[Item 26]
26. The method according to item 25, wherein the step of cleaning the metal substrate includes a step of sputter etching the metal substrate.
[Item 27]
Item 23. The method according to Item 22, wherein the metal substrate includes aluminum, copper, titanium, or stainless steel.
[Item 28]
24. The method of item 22, wherein the metal substrate has a thickness of about 10 μm to about 1000 μm.
[Item 29]
23. The method according to item 22, wherein the step of forming the one or more diffusion barrier layers includes physical vapor deposition, atomic layer growth, or chemical vapor deposition of a titanium compound.
[Item 30]
30. The method of item 29, wherein the step of forming the one or more diffusion barrier layers includes atomic layer growth.
[Item 31]
30. The method according to item 29, wherein the titanium compound includes Ti _x N _y or Ti _a Al _b N _c , where x + y = 1 or a + b + c = 1.
[Item 32]
32. The method of item 31, wherein x is about 0.5 and y is about 0.5.
[Item 33]
24. The method of item 22, wherein the one or more diffusion barrier layers have a thickness of about 10 nm to about 1 μm.
[Item 34]
23. The method of item 22, wherein the one or more insulating layers include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof.
[Item 35]
35. The item 34, wherein forming the one or more insulating layers includes depositing at least one of the insulating layers by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Method.
[Item 36]
35. A method according to item 34, wherein the step of forming the one or more insulating layers includes printing at least one of an insulator ink and an insulator precursor.
[Item 37]
35. The method of item 34, wherein the one or more insulating layers have a thickness of about 100 nm to about 10 μm.
[Item 38]
Item 23. The method according to Item 22, wherein the device layer includes a semiconductor layer.
[Item 39]
39. The method according to Item 38, wherein the semiconductor layer includes at least one of silicon and germanium.
[Item 40]
40. The method of item 39, wherein the semiconductor layer further comprises a dopant selected from the group consisting of B, P, As, and Sb.
[Item 41]
A step of forming a gate electrode on or under the semiconductor layer;
40. The method of item 39, wherein the gate electrode comprises a gate and a gate dielectric layer.
[Item 42]
The semiconductor layer has a first dopant of a first conductivity type,
The device further comprises a second semiconductor layer on or above the semiconductor layer,
40. The method of item 39, wherein the second semiconductor layer has a second dopant of a second conductivity type.
[Item 43]
The device layer has a first conductive layer,
23. A method according to item 22, wherein the first conductive layer is selected from the group consisting of a first metal layer and a first highly doped semiconductor layer.
[Item 44]
A dielectric layer on the first conductive layer;
A second conductive layer on the first conductive layer,
44. A method according to item 43, wherein the second conductive layer is selected from the group consisting of a second metal layer and a second highly doped semiconductor layer.
[Item 45]
40. The method according to item 39, further comprising irradiating the semiconductor to crystallize at least part of the semiconductor layer.
[Item 46]
Item 23. The method according to Item 22, further comprising the step of forming an antireflection layer on or above the metal substrate.
[Item 47]
47. A method according to item 46, wherein the device layer is located above the antireflection layer.
[Item 48]
Item 23. The device according to Item 22, further comprising a step of forming a stress relaxation layer on or above the metal substrate.
[Item 49]
The stress relaxation layer is formed on the metal substrate,
The method further includes forming an antireflection layer on the stress relaxation layer,
49. A device according to item 48, wherein the one or more diffusion barrier layers are formed on or above the antireflection layer.

Claims (18)

a) a metal substrate comprising at least one of iron, chromium, nickel, molybdenum, niobium, cobalt and titanium;
b) one or more diffusion barrier layers on the metal substrate;
c) one or more insulating layers on the diffusion barrier layer;
d) a semiconductor layer on the one or more insulating layers,
At least one of the diffusion barrier layers has a Ti _x N _y ratio of about 3: 4 to about 3: 2 or a ratio of (a + b) to c of about 3: 4 to about 3: 2 including a titanium compound represented by Ti _a Al _b N _c ,
The insulating layer electrically isolates the diffusion barrier layer from an electrical device, and an electrical device structure is subsequently formed on the insulating layer;
The device, wherein the semiconductor layer comprises silicon.   The device of claim 1, wherein the metal substrate is sealed by at least one of the diffusion barrier layers and at least one of the insulating layers.   The device according to claim 1 or 2, wherein at least one surface of the metal substrate is covered by at least one of the diffusion barrier layers and at least one of the insulating layers.   The device according to any one of claims 1 to 3, wherein the metal substrate comprises a foil or sheet of titanium, molybdenum or stainless steel and has a thickness of about 10 µm to about 1000 µm.   5. The device of any one of claims 1 to 4, wherein the one or more diffusion barrier layers have a thickness of about 10 nm to about 1 [mu] m. The one or more insulating layers include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof;
6. The device of any one of claims 1 to 5, wherein the one or more insulating layers have a thickness of about 100 nm to about 10 [mu] m. A gate electrode is further provided on or below the semiconductor layer,
The device of any one of claims 1 to 6, wherein the gate electrode comprises a gate and a gate dielectric layer. A method of forming a device on a metal substrate, comprising:
a) forming one or more diffusion barrier layers on the metal substrate;
b) forming one or more insulating layers on the diffusion barrier layer;
c) forming a semiconductor layer on the one or more insulating layers,
The metal substrate includes at least one of iron, chromium, nickel, molybdenum, niobium, cobalt and titanium,
At least one of the diffusion barrier layers has a Ti _x N _y ratio of about 3: 4 to about 3: 2 or a ratio of (a + b) to c of about 3: 4 to about 3: 2 including a titanium compound represented by Ti _a Al _b N _c ,
The insulating layer electrically isolates the diffusion barrier layer from an electrical device, and an electrical device structure is subsequently formed on the insulating layer;
The method, wherein the semiconductor layer comprises silicon.   The method of claim 8, wherein the metal substrate is encapsulated by at least one of the diffusion barrier layers and at least one of the insulating layers.   10. A method according to claim 8 or 9, wherein at least one face of the metal substrate is covered by at least one of the diffusion barrier layers and at least one of the insulating layers. The metal substrate includes a foil or sheet of titanium, molybdenum or stainless steel,
11. The method according to any one of claims 8 to 10, wherein the metal substrate has a thickness of about 10 [mu] m to about 1000 [mu] m.   12. The method according to any one of claims 8 to 11, wherein the step of forming the one or more diffusion barrier layers comprises physical vapor deposition, atomic layer growth or chemical vapor deposition of a titanium compound. 9. The method of claim 8, wherein the Ti _x N _y or the Ti _a Al _b N _c has a thickness of about 10 nm to about 1 μm. The one or more insulating layers include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof;
The one or more insulating layers have a thickness of about 100 nm to about 10 μm;
The step of forming the one or more insulating layers includes depositing at least one of the insulating layers by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. 2. The method according to item 1. The method according to claim 8, further comprising irradiating the semiconductor layer with light in a visible wavelength range so as to at least partially crystallize the semiconductor layer .   The device according to claim 1, wherein the diffusion barrier layer seals a plurality of main surfaces and a plurality of ends of the metal substrate. 17. The device according to claim 1, wherein the titanium compound represented by Ti _a Al _b N _c has a nanolaminate insulator in which TiN and AlN are alternately deposited.   The method according to claim 8, wherein the diffusion barrier layer seals a plurality of main surfaces and a plurality of ends of the metal substrate.

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