JP5724981B2 - Memory access control device, memory access control system, and memory access control method - Google Patents

Description

  The present invention relates to a memory access control device, a memory access control system, and a memory access control method for avoiding performance degradation due to thrashing in a cache memory.

  One of the causes of the performance degradation of the computer system is the occurrence of thrashing in which the same entry in the cache memory in the processor is competing among a plurality of memory requests. If cache miss hits frequently occur due to thrashing, the access frequency to the lower level cache and the main storage device increases, and the latency of memory access increases, so the system performance is greatly reduced. Therefore, in order to improve the performance of the computer system, it is a problem to avoid the performance degradation of the cache memory due to thrashing.

  As a technique for dealing with the above-described problem, Patent Document 1 includes a table that holds a history of access addresses of memory requests, detects the occurrence of thrashing, and holds transfer data based on the memory request generated by thrashing. A memory system that reduces the access frequency to the main storage device by providing a buffer for this purpose is disclosed.

JP 2002-215457 A

  The memory system of Patent Document 1 is for avoiding performance degradation due to thrashing after the next time after detecting the occurrence of thrashing for a certain access address. Therefore, it does not have a function for avoiding the occurrence of the first thrashing for a certain access address. Therefore, the memory system of Patent Document 1 cannot be said to be sufficient for improving the performance of the computer system.

  An object of the present invention is to provide a memory access control device, a memory access control system, and a memory access control method that solve the above-described problems.

  A memory access control device according to an embodiment of the present invention stores a copy of data stored in a main memory in association with an address in the main memory, and stores the copy in association with the address that matches the input address. The first associative memory device and the second associative memory device that output data, and the address included in the data reference command from the command issuing unit of the central processing unit are input, and the first associative memory device and the first associative memory device Access control means for outputting in parallel to two associative memory devices, the number of entries storing one piece of the data is smaller in the first associative memory device than in the second associative memory device, In addition, the association degree, which is the number of entries that may store one piece of the data, is greater in the first associative storage device than in the second associative storage device.

  A memory access control method according to an embodiment of the present invention stores a copy of data stored in a main memory in association with an address in the main memory, and stores the copy in correspondence with the address that matches the input address. A first associative memory device and a second associative memory device that output data, wherein the first associative memory device has the second associative memory for the number of entries for storing the one data. Associativeness, which is smaller than the device and has the possibility of storing one piece of the data, is accessed by the memory of the first associative memory device larger than that of the second associative memory device. Provided in the control device, an address included in the data reference command is input from the command issuing unit of the central processing unit, and is output in parallel to the first associative memory device and the second associative memory device.

  The present invention makes it possible to improve the system performance by suppressing the occurrence of thrashing and improving the hit rate of the cache memory.

It is a block diagram which shows the structure of the memory access control system of 1st Embodiment of this invention. It is an example of a mapping of the address of the main memory data to the 1st associative memory device in the 1st Embodiment of this invention, and a 2nd associative memory device. It is a flowchart (the 1) which shows operation | movement of the 1st Embodiment of this invention. It is a flowchart (the 2) which shows operation | movement of 1st Embodiment of this invention. It is an example of a structure of the entry of the 1st content addressable memory | storage device in 1st Embodiment of this invention. It is an operation example of the access control unit in the first embodiment of the present invention. It is a block diagram which shows the structure of the memory access control apparatus of 2nd Embodiment of this invention.

  A first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the memory access control system of this embodiment.

  The memory access control system 1 according to the present embodiment includes a memory access control device 10, an instruction issuing unit 20, and a main storage device 30.

  The memory access control device 10 and the instruction issuing unit 20 are mounted on a processor (not shown) of the central processing unit. When the instruction issuing unit 20 issues a data reference instruction, the memory access control device 10 accesses the main storage device 30 if necessary based on the address specified by the data reference instruction. In some systems, a lower level cache memory is provided in front of the main storage device 30.

  The memory access control device 10 includes an access control unit 100, a first associative storage device 110, a second associative storage device 120, and an instruction storage unit 130.

  The first associative memory device 110 and the second associative memory device 120 are cache memories arranged in parallel in the processor of the central processing unit. Note that some systems include a higher-level cache memory between the instruction issuing unit 20 and the system. The first associative storage device 110 includes an address storage unit 111 and a data storage unit 112, and the second associative storage device 120 includes an address storage unit 121 and a data storage unit 122.

  An example of the mapping of the address space of the main storage device 30 to the first associative storage device 110 and the second associative storage device 120 is shown in FIG.

  The main memory address space 200 is divided into n areas according to the address value, and the copy of the main memory data included in each area is an entry determined for each area in the second associative memory device 120. Stored in an entry in the group. n is generally an integer of 8 or more. As indicated by the mapping 201 of addresses to the second associative memory device 120, a copy of the main memory data such as address 1, address n + 1, address 2n + 1 and the like is stored in the entry 1-1 or entry 1-1 in the second associative memory device 120. 2 is stored. Similarly, a copy of the main memory data such as address 2, address n + 2, address 2n + 2, etc. is stored in entry 2-1 or entry 2-2.

  In the second associative storage device 120, the association degree, which is the number of entries that may store a copy of any main storage data in each area of the main storage address space 200, is 2. That is, the second associative storage device 120 stores a copy of the main memory data in the set associative format with the association degree of 2, and the total number of entries is 2n. Hereinafter, the association degree of 2 is expressed as 2 way.

  As for the first associative memory device 110, as indicated by the address mapping 202 to the first associative memory device 110, a copy of the main memory data may be stored in a 4-way full associative format, or the first associative memory device 110 may be used. As indicated by the address mapping 203 to the storage device 110, a copy of the main storage data may be stored in a 4-way set associative format.

  In the case of the 4-way full associative format, the first associative storage device 110 stores a copy of all main storage data in any of the four entries included regardless of the value of the address.

  In the case of the 4-way set associative format, the first associative memory device 110 includes two entries, an entry group including entries 1-1 to 1-4 and an entry group including entries 2-1 to 2-4. Contains entries. The first associative memory device 110 stores a copy of the main memory data in an entry in any entry group depending on whether the address value is odd or even. In this case, each entry group includes four entries, and the total number of entries included in the first associative storage device 110 is eight.

  As is apparent from the above description, the first associative memory device 110 has a feature that the degree of association is larger than that of the second associative memory device 120 and the total number of entries is smaller than that of the second associative memory device 120. Yes.

  FIG. 5 shows a configuration example of entries in the first associative storage device 110 when the first associative storage device 110 stores a copy of main storage data in a 4-way full associative format. The four entries included in the first associative memory device 110 include an ID number for identifying each, a main memory address, data transfer status information, LRU (Least Recently Used) information, and main memory. Data is associated and included.

  As for data transfer status information, the main memory address specified by the data reference instruction was mis-hit in both the first associative memory device 110 and the second associative memory device 120, and access to the main memory device 30 occurred. The state of data transfer related to the main storage data at the address is shown.

  In the case of the example of FIG. 5, for the entries with ID numbers 1 and 2, the main storage data has already been sent to the entry, and the copy of the main storage data in the entry is valid, but the entry with the ID number 3 Indicates that the transfer of the main storage data to the entry has not been completed, and the copy of the main storage data in the entry is not yet valid.

  The information of the LRU indicates the elapsed time since the last access to the entry of the first associative memory device 110, that is, the rank of the length of time when the data stored in the entry is not used. ing. Replacement of the copy of the main storage data in the entry is performed by the access control unit 100 with priority from the one with the smallest LRU value.

  In FIG. 5, an entry with an ID number of 4 is an unused entry.

  The configuration of each entry in the second associative storage device 120 is the same as that shown in FIG.

  The instruction storage unit 130 stores instruction information of a data reference instruction issued from the instruction issuing unit 20. The instruction information includes information such as the ID number of the instruction given to the data reference instruction by the instruction issuing unit 20 and the ID numbers of the entries in the first associative storage device 110 and the second associative storage device 120 used by the data reference instruction. Is included.

  The access control unit 100 controls the execution of the data reference instruction issued by the instruction issuing unit 20. The access control unit 100 first confirms in parallel with both the first associative memory device 110 and the second associative memory device 120 whether the main memory address designated by the data reference instruction is registered.

  When a hit occurs in the second associative memory device 120, the access control unit 100 accesses an entry in the second associative memory device 120 corresponding to the address.

  When a miss occurs in the second associative storage device 120 and a hit occurs in the first associative storage device 110, the access control unit 100 accesses the entry of the first associative storage device 110 corresponding to the address.

  When there is a miss-hit in both the first associative memory device 110 and the second associative memory device 120, the access control unit 100 sends the address to both the first associative memory device 110 and the second associative memory device 120. An entry for storing the data is secured. The access control unit 100 sends an access request to the main storage device 30 with the ID number information of the entry in the secured first associative storage device 110. The access control unit 100 stores the ID number of the entry secured in the second associative storage device 120 in association with the ID number of the entry secured in the first associative storage device 110.

  The access control unit 100 assigns the ID number of the entry in the first associative storage device 110 given to the reply data from the main storage device 30 and the entry in the second associative storage device 120 linked to the ID number. Reply data is stored in an entry in the first associative memory device 110 and the second associative memory device 120 specified by the ID number.

  When a replacement occurs in the second associative storage device 120, the access control unit 100 checks whether there is an unused entry in the first associative storage device 110. The data evicted from the second associative memory device 120 is stored in an unused entry in the first associative memory device 110.

  When there is a copy of data at any address in the main storage device 30 in both the first associative storage device 110 and the second associative storage device 120, the access control unit 100 determines the first associative storage device 110. The entry storing the copy of the main storage data at the address is set to the unused state.

  In the present embodiment, the operation of the access control unit 100 when the data reference instructions ReqA1 to A3, ReqB1 to B3, and ReqC1 to C3 are issued from the instruction issuing unit 30 is shown as an operation example 300 of the access control unit 100 in FIG. Shown in The first associative memory device 110 stores a copy of the main memory data in a 4-way full associative format indicated by the address mapping 202 to the first associative memory device 110, and the second associative memory device 120 A copy of the main memory data is stored in a two-way set social format indicated by mapping address 201 to associative memory 120. The access addresses of ReqA1 to A3, ReqB1 to B3, and ReqC1 to C3 are all addresses mapped to entry 1-1 or entry 1-2 in the second associative memory device 120.

  Upon receiving ReqA1 from the instruction issuing unit 20, the access control unit 100 secures entry 1 in the first associative memory 110 and entry 1-1 in the second associative memory device 120, and assigns entry number 1 to the request. And the main storage device 30 is accessed. The access control unit 100 stores entry 1-1 in association with entry 1 (step 1).

  When the access control unit 100 receives ReqB1 from the instruction issuing unit 20, the access control unit 100 secures entry 2 of the first associative memory 110 and entry 1-2 of the second associative memory device 120, and assigns entry number 2 to the request. And the main storage device 30 is accessed. The access control unit 100 stores the entry 1-2 in association with the entry 2 (step 2).

  Upon receiving ReqC1 from the instruction issuing unit 20, the access control unit 100 secures entry 3 in the first associative memory 110, replaces the address of ReqA in entry 1-1 in the second associative memory 120, and requests Is assigned the entry number 3 as an ID to access the main storage device 30. The access control unit 100 stores entry 1-1 associated with entry 3 and deletes 1-1 associated with entry 1. (Step 3).

  When receiving the ReqA2 from the instruction issuing unit 20, the access control unit 100 hits entry 1 of the first associative memory 110, and the status is being transferred, so the instruction information is associated with entry 1 and stored in the instruction storage unit 130. Store (step 4).

  When receiving the ReqB2 from the instruction issuing unit 20, the access control unit 100 hits the entry 2 of the first associative memory 110, and the status is being transferred, so the instruction information is associated with the entry 2 and stored in the instruction storage unit 130. Store (step 5).

  When receiving the ReqC2 from the instruction issuing unit 20, the access control unit 100 hits the entry 3 of the first associative memory 110, and the status is being transferred, so the instruction information is associated with the entry 3 and stored in the instruction storage unit 130. Store (step 6).

  When the access control unit 100 receives the reply of ReqA1 from the main storage device 30, since there is no entry in the second associative storage device 120 linked to the entry 1 assigned to the reply, the first associative memory The reply data is written only in the 110 entry 1. The access control unit 100 reads ReqA1 and ReqA2 associated with entry 1 from the instruction storage unit 130, and sends the reply data of ReqA1 and RaqA2 to the instruction issuing unit 20 together with the reply data of entry 1 of the first associative memory 110. Data is transmitted (step 7).

  When the access control unit 100 receives the reply of ReqB1 from the main storage device 30, since the entry of the second associative storage device 120 linked to the entry 2 attached to the reply is 1-2, the first The reply data is written in entry 2 of the associative memory 110 and entry 1-2 of the associative memory device 120. The access control unit 100 reads ReqB1 and ReqB2 associated with entry 2 from the instruction storage unit 130, and sends the reply data of ReqB1 and ReqB2 to the instruction issuing unit 20 together with the reply data of entry 2 of the first associative memory 110. Send data. Since there is an entry with the same address in the first associative memory 110 and the second associative memory device 120, the access control unit 100 sets entry 2 in the first associative memory 110 to be unused (step 8).

  When the access control unit 100 receives the reply of ReqC1 from the main storage device 30, since the entry of the second associative storage device 120 linked to the entry 3 assigned to the reply is 1-1, the first The reply data is written in entry 3 of the associative memory 110 and entry 1-1 of the associative memory device 120. The access control unit 100 reads ReqC1 and ReqC2 associated with entry 3 from the instruction storage unit 130, and sends the reply data of ReqC1 and ReqC2 to the instruction issuing unit 20 together with the reply data of entry 3 in the first associative memory 110. Send data. Since there is an entry with the same address in the first associative memory 110 and the second associative memory device 120, the access control unit 100 sets entry 3 in the first associative memory 110 to be unused (step 9).

  Upon receiving ReqA3 from the instruction issuing unit 20, the access control unit 100 hits entry 1 of the first associative memory 110, accesses entry 1, and transmits reply data to the instruction issuing unit 20 (step 10).

  When receiving the ReqB3 from the instruction issuing unit 20, the access control unit 100 hits the entry 1-2 of the first associative memory 120, accesses the entry 1-2, and transmits reply data to the instruction issuing unit 20 ( Step 11).

  Upon receiving ReqC3 from the instruction issuing unit 20, the access control unit 100 hits the entry 1-1 of the first associative memory 120, accesses the entry 1-1, and transmits reply data to the instruction issuing unit 20 ( Step 12).

  Thereafter, step 10 to step 12 are repeated.

  Next, the operation of this embodiment will be described in detail with reference to the flowcharts of FIGS.

  The access control unit 100 receives a data reference command from the command issuing unit 20 (S101). The access control unit 100 refers to the first associative memory device 110 and the second associative memory device 120 in parallel, and checks whether there is an entry that hits the access address of the received data reference instruction (S102).

  When the second associative memory device 120 is hit (Yes in S103), or the second associative memory device 120 is not hit (No in S103), the first associative memory device 110 is hit (Yes in S104) ), The access control unit 100 confirms the data transfer status of the hit entry (S107).

  When the data transfer status is “transferring” (Yes in S108), the access control unit 100 registers the command information of the data reference command by adding the entry ID to the command storage unit 130 (S111). The process proceeds to S121. If the data transfer status is not “transferring” (No in S108), the process proceeds to S125.

  If the second associative storage device 120 does not hit (No in S103) and the first associative storage device 110 does not hit (No in S104), the access control unit 100 determines that the first associative storage device 110 is not hit. (S105).

  If there is an unused entry (Yes in S106), the process proceeds to S110. When there is no unused entry (No in S106), the access control unit 100 refers to the information on the LRU in the first associative storage device 110, clears the information on the entry with the smallest LRU value, and sets the unused state. Set (S109).

The access control unit 100 registers the access address of the data reference instruction in the unused entry of the first associative storage device 110, and sets the data transfer status during transfer (S110). The access control unit 100 checks whether there is an unused entry in the second associative storage device 120 (S112).

  When there is no unused entry (No in S113), the access control unit 100 replaces one of the used entries in the second associative storage device 120 (S115). The access control unit 100 checks whether there is an unused entry in the first associative storage device 110 (S116). If there is no unused entry (No in S117), the process proceeds to S119. When there is an unused entry (Yes in S117), the access control unit 100 stores the data evicted from the second associative storage device 120 by the replacement in the unused entry of the first associative storage device 110 (S118). ), The process proceeds to S119.

  In the confirmation in S112, when there is an unused entry (Yes in S113), the access control unit 100 registers the access address of the data reference instruction in the unused entry of the second associative storage device 120 (S114). The access control unit 100 adds the entry ID to the command storage unit 130 and registers the command information of the data reference command (S119).

  The access control unit 100 assigns the ID of the corresponding entry in the first associative storage device 110, transmits a data reference instruction to the main storage device 30, and sets the ID of the entry secured in the second associative storage device 120. The ID is stored in association with the entry secured in the first associative storage device 110 (S120).

  The access control unit 100 receives the reply data from the main storage device 30, sets the data transfer status of the entry specified by the ID of the entry in the first associative storage device 110 assigned to the reply data to transferred, Reply data is written to the entry (S121).

  When the entry of the second associative storage device 120 is secured (Yes in S122), the access control unit 100 writes the reply data from the main storage device 30 to the second associative storage device 120 (S123). If an entry in the second associative storage device 120 is not secured (No in S122), the process proceeds to S124.

  The access control unit 100 reads command information from the command storage unit 130 (S124). The access control unit 100 reads data from the first associative storage device 110, transmits the data to the command issuing unit 30, and deletes the command information from the command storage unit 103 (S125).

  If the instruction storage unit 103 has instruction information related to the ID of the same entry (Yes in S126), the process proceeds to S124. If there is no instruction information regarding the ID of the same entry in the instruction storage unit 103 (No in S126), the process proceeds to S126.

  The access control unit 100 checks whether data relating to the same address exists in the first associative storage device 110 and the second associative storage device 120 (S127). If there is no data related to the same address (No in S128), the entire process ends. If there is data related to the same address (Yes in S128), the access control unit 100 uses the first associative storage device 110. In step S129, the entry storing the data relating to the address is set to unused (S129), and the entire process ends.

  This embodiment has an effect of improving the system performance by suppressing the occurrence of thrashing and improving the hit rate of the cache memory without much increase in hardware. The reason is that the memory access device 10 includes the first associative storage device 110 having a small number of entries but a large association degree, and the second associative storage device 120 having a large number of entries but a small association degree, and an access control unit. This is because 100 uses these two associative storage devices in parallel when processing data reference instructions, regardless of whether thrashing occurs or not.

  In a conventional general central processing unit, the second associative storage device 120 in this embodiment corresponds to a primary cache memory. In order to produce the effect as the primary cache memory, it is necessary to secure a certain number of entries for storing the main memory data. In that case, a highly associative method such as the full associative method is used in the hardware. It is difficult to adopt because the wear is large.

  Therefore, a set associative method that can suppress the hardware scale is adopted, but since this method has a low association degree, for example, when accesses of main memory addresses mapped to the same entry group in the cache are continuous, Thrashing occurs frequently and the performance deteriorates.

  In order to solve the above-described problem, the memory access device according to the present embodiment includes, in addition to the conventional primary cache memory, a full associative cache memory having a large association degree although the number of entries is small. Operates in parallel with the memory.

  Since the main memory data that has already been replaced and disappeared in the conventional primary cache memory still remains in the case of a fully associative cache memory with a large association, the cache hit rate increases, Reduces access to main memory and improves system performance. In addition, since the number of entries in the above-described fully associative cache memory is small, the hardware to be added can be reduced to a small scale.

  Conventionally, there is also a system provided with a full associative victim cache for storing data for storing data evicted from the primary cache. However, this victim cache is not implemented in parallel with the primary cache as in this embodiment, but is implemented in a hierarchical positional relationship with the primary cache. That is, since the victim cache is accessed after the primary cache misses, a penalty at the time of the primary cache miss occurs, which is an effect of improving the system performance compared to the present embodiment. Is small.

  Further, in the present embodiment, the memory access control device 10 includes an instruction storage unit 130 and temporarily stores a data reference instruction issued from the instruction issuing unit 20. When the main memory address specified by the data reference instruction causes a miss-hit in both the first associative memory device 110 and the second associative memory device 120, main memory access occurs and waits for reply data from the main memory. . In this embodiment, since the data reference instruction waiting for reply data is stored in the instruction storage unit 130, the access control unit 100 receives the subsequent instruction from the instruction issuing unit 20 and continues the processing, whereby the system It is possible to avoid a decrease in performance.

  Furthermore, in this embodiment, when a replacement occurs in the second associative memory device, if there is an unused entry in the first associative memory device 110, the replacement is evicted from the second associative memory device. The access control unit 100 copies the data to the first associative storage device 110, so that an effect of improving the cache hit rate can be expected.

In addition, the access control unit 100 determines that the first associative storage device 110 when a copy of data at any address in the main memory exists in both the first associative storage device 110 and the second associative storage device 120. The entry storing the data at the address is set to an unused state. As a result, it is possible to expect the cache hit rate to be improved by avoiding that both associative storage devices store the same main storage data in duplicate and effectively using entries.
<Second Embodiment>
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram showing the configuration of the memory access control device of this embodiment.

  The memory access control device 10 of this embodiment includes an access control unit 100, a first associative memory device 110, and a second associative memory device 120.

  The first associative memory device 110 and the second associative memory device 120 store a copy of the data stored in the main memory device 30 in association with the address of the main memory, and set the address coincident with the input address. Output the associated data.

  The number of entries for storing one data is the number of entries in which the first associative memory device 110 is smaller than the second associative memory device 120 and may store one data. The first associative memory device 110 is larger in the associative degree than the second associative memory device 120.

  As in the first embodiment, this embodiment can improve the system performance by suppressing the occurrence of thrashing and improving the hit rate of the cache memory without much hardware increase. effective. The reason is that the memory access device 10 includes the first associative storage device 110 having a small number of entries but a large association degree, and the second associative storage device 120 having a large number of entries but a small association degree, and an access control unit. This is because 100 uses these two associative storage devices in parallel when processing data reference instructions, regardless of whether thrashing occurs or not.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Memory access control system 10 Memory access control apparatus 100 Access control part 110 1st associative storage device 111 Address storage part 112 Data storage part 120 2nd associative storage apparatus 121 Address storage part 122 Data storage part 130 Instruction storage part 20 Instruction Issuing unit 30 Main memory device 200 Main memory address space 201 Address mapping to second associative memory device 202 Address mapping to first associative memory device 203 Address mapping to first associative memory device 110 300 Example of operation of access control unit 100

Claims (8)

A first associative memory device for storing a copy of data stored in a main memory in association with an address in the main memory, and outputting the data associated with the address that matches the input address; Two associative memory devices;
Instruction storage means;
Access control means;
With
The access control means inputs an address included in the data reference command from the command issuing unit of the central processing unit, outputs the address to the first associative memory device and the second associative memory device in parallel, and refers to the data The instruction information is associated with identification information of an entry storing one piece of the data that has been hit in the first and second associative storage devices with respect to the address included in the data reference instruction. After storing in the means, the instruction information of the data reference instruction is read from the instruction storage means, and the entry associated with the instruction information is accessed,
Number of entries, the first smaller than the content addressable memory device it is of the second content addressable memory, and the associativity is the number of the entries that may store one of the data, the The first associative memory device is larger than the second associative memory device,
Memory access control device. The access control means, when the address included in the data reference instruction causes a miss-hit in both the first associative memory device and the second associative memory device, the data for storing the data of the address entries, while securing both of the first content addressable memory and said second content addressable memory, the memory access control apparatus according to claim 1 to access the address of the main memory. When accessing the main memory, the access control means assigns the identification information of the secured entry to the access request, and based on the identification information of the entry given to reply data from the main memory. , the memory access control device according to claim 1 or 2 for determining the storage destination of the entry of the reply data. The first associative memory device and the second associative memory device further store, for each entry, data transfer status information indicating that the data is being transferred or transferred from the main memory. ,
The access control means detects that the data transfer process corresponding to any of the entries is completed, changes the corresponding data transfer status information from being transferred to transferred, and is associated with the entry. The memory access control device according to claim 1, wherein the data reference instruction is processed. When the replacement occurs in the second associative memory device, and there is an unused entry in the first associative memory device, the access control means is expelled from the second associative memory device in the replacement. The memory access control device according to claim 1, wherein the stored data is stored in the unused entry. In the first associative memory device, when the copy of the data of any address in the main memory exists in both the first associative memory device and the second associative memory device, the access control means The memory access control device according to claim 1, wherein the entry storing the data of the address is set to an unused state. A memory access control system including the memory access control device according to claim 1, the central processing unit, and the main memory. A first associative memory device for storing a copy of data stored in a main memory in association with an address in the main memory, and outputting the data associated with the address that matches the input address; A second associative memory device,
The number of entries that store one piece of data is the number of entries that the first associative storage device is smaller than the second associative storage device and that may store one piece of the data. A certain degree of association is provided in the memory access control device in which the first associative memory device is larger than the second associative memory device,
The address included in the data reference instruction is input from the instruction issuing unit of the central processing unit, and output in parallel to the first associative storage device and the second associative storage device, and the instruction information of the data reference instruction is The address included in the data reference instruction is stored in the instruction storage unit in association with the identification information of the entry that has been hit in the first and second associative storage devices, and from the instruction storage unit, Read the instruction information of the data reference instruction, and access the entry associated with the instruction information,
Memory access control method.

Images