JP2024011696A - Arithmetic processing apparatus and arithmetic processing method - Google Patents

Abstract

To provide an arithmetic processing apparatus and an arithmetic processing method for improving efficiency of data transfer.SOLUTION: A storage unit 134 stores data. On receipt of a data access request from an arithmetic unit or a superior cache, a control unit 131 accesses target data when the target data of the data access request exists in the storage unit 134, or acquires the target data when the target data does not exist in the storage unit 134, from a subordinate cache or a main memory and stores the target data in the storage unit 134. A cache miss information update unit 132 calculates the number of occurrences of cache miss indicating that the target data does not exist in the storage unit 134. A speculative prefetch unit 133 acquires speculative data based on the number of occurrences from the main memory or the subordinate cache, and stores the acquired speculative data in the storage unit 134.SELECTED DRAWING: Figure 2

Description

The present invention relates to an arithmetic processing device and an arithmetic processing method.

In recent years, the operating frequency of processors has improved dramatically. On the other hand, improvements in the operating speed of DRAM (Dynamic Random Access Memory), which is commonly used as main memory, have been slow, and technical research into architectures that make data transfer more efficient is needed to take full advantage of processor performance. It's thriving. In an information processing device, a cache memory whose data access is faster than a main memory is generally arranged in a CPU (Central Processing Unit). By placing recently referenced data on this cache memory, latency due to main memory reference can be reduced.

However, in order for the arrangement of the cache memory to reduce latency to be effective, it is necessary that the data to be referenced is stored in the cache memory. If there is no data to be referenced on the cache memory, an access to the main memory will occur, so even if a cache memory is provided, the data transfer speed becomes a bottleneck in the calculation speed. Therefore, attempts are being made to improve the data transfer speed by efficiently storing data in a cache memory using prefetching or the like.

As a cache management technique, a technique has been proposed in which the cache includes a direct map part and a multiway part managed by a cooperative replacement policy, and the multiway part functions as a victim cache for the direct map part. A victim cache is a cache for writing data evicted from the cache. Furthermore, a technique has been proposed in which an entry evicted from the cache is temporarily stored in a write buffer before being written back to the main memory, and if the requested data is in the write buffer, the data is returned to the cache. Also, conditional branch prediction predicts which branch to take, searches memory based on the prediction, and if the prediction is correct, the next instruction has already been fetched, but if the prediction is wrong, the conditional branch is Techniques have been proposed in which the problem is fetched speculatively until it is actually resolved. In addition, the data transferred to the work area in memory is stored in a specific cache area in the cache for data processing, and then the operation of evicting the data from the specific cache is repeated to store highly localized data in the cache memory. A technique has been proposed to leave the

Special table 2018-512650 publication Japanese Patent Application Publication No. 08-314802 US Patent Application Publication No. 2018/0322059 JP2011-86131A

However, in operations that involve many irregular accesses, such as sparse matrix operations, it is difficult to predict future data accesses. For example, it is very difficult to predict which data will be used in the future, such as vector data in sparse matrix-vector multiplication (SpMV). If future data access prediction fails, it becomes difficult to efficiently store data in the cache memory by prefetching, and it becomes difficult to improve the efficiency of data transfer. Furthermore, with any of the techniques described above, it is difficult to implement efficient prefetching in operations that involve many irregular accesses, and it is difficult to improve the efficiency of data transfer.

The disclosed technology has been developed in view of the above, and aims to provide an arithmetic processing device and an arithmetic processing method that improve the efficiency of data transfer.

In one aspect of the arithmetic processing device and the arithmetic processing method disclosed in the present application, the arithmetic processing device includes a calculation unit, a main memory, and one or a plurality of hierarchical caches. At least one of the caches includes the following parts. The storage unit stores data. The control unit receives a data access request from the calculation unit or the upper cache, and accesses the target data when the target data of the data access request exists in the storage unit. Further, when the target data does not exist in the storage unit, the control unit acquires the target data from the lower cache or the main memory and stores it in the storage unit. The information management unit calculates the number of occurrences of a cache miss indicating that the target data does not exist in the storage unit. The speculative prefetch unit acquires speculative data from the main memory or the lower cache based on the number of occurrences, and stores the acquired speculative data in the storage unit.

In one aspect, the present invention can streamline data transfer.

FIG. 1 is a schematic diagram showing the overall configuration of an information processing device. FIG. 2 is a block diagram of L1 and L2 caches according to the first embodiment. FIG. 3 is a diagram showing an example of memory addresses. FIG. 4 is a diagram of an example of cache miss information. FIG. 5 is a flowchart of data cache processing by the control unit according to the first embodiment. FIG. 6 is a flowchart of the cache miss information update process by the cache miss information update unit. FIG. 7 is a flowchart of speculative prefetch processing by the speculative prefetch unit. FIG. 8 is a block diagram of the L2 cache according to the second embodiment. FIG. 9 is a diagram showing the configuration of cache information according to the second embodiment. FIG. 10 is a flowchart of data cache processing by the control unit according to the second embodiment. FIG. 11 is a flowchart of data storage processing by the data monitor section. FIG. 12 is a flowchart of data cache processing when MRAM is used as a victim cache.

Embodiments of the arithmetic processing device and the arithmetic processing method disclosed in the present application will be described in detail below with reference to the drawings. Note that the following embodiments do not limit the arithmetic processing device and the arithmetic processing method disclosed in the present application.

FIG. 1 is a schematic diagram showing the overall configuration of an information processing device. As shown in FIG. 1, the information processing device 1 includes a calculation unit 11, an L1 cache 12, an L2 cache 13, an L3 cache 14, a main memory 15, an auxiliary storage device 16, a display device 17, and an input device 18. The calculation unit 11 is connected to each of the L1 cache 12, L2 cache 13, L3 cache 14, main memory 15, auxiliary storage device 16, display device 17, and input device 18 via a bus. The calculation unit 11, the L1 cache 12, the L2 cache 13, and the L3 cache 14 are installed, for example, in the CPU 10, which is a calculation processing device.

The calculation unit 11 is, for example, a CPU (Central Processing Unit) core. The calculation unit 11 reads various programs stored in the auxiliary storage device 16, develops them in the main memory 15, and uses the data stored in the L1 cache 12, L2 cache 13, L3 cache 14, and main memory 15. Perform calculations.

The L1 cache 12 is a cache memory that has a high operating speed and a smaller capacity than the L2 cache 12 and the L3 cache 14, and is the cache memory that is read first when data is accessed by the calculation unit 11. The L1 cache 12 is, for example, SRAM (Static Random Access Memory).

The L2 cache 13 is a cache memory that operates at a faster speed and generally has a larger capacity than the L1 cache 12. The L2 cache 13 is a cache memory that has a faster operation speed and generally has a larger capacity than the L1 cache 12, and is the cache memory that is read next when a cache miss occurs in the L1 cache 12 during data access by the calculation unit 11. It's memory. The L2 cache 13 is also, for example, SRAM.

The L3 cache 14 is a cache memory that has a faster operating speed and generally has a larger capacity than the L2 cache 13, and is the cache memory that is read next when a cache miss occurs in the L2 cache 13 during data access by the calculation unit 11. It's memory. The L3 cache 14 is also, for example, SRAM.

Here, in this embodiment, a case will be described in which the information processing device 1 has three cache memories, L1 cache 12, L2 cache 13, and L3 cache 14, but the number of cache memory hierarchies is not limited to this. For example, the information processing device 1 may not have the L2 cache 13 or the L3 cache 14, or may have four or more layers.

The main memory 15 is a main storage device with a lower operating speed and larger capacity than the L1 cache 12, L2 cache 13, and L3 cache 14. The main memory 15 stores data used in calculations by the calculation unit 11. The main memory 15 receives access from the calculation unit 11 when there is no data to be accessed in any of the L1 cache 12, L2 cache 13, and L3 cache 14. The main memory 15 is, for example, a DRAM (Dynamic Random Access Memory).

The auxiliary storage device 16 is, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive). The auxiliary storage device 16 stores an OS (Operating System) and various programs for performing calculations.

The display device 17 is, for example, a monitor or a display. The display device 17 presents the results of calculations by the calculation unit 11 to the user. The input device 18 is, for example, a keyboard or a mouse. The user inputs data and commands to the information processing device 1 using the input device 18 while referring to the screen displayed on the display device 17 . The display device 17 and the input device 18 may be configured as one piece of hardware.

FIG. 2 is a block diagram of the L1-L2 cache according to the first embodiment. In FIG. 2, in order to make the hierarchical structure of the L1 cache 12, L2 cache 13, and L3 cache 14 easier to understand, they are shown connected in multiple stages. In actual connection, each may be connected to a bus extending from the calculation unit 11 as shown in FIG.

The L1 cache 12 includes a control section 121 and a storage section 122. The storage unit 122 has cache information 123 that is a cached data group.

The control unit 121 receives a data request from the calculation unit 11. Then, the control unit 121 determines whether the data specified in the data request exists in the storage unit 122. If the specified data exists in the cache information 123 held by the storage unit 122, the control unit 121 extracts the specified data from the cache information 123 and sends it to the calculation unit 11 to respond.

On the other hand, if the data specified in the cache information 123 held by the storage unit 122 does not exist, the control unit 121 determines that there is a cache miss and outputs a data request to the L2 cache 13. Thereafter, upon receiving the requested data from the L2 cache 13, the control unit 121 stores the received data as cache information 123 held by the storage unit 122. Further, depending on the cache method, the L1 cache 12 may output the data received from the L2 cache 13 to the calculation unit 11.

Next, the L2 cache 13 will be explained. In this embodiment, the L2 cache 13 operates using a set associative method as a cache mapping method. FIG. 3 is a diagram showing an example of memory addresses. In this embodiment, the memory address 101 has, for example, a tag, a set, a block offset, and a byte offset, as shown in FIG. The tag and set together are called a block address. The block address is information indicating which block in the main memory 15. Further, the set is an index indicating in which set in the cache the data is stored. Further, the block offset is information indicating in which part of the block the requested data is located. Further, the byte offset is information indicating in which part of a word, which is a unit of one read/write, the requested data is located. Hereinafter, a memory address indicating a location where certain data is stored will be referred to as a memory address of that data.

Here, an example of the number of sets in the L2 cache 13 will be explained. The capacity of the area for storing cache information 135 in the storage unit 134 of the L2 cache 13 is calculated by the total product of the number of sets, the number of ways, and the block size. For example, the L2 cache 13 has 16 ways, 2048 sets, and a block size of 256 Bytes. In addition, the L2 cache 13 has 16 ways, 1024 sets, and a block size of 64 Bytes.

Returning to FIG. 2, the explanation will be continued. The L2 cache 13 according to this embodiment performs speculative prefetching on data that is frequently accessed irregularly when there is sufficient processing capacity. That is, the L2 cache 13 stores data determined to be frequently accessed irregularly in the storage unit 134 in advance as cache information 135 before the data is accessed. Here, in this embodiment, a case has been described in which the L2 cache 13 performs speculative prefetching based on irregular access, but the present invention is not limited to this, and other cache memories such as the L1 cache 12 and the L3 cache 14 may also perform the speculative prefetching. . However, considering the small capacity of the L1 cache 12 and the frequency of access from the calculation unit 11, the L1 cache 12 is not very suitable for the speculative prefetch based on irregular access according to the embodiment.

Details of the L2 cache 13 will be explained below. As shown in FIG. 2, the L2 cache 13 includes a control section 131, a cache miss information update section 132, a speculative prefetch section 133, and a storage section 134.

The control unit 131 receives a data request from the L1 cache 12. Then, the control unit 121 determines whether the data specified in the data request exists in the storage unit 134. If the specified data exists in the cache information 135 held by the storage unit 134, the control unit 131 extracts the specified data from the cache information 135, sends it to the L1 cache 12 and the calculation unit 11, and sends a response. Let's do it.

On the other hand, if the data specified in the cache information 135 held by the storage unit 134 does not exist, the control unit 131 determines that there is a cache miss and outputs a data request to the L3 cache 14. Further, the control unit 131 notifies the cache miss information updating unit 132 of a cache miss of the specified data. Thereafter, upon receiving the requested data from the L3 cache 14, the control unit 131 stores the received data as cache information 135 held by the storage unit 134. Further, depending on the cache method, the L1 cache 12 may output data received from the L3 cache 14 to the L1 cache 12.

The cache miss information 136 is a table for managing the frequency of occurrence of cache misses for each tag included in a memory address. FIG. 4 is a diagram of an example of cache miss information. In the cache miss information 136, tags and counter values corresponding to each tag are registered. The tag corresponds to the upper part of the memory address 101 shown in FIG. Further, the counter represents the number of cache misses that have occurred in the address range corresponding to the tag.

The cache miss information update unit 132 updates the cache miss information 136 in accordance with the change in the cache information 135. More specifically, the cache miss information update unit 132 receives a notification of a cache miss for specified data from the control unit 131 when a cache miss occurs. Next, the cache miss information update unit 132 refers to the cache miss information 136 stored in the storage unit 134. Then, the cache miss information update unit 132 determines whether an entry corresponding to the data specified in the cache miss information 136 exists. That is, the cache miss information update unit 132 determines whether or not an entry having the tag included in the memory address of the specified data exists in the cache miss information 136.

If the corresponding entry does not exist, the cache miss information update unit 132 adds an entry having the tag included in the memory address of the specified data to the cache miss information 136. Furthermore, the cache miss information update unit 132 sets the counter to its initial value. On the other hand, if a corresponding entry exists, the cache miss information update unit 132 increments the counter corresponding to the tag included in the memory address of the specified data in the cache miss information 136. That is, the cache miss information updating unit 132 accumulates the number of cache misses for each tag. When the cache miss information 136 is updated, the cache miss information update unit 132 notifies the speculative prefetch unit 133 of the update of the cache miss information 136.

Here, the L2 cache 13 may perform hardware prefetch such as stride prefetch. However, the cache miss information update unit 132 does not treat a hardware prefetch in the same way as a cache miss, and does not increment the count in the cache miss information 136 even if a hardware prefetch occurs.

Further, the cache miss information updating unit 132 may clear the entry of the cache miss information 136 when a predetermined condition is satisfied. For example, when a group of operations in a specific process is completed, the cache miss information update unit 132 may clear the entry of the cache miss information 136. This cache miss information update unit 132 is an example of an “information management unit”.

The speculative prefetch unit 133 prefetches uncached data from an address range that is frequently accessed irregularly when there is some free space on the bus between the L2 cache 13 and the L3 cache 14. That is, the speculative prefetch unit 133 acquires uncached data from the L3 cache 14 or the main memory 15, which is a lower memory, and stores it in the storage unit 134 as cache information 135.

Here, in normal prefetching such as hardware prefetching, prefetching is performed by estimating the regularity of data access. That is, if data accesses are performed according to a regularity that can be estimated within a certain address range, it is considered that the occurrence of cache misses in that address range can be suppressed by normal prefetching. From this, if cache misses occur frequently, it is assumed that data accesses are being performed with a degree of irregularity that can be inferred. In other words, an address range where a large number of cache misses occur can be considered an address range where irregular accesses occur frequently. Therefore, the speculative prefetch unit 133 determines that there is data to be irregularly accessed in the address range where the counter value is large in the cache miss information 136, and stores the data in the storage unit 134 of the L2 cache 13.

However, if the counter values in the cache miss information 136 are small overall, it can be said that irregular accesses have not occurred in any address range. Therefore, the speculative prefetch unit 133 has a determination threshold value in advance for determining the occurrence of irregular access. When the determination threshold is large, irregular accesses are often missed, and when it is small, irregular accesses are often erroneously detected. Therefore, it is preferable that the determination threshold value is determined according to the operating state of the information processing device 1.

In this way, data to be accessed irregularly is inferred in a specific address range, and data that is uncertain whether it will be accessed in the future is selected from that address range and prefetched. The prefetch performed by the speculative prefetch unit 133 is called speculative prefetch. The data targeted for speculative prefetch by the speculative prefetch unit 133 is an example of "speculative data." The details of the operation of the speculative prefetch unit 133 will be described below.

The speculative prefetch unit 133 receives an update notification of the cache miss information 136 from the cache miss information update unit 132. Next, the speculative prefetch unit 133 determines whether or not there is free space in the storage unit 134 to store the data. If there is a free area to store data, the speculative prefetch unit 133 selects one set in which a free way exists.

Next, the speculative prefetch unit 133 refers to the cache miss information 136. Then, the speculative prefetch unit 133 selects entries from among the entries stored in the cache miss information 136 in descending order of the counter value.

Next, the speculative prefetch unit 133 determines whether the counter value of the selected entry is greater than the determination threshold. If the counter value is larger than the determination threshold, the speculative prefetch unit 133 determines whether data corresponding to the tag of the selected set and the selected entry exists in the storage unit 134. If data corresponding to the selected set and tag already exists in the storage unit 134, the speculative prefetch unit 133 selects the entry with the next largest counter value from the cache miss information 136, and repeats the same process.

On the other hand, if the data corresponding to the selected set and tag does not exist in the storage unit 134, the speculative prefetch unit 133 can free up processing capacity of the bus between the L2 cache 13 and the L3 cache 14. Wait until. Specifically, the speculative prefetch unit 133 determines that there is sufficient processing capacity when the throughput of the bus between the L2 cache 13 and the L3 cache 14 is smaller than a preset throughput threshold. The speculative prefetch unit 133 can use, for example, the busy rate (usage rate) of the bus, the load/store ratio, the cache miss rate of the L2 cache 13, or the latency related to data acquisition as the amount of bus processing.

For example, when using the load/store ratio, the speculative prefetch unit 133 obtains the ratio of the number of load instructions and the number of store instructions to the executed instructions from the L1 cache 12. In the case of load instructions and store instructions, data is carried on the bus, so if the ratio is large, the speculative prefetch unit 133 can determine that the amount of processing on the bus is large. Furthermore, when there are many cache misses in the L2 cache 13, the amount of data that the L2 cache 13 acquires from the L3 cache 14 increases. Therefore, when there are many cache misses in the L2 cache 13, the speculative prefetch unit 133 can determine that the amount of bus processing is large. Furthermore, the latency related to data acquisition is the time required for the calculation unit 11 to acquire data from the L1 cache 12. The latency associated with data acquisition increases as the number of accesses to the L3 cache 14 and main memory 15 increases, so if this value is large, the speculative prefetch unit 133 can determine that the amount of bus processing is large.

After the processing capacity of the bus between the L2 cache 13 and the L3 cache 14 becomes available, the speculative prefetch unit 133 determines whether the data corresponding to the selected set and tag is not stored in the storage unit 134 while waiting. Check whether If data is not stored during standby, the speculative prefetch unit 133 acquires the corresponding data from the L3 cache 14 and stores it in the storage unit 134 of the L2 cache 13 . Thereby, the speculative prefetch unit 133 executes speculative prefetch processing.

FIG. 5 is a flowchart of data cache processing by the control unit according to the first embodiment. Next, the flow of data cache processing by the control unit 131 will be described with reference to FIG. Here, a case will be described in which access to data A by the calculation unit 11 occurs.

The control unit 131 receives a request to send data A from the L1 cache 12 (step S101).

Next, the control unit 131 determines whether data A exists in the cache information 135 stored in the storage unit 134 (step S102).

If data A does not exist in the cache information 135 stored in the storage unit 134 (step S102: negative), the control unit 131 notifies the cache miss information update unit 132 of the cache miss of data A (step S103).

Next, the control unit 131 requests the L3 cache 14 to transmit data A (step S104). Step S104 may be performed simultaneously with step S103 or before step S103.

Thereafter, the control unit 131 obtains data A from the L3 cache 14. Then, the control unit 131 stores the data A in the storage unit 134, which is an SRAM, as cache information 135 (step S105).

On the other hand, if the data A exists in the cache information 135 stored in the storage unit 134 (step S102: affirmative), the control unit 131 acquires the data A from the cache information 135 held in the storage unit 134. do. Then, the control unit 131 transmits the data A to the L1 cache 12 and the calculation unit 11 (step S106).

FIG. 6 is a flowchart of the cache miss information update process by the cache miss information update unit. Next, with reference to FIG. 6, the flow of the cache miss information update process by the cache miss information update unit 132 will be described.

The cache miss information update unit 132 receives a cache miss notification from the control unit 131 (step S201).

Next, the cache miss information update unit 132 determines whether or not there is an entry corresponding to the cache miss data, that is, an entry corresponding to the tag included in the memory address of the data specified in the notification, in the cache miss information 136. is determined (step S202).

If there is an entry corresponding to the cache-missed data (step S202: affirmative), the cache-miss information update unit 132 increments the counter value of the entry corresponding to the cache-missed data (step S203).

On the other hand, if there is no entry corresponding to the cache-missed data (step S202: negative), the cache-miss information update unit 132 adds the entry corresponding to the cache-missed data to the cache-miss information 136. (Step S204). At this time, the cache miss information update unit 132 sets the counter value of the added entry to the initial value.

FIG. 7 is a flowchart of speculative prefetch processing by the speculative prefetch unit. Next, with reference to FIG. 7, the flow of speculative prefetch processing by the speculative prefetch unit 133 will be described.

The speculative prefetch unit 133 receives an update notification of the cache miss information 136 from the cache miss information update unit 132 (step S301).

Next, the speculative prefetch unit 133 determines whether there is a free area in the storage unit 134 to store data (step S302). If there is no free space to store the data (step S302: negative), the speculative prefetch unit 133 ends the speculative prefetch process.

On the other hand, if there is a free area to store data (step S302: affirmative), the speculative prefetch unit 133 selects a set in which a free way exists (step S303).

Next, the speculative prefetch unit 133 refers to the cache miss information 136. Then, the speculative prefetch unit 133 selects the entry with the largest counter value among the unselected entries among the entries registered in the cache miss information 136 (step S304).

Next, the speculative prefetch unit 133 determines whether the counter value of the selected entry is larger than the determination threshold (step S305). If the counter value of the selected entry is less than or equal to the determination threshold (step S305: negative), the speculative prefetch unit 133 ends the speculative prefetch process.

On the other hand, if the counter value of the selected entry is larger than the determination threshold (step S305: affirmative), the speculative prefetch unit 133 determines whether data corresponding to the selected set and tag exists in the storage unit 134. (Step S306). If data corresponding to the selected set and tag already exists in the storage unit 134 (step S306: affirmative), the speculative prefetch unit 133 returns to step S304.

On the other hand, if the data corresponding to the selected set and tag does not already exist in the storage unit 134 (step S306: negative), the speculative prefetch unit 133 controls the bus between the L2 cache 13 and the L3 cache 14. The processing waits until processing capacity becomes available (step S307).

After that, the speculative prefetch unit 133 checks again whether data corresponding to the selected set and tag is stored in the storage unit 134 (step S308). If the data corresponding to the selected set and tag is stored in the storage unit 134 (step S308: affirmative), the speculative prefetch unit 133 returns to step S304.

On the other hand, if the data corresponding to the selected set and tag is not stored in the storage unit 134 (step S308: negative), the speculative prefetch unit 133 acquires the corresponding data from the L3 cache 14. Then, the speculative prefetch unit 133 stores the cache information 135 in the storage unit 134 (step S309).

As described above, the cache of the information processing apparatus according to this embodiment speculatively prefetches data in an address range where cache misses occur frequently. Thereby, when irregular data access is performed, it is possible to improve the possibility that data is prefetched. Therefore, it is possible to use the limited memory bandwidth without wasting it, and data transfer can be made more efficient.

FIG. 8 is a block diagram of the L2 cache according to the second embodiment. In FIG. 8, details of the L1 cache 12 are omitted. The L2 cache 13 according to this embodiment includes a storage unit 134 that is a mixed memory of an SRAM 137 and an MRAM 138 that is a memory with a higher storage density than the SRAM 137. In the storage unit 134, the SRAM 137 is the main area, and the MRAM 138 is the spare area. The L2 cache 13 then stores the data in the MRAM 138 in speculative prefetch. Furthermore, the L2 cache 13 moves frequently accessed data among the data stored in the MRAM 138 to the SRAM 137. Details of the L2 cache 13 according to this embodiment will be explained below. In the following description, descriptions of the operations of the same parts as in the first embodiment will be omitted.

As shown in FIG. 8, the L2 cache 13 according to the present embodiment includes a data monitor section 140 in addition to each section according to the first embodiment. Furthermore, in the L2 cache 13 according to this embodiment, the storage unit 134 is a mixed memory of an SRAM 137 and an MRAM (Magnetoresistive Random Access Memory) 138. MRAM 138 is a memory with higher storage density than SRAM 137.

SRAM 137 stores cache information 135. The SRAM 137 has fields and functions similar to general cache memory.

MRAM 138 stores auxiliary cache information 139 and cache miss information 136. The auxiliary cache information 139 is a data group stored in the storage unit 134 by speculative prefetch performed by the speculative prefetch unit 133.

FIG. 9 is a diagram showing the configuration of cache information according to the second embodiment. The storage unit 134 collectively holds the cache information 135 stored in the SRAM 137 and the auxiliary cache information 139 stored in the MRAM 138 as one memory array 200. For example, in the example shown in FIG. 9, the storage unit 134 stores data as a 4-way associative memory array 200. In the auxiliary cache information 139 of the MRAM 138, a reference counter indicating the number of times each data is referenced, shown as Reference Count in FIG. 9, is registered for each block. The reference counter is an approximately 2-bit counter.

The control unit 131 receives a data transmission request from the L1 cache 12. Then, the control unit 131 determines whether the data specified in the transmission request is stored in the storage unit 134. In this case, the control unit 131 searches for data in the memory array 200 that collects the cache information 135 and the auxiliary cache information 139 shown in FIG. That is, the control unit 131 determines whether it exists in the cache information 135 or the auxiliary cache information 139. If the specified data is stored in the storage unit 134, the control unit 131 acquires the specified data from the cache information 135 or the auxiliary cache information 139 held by the storage unit 134. After that, the control unit 131 transmits the acquired data to the L1 cache 12 and the calculation unit 11.

Furthermore, the control unit 131 determines whether the storage location of the cache hit data is the MRAM 138 or not. If the acquired data is not stored in the MRAM 138, the control unit 131 ends the data caching process while leaving the cache hit data stored in the SRAM 137. On the other hand, if the storage location of the cache hit data is the MRAM 138, the control unit 131 notifies the data monitor unit 140 of access to the cache hit data.

The speculative prefetch unit 133 receives a cache miss notification from the cache miss information update unit 132. Then, the speculative prefetch unit 133 uses the counter value in the cache miss information 136 to identify the address range in which the irregularly accessed data is stored. Thereafter, the speculative prefetch unit 133 acquires data in the specified address range from the L3 cache 14.

Here, the data subject to speculative prefetching is less likely to be accessed than other data stored in the storage unit 134 including other prefetched data such as hardware prefetching. Therefore, even if the data to be subjected to speculative prefetching is stored in a memory whose operating speed is relatively slow, the effect on the data transfer speed is small. Further, by retaining more data to be subjected to speculative prefetching, the possibility of access can be improved, and the effect of speculative prefetching can be increased. However, if the data obtained by speculative prefetching is frequently accessed, it is preferable that the data be stored in a memory whose operating speed is as fast as possible.

Therefore, the speculative prefetch unit 133 stores the acquired data as auxiliary cache information 139 held in the MRAM 138 of the storage unit 134. That is, the speculative prefetch unit 133 stores data to be speculatively prefetched in the MRAM 138 and performs speculative prefetching.

The data monitor unit 140 moves data to the SRAM 137 according to the access frequency of the data stored in the MRAM 138. Details of the data monitor section 140 will be explained below.

The data monitor unit 140 has a movement threshold for determining movement from MRAM 138 to SRAM 137. The data monitor unit 140 receives notification from the control unit 131 of access to cache hit data. Then, the data monitor unit 140 increments the reference counter of the cache hit data in the auxiliary cache information 139. Here, if the write speed is particularly slow, the data monitor unit 140 may change the increment amount so that the increment amount in the case of data access by writing is larger than the increment amount in the case of data access by reading.

Next, the data monitor unit 140 determines whether the reference counter of the cache hit data exceeds the movement threshold. If the reference counter of the cache hit data exceeds the movement threshold, the data monitor unit 140 determines whether there is a free space in the SRAM 137 to store the cache hit data.

If there is free space in the SRAM 137 to store the cache hit data, the data monitor unit 140 moves the cache hit data from the MRAM 138 to the SRAM 137.

On the other hand, if there is no free space in the SRAM 137 to store the cache hit data, the data monitor unit 140 selects a free space to store the cache hit data from among the data stored in the SRAM 137. Select replacement data to secure. The data monitor unit 140 selects replacement data using a commonly used method such as pseudo LRU (Least Recently Used). The data monitor unit 140 then moves the cache hit data from the MRAM 138 to the SRAM 137. Furthermore, the data monitor unit 140 moves the selected replacement data from the SRAM 137 to the MRAM 138.

FIG. 10 is a flowchart of data cache processing by the control unit according to the second embodiment. Next, with reference to FIG. 10, the flow of data cache processing by the control unit 131 according to this embodiment will be described. Here, a case will be described in which access to data A by the calculation unit 11 occurs.

The control unit 131 receives a request to send data A from the L1 cache 12 (step S401).

Next, the control unit 131 determines whether data A exists in either the cache information 135 or the auxiliary cache information 139 stored in the storage unit 134 (step S402).

If the data A does not exist in either the cache information 135 or the auxiliary cache information 139 stored in the storage unit 134 (step S402: negative), the control unit 131 updates the cache miss information update unit 132 with the cache miss of the data A. Notify (step S403).

Next, the control unit 131 requests the L3 cache 14 to transmit data A (step S404).

Thereafter, the control unit 131 obtains data A from the L3 cache 14. Then, the control unit 131 stores data A in the SRAM 137 as cache information 135 (step S405).

On the other hand, if data A exists in either the cache information 135 or the auxiliary cache information 139 stored in the storage unit 134 (step S402: affirmative), the control unit 131 controls the cache information held by the storage unit 134. 135 or cache auxiliary information 139. Then, the control unit 131 transmits the data A to the L1 cache 12 and the calculation unit 11 (step S406).

After that, the control unit 131 determines whether the storage location of data A is the MRAM 138 (step S407). If the storage location of data A is not the MRAM 138 (step S407: negative), the control unit 131 leaves data A as is and ends the data cache processing.

On the other hand, if the storage location of data A is MRAM 138 (step S407: affirmative), control unit 131 notifies data monitor unit 140 of access to data A (step S408). After that, the control unit 131 ends the data cache processing.

Here, the flow of speculative prefetch by the speculative prefetch unit 133 according to this embodiment is similar to the flow shown in FIG. 7 . However, the speculative prefetch unit 133 according to this embodiment stores data in the MRAM 138 in step S309.

FIG. 11 is a flowchart of data storage processing by the data monitor section. Next, with reference to FIG. 11, the flow of data cache storage processing by the data monitor unit 140 will be described. Here, a case will be described in which access to data A by the control unit 131 occurs.

The data monitor unit 140 receives from the control unit 131 a notification of access to the cache hit data A (step S501).

Next, the data monitor unit 140 increments the reference counter for data A in the auxiliary cache information 139 (step S502).

Next, the data monitor unit 140 determines whether the reference counter of data A is larger than the movement threshold (step S503). If the reference counter of data A is less than or equal to the movement threshold (step S503: negative), the data monitor unit 140 ends the data storage process.

On the other hand, if the reference counter for data A is larger than the movement threshold (step S503: affirmative), the data monitor unit 140 determines whether there is free space in the SRAM 137 to store data A ( Step S504).

If there is free space in the SRAM 137 to store the data A (step S504: affirmative), the data monitor unit 140 moves the data A from the MRAM 138 to the SRAM 137 and stores it in the SRAM 137 (step S505). Thereafter, the data monitor unit 140 ends the data storage process.

On the other hand, if there is no free space in the SRAM 137 to store data A (step S504: negative), the data monitor unit 140 selects replacement data from among the data stored in the SRAM 137 (step S506). ). Here, a case will be described in which the data monitor unit 140 selects data B as the replacement data.

Next, the data monitor unit 140 moves data A from the MRAM 138 to the SRAM 137 and stores it in the SRAM 137. Furthermore, the data monitor unit 140 moves data B from the SRAM 137 to the MRAM 138 and stores it in the MRAM 138 (step S507). Thereafter, the data monitor unit 140 ends the data storage process.

As explained above, the L2 cache according to this embodiment is a mixed memory of SRAM and memory with higher storage density than SRAM, and the data to be speculatively prefetched is transferred to the memory with higher storage density than SRAM. Store. Furthermore, when the data stored in MRAM is accessed frequently, the L2 cache according to the present embodiment moves the data to SRAM. In this way, by storing speculative prefetch data that is unlikely to be accessed among the data stored in the L2 cache in MRAM with high storage density, data transfer speed can be suppressed while reducing speculative prefetch data. Can hold more data. Thereby, the cache hit rate due to speculative prefetching can be improved, and the effect of speculative prefetching can be increased.

(Modified example)
The MRAM 138 in the second embodiment can also be used as a victim cache within the L2 cache 13. The operation when using the MRAM 138 as a victim cache will be described below.

FIG. 12 is a flowchart of data cache processing when MRAM is used as a victim cache. With reference to FIG. 12, data cache processing when using the MRAM 138 as a victim cache will be described. Here, a case will be described in which the calculation unit 11 requests access to data A and data A does not exist in the L2 cache 13.

The control unit 131 receives an acquisition request for data A from the L1 cache 12 and determines whether data A is stored as either cache information 135 or auxiliary cache information 139 in the storage unit 134. In this case, since data A is not stored in the storage unit 134 and the control unit 131 cannot detect data A, a cache miss of data A occurs (step S601).

Next, the control unit 131 requests the L3 cache 14 to transmit data A (step S602).

Next, the control unit 131 determines whether there is any free space in the SRAM 137 to store the data A (step S603). If there is free space to store data A (step S603: affirmative), the control unit 131 proceeds to step S608.

On the other hand, if there is no free space to store the data A (step S603: negative), the control unit 131 deletes the data from the cache information 135 of the SRAM 137 in order to secure the free space to store the data A. Data B to be processed is selected (step S604).

Next, the control unit 131 determines whether there is a free area in the MRAM 138 to store the data B (step S605). If there is free space to store data B (step S605: affirmative), the control unit 131 proceeds to step S607.

On the other hand, if there is no free space to store the data B (step S605: negative), the control unit 131 deletes the data from the auxiliary cache information 139 of the MRAM 138 in order to secure a free space to store the data B. Select data. Then, the control unit 131 deletes the selected data from the auxiliary cache information 139 of the MRAM 138 (step S606). After that, the control unit 131 proceeds to step S607.

Next, the control unit 131 stores data B in the MRAM 138 (step S607).

Thereafter, the control unit 131 obtains data A from the L3 cache 14. Then, the control unit 131 stores data A in the SRAM 137 (step S608).

As explained above, the MRAM in the L2 cache can also be used as a victim cache in the L2 cache. This allows the MRAM in the L2 cache to be used more efficiently.

1 Information Processing Device 11 Arithmetic Unit 12 L1 Cache 13 L2 Cache 14 L3 Cache 15 Main Memory 16 Auxiliary Storage Device 17 Display Device 18 Input Device 121 Control Unit 122 Storage Unit 123 Cache Information 131 Control Unit 132 Cache Miss Information Update Unit 133 Speculative Prefetch unit 134 Storage unit 135 Cache information 136 Cache miss information 140 Data monitor unit

Claims (8)

An arithmetic processing device having an arithmetic unit and one or a plurality of hierarchical caches,
At least one of the caches includes:
a storage unit that stores data;
Upon receiving a data access request from the arithmetic unit or upper cache, if the target data of the data access request exists in the storage unit, the target data is accessed, and if the target data does not exist in the storage unit, the target data is accessed. a control unit that acquires target data from a lower cache or main memory and stores it in the storage unit;
an information management unit that calculates the number of cache misses that indicate that the target data does not exist in the storage unit;
and a speculative prefetch unit that acquires speculative data from the main memory or the lower cache based on the number of occurrences and stores the acquired speculative data in the storage unit. Device. The information management unit calculates the number of occurrences for each address range,
The speculative prefetch unit selects one of the address ranges based on the number of occurrences and acquires the speculative data included in the selected address range. arithmetic processing unit. The storage unit has a main area and a spare area,
The arithmetic processing device according to claim 1, wherein the speculative prefetch unit stores the speculative data in the spare area. A claim further comprising a data monitor unit that calculates an access frequency for each of the plurality of data stored in the spare area, selects data based on the access frequency, and stores the selected data in the main area. The arithmetic processing device according to item 3. The control unit acquires the target data from the lower cache or the main memory when the target data does not exist in the storage unit, and acquires the target data from the lower cache or the main memory when the target data is not stored in the main area. 4. The arithmetic processing device according to claim 3, wherein specific data is moved from the main area to the spare area and the target data is stored in the main area. The speculative prefetch unit determines whether or not there is sufficient processing capacity on the bus between the cache in which it is mounted and the main memory or the lower cache, and if there is sufficient processing capacity, the speculative prefetch unit 2. The arithmetic processing device according to claim 1, wherein speculative data is acquired from the main memory or the lower cache, and the acquired speculative data is stored in the storage unit. The speculative prefetch unit calculates a value of an index representing the processing amount of the bus, and determines whether or not there is enough processing capacity based on a comparison between the calculated value and a threshold value. 7. The arithmetic processing device according to claim 6. An arithmetic processing method using an arithmetic unit, a main memory, and one or a plurality of hierarchical caches, the method comprising:
at least one of the caches,
receive a data access request from the arithmetic unit or upper cache;
accessing the target data when the target data of the data access request exists in the storage area of the cache;
If the target data does not exist in the storage area, acquiring the target data from a lower cache or the main memory and storing it in the storage area;
calculating the number of occurrences of cache misses indicating that the target data does not exist in the storage area;
An arithmetic processing method comprising: acquiring speculative data from the main memory or the lower cache based on the number of occurrences, and storing the acquired speculative data in the storage area.

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