JP5720042B2 - SiC substrate dry etching method - Google Patents
SiC substrate dry etching method Download PDFInfo
- Publication number
- JP5720042B2 JP5720042B2 JP2011065917A JP2011065917A JP5720042B2 JP 5720042 B2 JP5720042 B2 JP 5720042B2 JP 2011065917 A JP2011065917 A JP 2011065917A JP 2011065917 A JP2011065917 A JP 2011065917A JP 5720042 B2 JP5720042 B2 JP 5720042B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- dry etching
- sic substrate
- substrate
- sic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 36
- 238000001312 dry etching Methods 0.000 title claims description 26
- 238000000034 method Methods 0.000 title claims description 17
- 238000005530 etching Methods 0.000 claims description 37
- 238000001816 cooling Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Drying Of Semiconductors (AREA)
Description
本発明は、ＳｉＣ基板のドライエッチング方法に関するものである。 The present invention relates to a method for dry etching a SiC substrate.
SiC基板又はエピタキシャル成長させたSiC膜を有する基板（以下、纏めて「ＳｉＣ基板」と総称する。）を使って各種デバイスを作製する場合、ドライエッチング工程が必要になる。
SiC基板をドライエッチングするには高密度プラズマを発生できる、例えばICPプラズマエッチング装置のようなエッチング装置を用いて塩素系ガスやフッ素系ガスを用い、エッチングマスクにはSiC基板との選択比を確保するため金属やSiO2膜を用いることが一般的である。
When various devices are manufactured using an SiC substrate or a substrate having an epitaxially grown SiC film (hereinafter collectively referred to as “SiC substrate”), a dry etching process is required.
For dry etching of SiC substrates, high-density plasma can be generated. For example, chlorine-based gas or fluorine-based gas is used with an etching device such as an ICP plasma etching device, and the etching mask has a selective ratio with the SiC substrate. Therefore, it is common to use a metal or SiO 2 film.
フッ素系ガスとしては、CF4やSF６が一般的に用いられる。AlやNiなどの金属やSiO2をマスクとしてエッチングすると、エッチング側壁は垂直に近くなることが多く、またエッチング開口部分は直角に近くなってしまうことが多い。さらに、エッチングマスクに金属やSiO2を用いるため、成膜装置が必要になり、成膜工程やマスク膜の除去工程も必要になり、工程が複雑になる。 As the fluorine-based gas, CF 4 or SF 6 is generally used. When etching is performed using a metal such as Al or Ni or SiO 2 as a mask, the etching side wall is often close to the vertical, and the etching opening is often close to a right angle. Further, since metal or SiO 2 is used for the etching mask, a film forming apparatus is required, and a film forming process and a mask film removing process are also required, which complicates the process.
レジストをマスクとしたSiC基板のドライエッチング方法も提案されている（特許文献１参照）。これは、SiC基板上にレジスト材料によりパターンマスクを形成した後、SiC基板を一定の温度に保ちながら反応性イオンビームなどの異方性プラズマエッチングを行い、そのプロセス中にパターンマスクを変形・変質してその側壁をなだらかに傾斜させ、SiC基板のエッチング面側壁になだらかな傾斜をつけるようにするものであるが、１段のテーパー角形成に止まるため、所望のエッチング側壁を得るのに十分ではない。 A dry etching method of an SiC substrate using a resist as a mask has also been proposed (see Patent Document 1). This is because after forming a pattern mask with a resist material on a SiC substrate, anisotropic plasma etching such as reactive ion beam is performed while keeping the SiC substrate at a constant temperature, and the pattern mask is deformed and altered during the process. Then, the side wall is gently inclined so that the side surface of the etched surface of the SiC substrate is gently inclined. However, since the formation of the taper angle at one stage is stopped, it is not sufficient to obtain a desired etching side wall. Absent.
本発明は、エッチング側壁を２段以上の傾斜構造にしてテーパー角を低角度にするとともに、エッチング後のマスク剥離工程を簡素化できるＳｉＣ基板のドライエッチング方法を提供することを課題とする。 It is an object of the present invention to provide a dry etching method for an SiC substrate that can reduce the taper angle by making the etching sidewall have an inclined structure having two or more steps, and simplify the mask peeling process after etching.
上記の課題は、以下のＳｉＣドライエッチング方法によって解決される。
ＳｉＣ基板にSF6のみ又はSF6とAｒとの混合ガスによるドライエッチングにより凹部を形成する際に、エッチングマスクとしてレジスト現像後に１３０℃〜１６０℃の温度で１分〜５分ポストベークするとともに、基板印加バイアス電力とアンテナ電力との比（基板印加バイアス電力／アンテナ電力）を０．０１〜０．１としたことを特徴とするドライエッチング方法。
The above problem is solved by the following SiC dry etching method.
When a recess is formed on the SiC substrate by dry etching using only SF 6 or a mixed gas of SF 6 and Ar, post-baking is performed at a temperature of 130 ° C. to 160 ° C. for 1 minute to 5 minutes after resist development as an etching mask, A dry etching method characterized in that a ratio of substrate applied bias power to antenna power (substrate applied bias power / antenna power) is set to 0.01 to 0.1.
本発明によれば、レジストをマスクにしてSiC基板を深さ1μｍ以上ドライエッチングすることができ、金属やSiO2膜をエッチングマスクにする必要がなく、簡素化された工程でSiC基板に凹部分を形成できる。凹部分の側壁のテーパー角度も開口部分に近い方が緩やかな２段階の傾斜形状にでき、デバイス動作時のエッジ部分への電界集中を緩和することができ、耐圧の向上が期待できる。 According to the present invention, a SiC substrate can be dry-etched by a depth of 1 μm or more using a resist as a mask, and there is no need to use a metal or SiO 2 film as an etching mask. Can be formed. The taper angle of the side wall corresponding to the concave portion can be made a gentle two-step inclined shape closer to the opening portion, the electric field concentration on the edge portion during device operation can be reduced, and an improvement in breakdown voltage can be expected.
（実施の形態1）
レジストマスクを用いたSiC基板のドライエッチング方法を実施の形態１を用いて説明する。
結晶構造が4H-SiCでC面4°オフ基板（又はSiCエピタキシャル膜付きの4°オフ基板）を有機洗浄、RCA洗浄した後、レジストを2μｍの厚さで塗布、露光、現像を行いエッチングパターンを形成した。その後、140℃で1分間のポストベークを行った。このレジスト付きパターン基板をICP方式のドライエッチング装置でSF6をエッチングガスとして圧力0.5Paでドライエッチングした。エッチングガスは、SF 6 のみ又はSF 6 とAｒとの混合ガスがよい。レジストマスクは、レジスト現像後に１３０℃〜１６０℃の温度で１分〜５分ポストベークするのがよい。
(Embodiment 1)
A dry etching method of an SiC substrate using a resist mask will be described using the first embodiment.
The crystal structure is 4H-SiC, and the C-plane 4 ° off substrate (or 4 ° off substrate with SiC epitaxial film) is organically cleaned and RCA cleaned, then the resist is applied in a thickness of 2μm, exposed, and developed to produce an etching pattern. Formed. Thereafter, post-baking was performed at 140 ° C. for 1 minute. This resist-patterned substrate was dry-etched with an ICP dry etching apparatus at a pressure of 0.5 Pa using SF 6 as an etching gas. The etching gas is preferably SF 6 alone or a mixed gas of SF 6 and Ar. The resist mask is preferably post-baked at a temperature of 130 ° C. to 160 ° C. for 1 minute to 5 minutes after resist development.
図１にSiO2膜をエッチングした場合のレジストとの選択比が基板印加バイアス電力（以下、「バイアスパワー」という）とアンテナ電力（以下、「アンテナパワー」という）の比によって変化する様子を示す。
図１によれば、バイアス/アンテナパワーの比が小さい方が、選択比が高くなることがわかる。エッチングする対象がSiC基板になってもこの傾向は同様である。バイアス/アンテナパワー比が0.1以下、好ましくは0.01にすることが、選択比を大きくすることに有利である。
FIG. 1 shows how the selection ratio with respect to a resist when an SiO 2 film is etched varies depending on the ratio of the bias power applied to the substrate (hereinafter referred to as “bias power”) and the antenna power (hereinafter referred to as “antenna power”). .
As can be seen from FIG. 1, the selection ratio increases as the bias / antenna power ratio decreases. This tendency is the same even if the object to be etched is a SiC substrate. It is advantageous for increasing the selection ratio that the bias / antenna power ratio is 0.1 or less, preferably 0.01.
図１に示した結果をもとに、SiC基板（C面）でのドライエッチングを行った。SF6ガス流量50sccm、圧力0.5Pa、アンテナパワー400W、バイアスパワー20Wで240秒でドライエッチングした。このときSiC基板は裏面からHeガスで冷却している。この条件でドライエッチングすると、SiC基板は約0.2μｍ/minの早さでエッチングされる。その時のレジストのエッチングレートは約0.4μｍ/minである。 Based on the results shown in FIG. 1, dry etching was performed on the SiC substrate (C surface). Dry etching was performed in 240 seconds with an SF 6 gas flow rate of 50 sccm, a pressure of 0.5 Pa, an antenna power of 400 W, and a bias power of 20 W. At this time, the SiC substrate is cooled with He gas from the back surface. When dry etching is performed under these conditions, the SiC substrate is etched at a rate of about 0.2 μm / min. At that time, the etching rate of the resist is about 0.4 μm / min.
ラインとスペースが2μｍ/2μｍの間隔でパターニングされた場合のエッチング断面形状を図２に示す。これは収束イオンビーム装置（FIB）で断面を切り出した写真である。表面にPtの保護膜が形成されている。エッチング深さは約0.8μｍである。エッチング側壁の角度は、凹部底に近い方は約55°になっており、開口部に近い方は約35°になっている。この実施例の条件でこのように側壁が２段階のテーパー角度がつくようにドライエッチングされ、１段目、２段目の角度はかなりテーパーになるようエッチングできる。 FIG. 2 shows an etching cross-sectional shape when lines and spaces are patterned at intervals of 2 μm / 2 μm. This is a photograph of a cross section cut out by a focused ion beam device (FIB). A protective film of Pt is formed on the surface. The etching depth is about 0.8 μm. The angle of the etching side wall is about 55 ° near the bottom of the recess, and about 35 ° near the opening. Under the conditions of this embodiment, dry etching is performed so that the side wall has a two-step taper angle as described above, and the first and second step angles can be etched so as to be considerably tapered.
次に直径50μｍの円形にドライエッチングした場合の断面形状を図３に示す。エッチング深さは同様に約0.8μｍであるが、エッチング側壁の角度は凹部底に近い方は約35°になっており、開口部に近い方は約20°になっている。エッチング面積が広い方がさらにテーパー角度は緩やかになる。このようにテーパー角度はエッチング幅（面積）によって違う。
このような２段のテーパー形状になることによってエッチングした端部が鋭角にならなくなり電界集中を緩和でき、このエッチング方法で作製したSiC半導体素子のリーク電流の発生を抑え耐圧の向上を達成できる。
Next, FIG. 3 shows a cross-sectional shape when dry etching is performed into a circle having a diameter of 50 μm. The etching depth is similarly about 0.8 μm, but the angle of the etching side wall is about 35 ° near the bottom of the recess and about 20 ° near the opening. The taper angle becomes gentler as the etching area increases. Thus, the taper angle varies depending on the etching width (area).
With such a two-stage tapered shape, the etched end does not become an acute angle, and the electric field concentration can be mitigated, and the generation of a leakage current of the SiC semiconductor device manufactured by this etching method can be suppressed and the breakdown voltage can be improved.
（実施の形態２）
エッチング条件のアンテナパワーとバイアスパワーを更に変更した実施の形態２を説明する。
結晶構造が4H-SiCでC面4°オフ基板（又はSiCエピタキシャル膜付きの4°オフ基板）を有機洗浄、RCA洗浄した後、レジストを2.5μｍの厚さで塗布、露光、現像を行いエッチングパターンを形成した。その後、140℃で1分間のポストベークを行った。このレジスト付きパターン基板をICP方式のドライエッチング装置でSF6をエッチングガスとして圧力0.5Paでアンテナパワー700W、バイアスパワー７W（すなわちバイアス/アンテナパワー比が0.01）でドライエッチングした。
(Embodiment 2)
A second embodiment in which the antenna power and the bias power in the etching conditions are further changed will be described.
The crystal structure is 4H-SiC and the C-plane 4 ° off substrate (or 4 ° off substrate with SiC epitaxial film) is organically cleaned and RCA cleaned, and then the resist is applied with a thickness of 2.5μm, exposed and developed for etching. A pattern was formed. Thereafter, post-baking was performed at 140 ° C. for 1 minute. This resist-patterned substrate was dry etched with an ICP dry etching apparatus using SF 6 as an etching gas at a pressure of 0.5 Pa and an antenna power of 700 W and a bias power of 7 W (that is, a bias / antenna power ratio of 0.01).
このときSiC基板は、裏面からHeガスで冷却している。この条件でドライエッチングすると、SiC基板は約0.175μｍ/minの早さでエッチングされる。その時のレジストのエッチングレートは約0.33μｍ/minである。ラインとスペースが2μｍ/2μｍの間隔でパターニングされた場合のエッチング断面形状を図４に示す。これは収束イオンビーム装置（FIB）で断面を切り出した写真である。表面にPtの保護膜が形成されている。エッチング深さは約1.1μｍである。エッチング側壁の角度は凹部底に近い方は約55°になっており、開口部に近い方は約30°になっている。この実施の形態２の条件でこのように側壁が２段階のテーパー角度がつくようにエッチングされ、実施の形態１と同様に１段目、２段目の角度はかなりテーパーになるようにエッチングできる。 At this time, the SiC substrate is cooled with He gas from the back surface. When dry etching is performed under these conditions, the SiC substrate is etched at a rate of about 0.175 μm / min. At that time, the etching rate of the resist is about 0.33 μm / min. FIG. 4 shows an etching cross-sectional shape when lines and spaces are patterned at intervals of 2 μm / 2 μm. This is a photograph of a cross section cut out by a focused ion beam device (FIB). A protective film of Pt is formed on the surface. The etching depth is about 1.1 μm. The angle of the etching side wall is about 55 ° near the bottom of the recess, and about 30 ° near the opening. Etching is performed so that the side wall has a two-step taper angle in this way under the conditions of the second embodiment, and the first and second step angles can be etched so as to be considerably tapered as in the first embodiment. .
次に、直径50μｍの円形にドライエッチングした場合の断面形状を図５に示す。エッチング深さは同様に約1.1μｍであるが、エッチング側壁の角度は凹部底に近い方は約30°になっており、開口部に近い方は約20°になっている。このようにエッチング幅が広い方がさらにテーパー角度は緩やかになる。実施の形態２の条件でSiCをエッチングすると深さは1.1μｍまで深くすることができ、エッチング側壁の２段テーパー形状は実施の形態１より更に緩やかな角度に形成できる。 Next, FIG. 5 shows a cross-sectional shape when dry etching is performed into a circle having a diameter of 50 μm. The etching depth is similarly about 1.1 μm, but the angle of the etching side wall is about 30 ° near the bottom of the recess and about 20 ° near the opening. Thus, the taper angle becomes gentler when the etching width is wider. When SiC is etched under the conditions of the second embodiment, the depth can be increased to 1.1 μm, and the two-step tapered shape of the etched sidewall can be formed at a more gentle angle than in the first embodiment.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011065917A JP5720042B2 (en) | 2011-03-24 | 2011-03-24 | SiC substrate dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011065917A JP5720042B2 (en) | 2011-03-24 | 2011-03-24 | SiC substrate dry etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2012204472A JP2012204472A (en) | 2012-10-22 |
| JP5720042B2 true JP5720042B2 (en) | 2015-05-20 |
Family
ID=47185162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011065917A Expired - Fee Related JP5720042B2 (en) | 2011-03-24 | 2011-03-24 | SiC substrate dry etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5720042B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112530795A (en) * | 2020-08-21 | 2021-03-19 | 中国工程物理研究院电子工程研究所 | Silicon carbide power device terminal based on small-angle deep etching process and manufacturing method |
| CN114427115A (en) * | 2022-04-01 | 2022-05-03 | 浙江大学杭州国际科创中心 | Silicon carbide single crystal wafer stripping method and stripping device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000114234A (en) * | 1998-09-30 | 2000-04-21 | New Japan Radio Co Ltd | Method for etching silicon carbide substrate |
| JP2004247676A (en) * | 2003-02-17 | 2004-09-02 | Mitsubishi Electric Corp | Apparatus and method of plasma processing, and method of manufacturing semiconductor device |
| JP5531436B2 (en) * | 2008-12-01 | 2014-06-25 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor element |
-
2011
- 2011-03-24 JP JP2011065917A patent/JP5720042B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2012204472A (en) | 2012-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4450245B2 (en) | Manufacturing method of semiconductor device | |
| JP2008288475A (en) | Method of manufacturing silicon carbide semiconductor device | |
| US9076804B2 (en) | Systems and methods to enhance passivation integrity | |
| JP2010040698A (en) | Guard ring structure and formation method thereof, and semiconductor device | |
| US9257280B2 (en) | Mitigation of asymmetrical profile in self aligned patterning etch | |
| JP2016072631A (en) | Method for growing nitride-based semiconductor with high quality | |
| JP2018520977A (en) | Method for making it possible to obtain a nitride semipolar layer obtained on at least one of the following materials: gallium (Ga), indium (In) and aluminum (Al) on a crystalline substrate | |
| JP2010192555A (en) | Schottky barrier diode and method of manufacturing the same | |
| JP5720042B2 (en) | SiC substrate dry etching method | |
| JP2008311406A (en) | MANUFACTURING METHOD OF GROOVE GATE TYPE SiC SEMICONDUCTOR DEVICE | |
| JP5531436B2 (en) | Method for manufacturing silicon carbide semiconductor element | |
| JP2009182059A (en) | Dry etching method | |
| JP5680457B2 (en) | Diode manufacturing method | |
| JP2007184390A (en) | Method of etching semiconductor substrate | |
| JP2010040697A (en) | Semiconductor device and manufacturing method thereof | |
| JP6828595B2 (en) | Manufacturing method of semiconductor devices | |
| JP5687078B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| CN104658902B (en) | Trench gate engraving method | |
| JP2007005658A (en) | Compound semiconductor wafer and its manufacturing method | |
| TWI545658B (en) | Gate structures and method of forming channel thereof | |
| JP4795817B2 (en) | Manufacturing method of semiconductor device | |
| JP5012856B2 (en) | Manufacturing method of semiconductor device | |
| JP6315665B2 (en) | Group III nitride semiconductor layer and group III nitride semiconductor substrate manufacturing method | |
| JP2007088168A (en) | Method for manufacturing semiconductor device | |
| JP5935821B2 (en) | Method for manufacturing silicon carbide semiconductor element and silicon carbide semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20121114 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20121114 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20121114 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131121 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131118 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140829 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140909 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141107 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150210 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150225 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5720042 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R370 | Written measure of declining of transfer procedure |
Free format text: JAPANESE INTERMEDIATE CODE: R370 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |