JP5719737B2 - Current detection circuit and motor control device - Google Patents

Description

  The present invention relates to a current detection circuit that detects a current flowing through a switching element, particularly an FET (field effect transistor), and a motor control device using the current detection circuit.

Some motor control devices convert a DC voltage into a three-phase AC voltage by an inverter, and drive a three-phase AC motor (a three-phase brushless motor or a three-phase induction motor) by this three-phase AC voltage (for example, a patent) Reference 1). FIG. 5 shows the configuration of the motor control device described in Patent Document 1 (FIG. 2 of Patent Document 1) as it is. The motor control device shown in FIG. 5 converts a direct current into an alternating current using an inverter circuit including a three-phase bridge circuit composed of _six transistors Q ₁ ′ to Q ₆ ′ and a control circuit CONT. The output voltage is controlled to control the rotation of the three-phase brushless motor M. In such an inverter circuit, it is necessary to prevent transistor damage due to overcurrent and motor performance deterioration due to overload.

Therefore, a method for shutting off the motor current by collectively turning off (all off) the transistors Q ₁ ′ to Q ₆ ′ when an overcurrent occurs using a circuit that detects that the output current of the inverter is in the overcurrent region. Is used. One of the typical examples of detecting this overcurrent is a current detection resistor (or a shunt current) on the input side of the inverter's three-phase bridge circuit (for example, a DC power line connecting the three-phase bridge circuit and the electrode (+)). There is a method of detecting an overcurrent state by inserting a detector) and comparing the detected voltage with a current setting reference voltage. Further, for example, a Hall sensor incorporating a Hall element is arranged on the input side of the inverter (for example, a DC power line connecting the three-phase bridge circuit and the electrode (+)), and the output voltage of the Hall sensor is set as a current setting reference voltage. There is a method of detecting an overcurrent state by comparing with.

  However, the use of the current detection resistor or the Hall element is contrary to the demand for miniaturization of the motor control device (more precisely, the overcurrent protection circuit), and the use of these components increases the product cost. become. In order to cope with this problem, the motor control device described in Patent Document 1 detects a current flowing through the FET based on an on-voltage (voltage drop) at the conduction timing of the FET (Field Effect Transistor).

That is, in the motor control device described in Patent Document 1 shown in FIG. 5, the three-phase bridge circuit is configured using FETs Q ₁ ′ to Q _6, and the first phase, the second phase, and the third phase of the motor M are configured. Three switches AS ₁ , AS ₂ , and AS ₃ that are turned on in accordance with the conduction timing of each FET are set to the drain-source voltages V _DS4 , V _DS5 , and V _DS6 of the FETs Q ₁ ′ to Q ₆ that are proportional to the motor current. To detect sequentially in series. Then, when the drain-source voltages V _DS4 , V _DS5 , and V _{DS6 of the FETs} Q ₁ ′ to Q ₆ ′ exceed the current setting reference voltage Vs, it is determined as an overcurrent, and the drive information from the control circuit CONT is stopped. Then, all the FETs are turned off so that no overcurrent flows.

FIG. 6 is a view showing the same figure (FIG. 1 of Patent Document 1) described in Patent Document 1 as it is, and is a diagram showing the relationship between the drain-source voltage V _DS and the drain current _ID of the FET. is there. As shown in this figure, when the gate voltage V _G of the FET as a parameter, and the voltage drop V _DS between the drain and source when FET on, the drain current I _D, as shown in FIG., Over a wide range Have a linear proportional relationship. In addition, since the slope is much gentler than that of a normal transistor, a sufficiently large change in drain-source voltage drop proportional to the change in drain current can be obtained. Therefore, a large difference can be provided between the control current region and the overcurrent region, so that effective overcurrent detection is possible.

JP-A-4-308420

  In the motor control device described in Patent Document 1 described above, the drain current and the voltage drop between the drain and the source are reduced for the purpose of downsizing the overcurrent protection circuit for preventing damage due to overcurrent of the motor, the transistor, and the cost. Using a FET that has a linear relationship over a wide range, and turning on in accordance with the timing of movement of this FET, the drain-source voltage drop proportional to each phase current of the motor is sequentially detected in series. When the output of this circuit exceeds the set reference voltage, it is determined that the current is overcurrent, the supply of the drive signal to the control circuit is stopped, and the FET current is cut off.

However, the overcurrent protection circuit based on the detection of the drain-source voltage of the FET described in Patent Document 1 has the following problems. That is, in the configuration that implements the FETQ ₁ '~Q _6' on the printed circuit board, so that the current path flowing to the FETQ ₁ '~Q _6' is formed by the wiring pattern. Therefore, when measuring the drain-source voltage (more precisely, the voltage between the drain and the circuit ground) of the FETs Q4 ′ to Q6 ′ using the (−) terminal of the DC power supply as a reference (circuit ground), The voltage drop (offset) due to the resistance is included.

In this case, a wiring pattern between the (−) terminal of the DC power source and the source of the transistor Q ₄ ′, a wiring pattern between the (−) terminal of the DC power source and the source of the transistor Q ₅ ′, The length (or width and thickness) of the wiring pattern between the (−) terminal and the source of the transistor Q ₆ ′ may be different. Therefore, the drain-circuit ground voltage of FETQ4'~Q 6 _', generated a voltage difference due to the resistance of the wiring pattern are different (the difference between the voltage drop) is, the problem that the determination value of the overcurrent varies is there. Therefore, in consideration of the variation in resistance of the wiring pattern, it is necessary to detect the drain-source voltage of FETQ4'~Q 6 _'.

The present invention has been made in view of such circumstances, and when detecting the current flowing through the FET mounted on the printed wiring board based on the voltage drop V _DG between the drain and the circuit ground when the FET is on. Current detection that can detect the voltage drop between the drain and source of the FET (current flowing through the FET) by canceling the offset generated by the resistance of the wiring pattern that forms the current path of the FET by a simple method An object of the present invention is to provide a circuit and a motor control device including the current detection circuit.

  The present invention has been made to solve the above-described problems, and the current detection circuit according to the present invention has one input / output terminal of a switch element mounted on a printed wiring board having a wiring pattern on the printed wiring board. Is connected to a negative electrode terminal provided on the printed wiring board via the first electrode, and the negative electrode terminal is connected to a negative electrode side of a DC power source for supplying a current to the switch element, and controls the switch element In a circuit connected to the circuit ground of the circuit, a current detection circuit that detects a current flowing through the switch element based on a voltage drop when the switch element is conductive includes the other input / output terminal of the switch element and the circuit A resistor series circuit including a first resistor and a second resistor connected to a ground; and in the resistor series circuit, one of the first resistors is provided. Is connected to the other input / output terminal of the switch element, the other end is connected to one end of the second resistor, the other end of the second resistor is connected to the circuit ground, and the second resistor The ratio of the resistance value to the first resistance (second resistance / first resistance) is the ratio of the resistance value between the on-resistance and the wiring pattern resistance when the switch element is conductive (on-resistance / wiring pattern resistance). And a voltage at a connection point between the first resistor and the second resistor and a voltage with respect to the circuit ground is output as a detection signal of a current flowing through the switch element. To do.

  Further, the current detection circuit of the present invention is configured such that the resistance values of the first resistor and the second resistor are compared with the resistance values of the on-resistance and the wiring pattern resistor of the switch element. It is characterized by being set to a sufficiently large value so as to satisfy the tolerance required for detection.

  The motor control device of the present invention uses a three-phase bridge circuit of a switch element mounted on a printed wiring board and an inverter composed of the control circuit to generate a three-phase AC voltage from a DC voltage input from a DC power source. A motor control device that generates and controls rotation of a three-phase AC motor, wherein a current path of a current flowing from the DC power source to each switch element is formed by a wiring pattern on the printed wiring board, and the lower arm side Each wiring pattern that forms a current path between each switch element and the negative electrode side of the DC power supply has one end connected to one input / output terminal of the corresponding switch element on the lower arm side, and the other end Are connected to a negative electrode terminal provided on the printed circuit board, and the negative electrode terminal is connected to the negative electrode side of the DC power supply and the circuit graph of the control circuit. In the motor control device configured to be connected to a switch, a current detection circuit that detects a current flowing through the switch element based on a voltage drop when the switch element on the lower arm side is conductive is provided on each of the lower arm side. Corresponding to the switch element, each resistor series circuit including a first resistor and a second resistor connected between the other input / output terminal of the switch element and the circuit ground is provided. In the resistor series circuit, one end of the first resistor is connected to the other input / output terminal of the corresponding switch element, the other end is connected to one end of the second resistor, and the other end of the second resistor. Is connected to the circuit ground, and the ratio of the resistance value between the second resistor and the first resistor (second resistor / first resistor) is the on-resistance and wiring when the corresponding switch element is conductive With pattern resistance It is set to coincide with a ratio of resistance values (on resistance / wiring pattern resistance), and is a voltage at a connection point between the first resistor and the second resistor, and a voltage with respect to the circuit ground is applied to the switch element. It outputs as a detection signal of the flowing current.

  In the motor control device of the present invention, the resistance values of the first resistor and the second resistor are compared to the ON resistance of the switch element and the resistance value of the wiring pattern resistor. It is characterized by being set to a sufficiently large value so as to satisfy the tolerance required for detection.

  The motor control device according to the present invention is a switch connected in parallel to each of the second resistors corresponding to the respective switch elements on the lower arm side, and the conduction timing of the corresponding switch elements on the lower arm side And a switch that outputs the current detection signal of the corresponding switch element only when the switch element is conductive.

  The motor control device of the present invention includes an overcurrent detection circuit that outputs an overcurrent detection signal when a current detection signal when the lower arm side switch element is on exceeds a predetermined overcurrent setting reference voltage; And an overcurrent protection unit that turns off all the switch elements of the three-phase bridge circuit when an overcurrent detection signal is output from the overcurrent detection circuit.

The current detection circuit of the present invention includes a resistor series circuit including a first resistor and a second resistor connected between one input / output terminal of the switch element and circuit ground, and the second resistor And the resistance value ratio of the first resistor (second resistance / first resistance) coincides with the resistance value ratio (on resistance / wiring pattern resistance) between the ON resistance of the switch element and the wiring pattern resistance. In addition, the voltage between the connection point of the first resistor and the second resistor and the circuit ground is output as a detection signal of the current flowing through the switch element.
As a result, the wiring pattern that forms the current path of the switch element when the current flowing through the switch element mounted on the printed circuit board is detected based on the voltage drop between the drain terminal and the circuit ground when the switch element is on. The offset generated by the resistor can be canceled by a simple method, and the voltage between one input / output terminal of the switch element and the other input / output terminal (current flowing through the switch element) can be detected.

It is a figure which shows the current detection circuit concerning the 1st Embodiment of this invention. It is a figure which shows the structure of the motor control apparatus concerning the 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the electric current detection circuit in the motor control apparatus shown in FIG. It is a figure which shows the detection timing of the electric current (drain-source voltage _VDS ) which flows into FET. It is a figure which shows the structure of the motor control apparatus of patent document 1. FIG. FIG. 4 is a relationship diagram between a drain-source voltage drop and a drain current of an FET.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a current detection circuit according to the first embodiment of the present invention. In the circuit shown in FIG. 1, an FET Qo that is a current detection target is mounted on a printed wiring board, and a negative terminal B (-) connected to the negative side of a DC power supply (not shown) is also printed on the printed wiring board. Implemented above. The source terminal S of the FET Qo is connected to the negative electrode terminal B (−) on the printed wiring board via a wiring pattern (path indicated by the wiring pattern resistance Rp) serving as a current path flowing through the FET Qo. Connected to ground G. The FET Qo is on / off controlled by a control circuit (not shown) (see, for example, the control unit 20 shown in FIG. 2).

  As shown in FIG. 1, the current detection circuit 1 of the present embodiment is configured by a resistance voltage dividing circuit, and the resistance voltage dividing circuit includes a detection unit resistor R1 (first resistor) and an offset resistor Ro (second resistor). A series circuit of resistors), and a current detection signal is output from a connection point (node N1) between the detection unit resistor R1 and the offset resistor Ro.

The current detection circuit 1 is a circuit whose purpose is to detect a current (drain current I _D ) flowing through the FET Qo based on the drain-source voltage V _DS of the FET Qo. That is, as shown in FIG. 6, FETQo the drain-source voltage _{V DS} (voltage drop), because in a relationship proportional to the drain current _{I D,} the drain-source voltage _{V DS} of the FETQo (voltage drop) Based on the above, the current (drain current _ID ) flowing through the FET Qo is detected.

In the circuit configuration shown in FIG. 1, the drain-source voltage V _DS of the FET Qo is not directly measured, but the voltage V _DG between the drain terminal D of the FET Qo and the circuit ground G is measured. In addition to the drain-source voltage V _DS (voltage drop = on-resistance Ron × drain current I _D ) of the FET Qo, the drain-circuit ground voltage V _DG includes a voltage drop due to the wiring pattern resistance Rp as an offset. It is. Therefore, the drain-circuit ground voltage V _DG is expressed by the following equation (1).

V _DG = Ron × _ID + Rp × _ID (1)

Since this wiring pattern resistance (Rp) varies depending on the length, width, and thickness of the wiring pattern, the offset (Rp × I _D ) varies. For this reason, it is necessary to cancel the offset (Rp × I _D ) of the voltage drop generated by the wiring pattern resistance Rp and extract the drain-source voltage V _DS (= on resistance Ron × I _D ) of the FET Qo.

  Therefore, in the current detection circuit of the present embodiment, a resistance voltage dividing circuit (a resistance series circuit including a detection unit resistance Rd and an offset resistance Ro) is inserted between the drain terminal D of the FET Qo and the circuit ground G. Then, the voltage drop due to the wiring pattern resistance (Rp), which is the resistance component of the wiring pattern, is divided by the offset resistor Ro constituting the resistance voltage dividing circuit to cancel the offset.

  For this purpose, the relationship between the on-resistance Ron of the FET Qo, the wiring pattern resistance Rp, the offset resistance Ro, and the detection unit resistance Rd is determined as follows.

Ron: Rp = Ro: Rd (2)
That is, the resistance voltage dividing circuit side (resistance Rd and resistance) is compared with the ratio of the upper and lower resistance values (Ron / Rp) on the side where the drain current _ID flows and the voltage drop is generated (resistance Ron and wiring pattern resistance Rp side). The ratio of the upper and lower resistance values (Rd / Ro) on the Ro side is set to an inverse ratio. That is, the following relationship is established.

  Ron / Rp = Ro / Rd

  Next, a specific numerical example will be described. FIG. 1B is a diagram for explaining a specific example of canceling the voltage drop (offset) generated by the wiring pattern resistance Rp. As shown in this figure, the motor current is 100 A, the on-resistance Ron of the FET Qo is 4 mΩ (Ron = 4 mΩ), the wiring pattern resistance Rp is 1 mΩ (Rp = 1 mΩ), and the detection unit resistance (first resistance) Rd Is 10 kΩ (R1d = 10 kΩ), and the offset resistance (second resistance) Ro is 40 kΩ (Ro = 40 kΩ).

In this case, the drain-circuit ground voltage V _DG is 0.50 V (= 100 A × 5 mΩ). That is, the voltage drop due to the on-resistance Ron of the FET Qo becomes “0.40 V (= 100 A × 4 mΩ)”, the voltage drop due to the wiring pattern resistance Rp becomes “0.10 V (= 100 A × 1 mΩ)”, and between the drain and the circuit ground The voltage V _DG is 0.50V.
On the other hand, the voltage VRo (the voltage across the resistor Ro) of the detection voltage (node N1) of the resistance voltage divider circuit is divided by the drain-circuit ground voltage V _DG (= 0.50V). It becomes like this.

  VRo = 0.50V × 40kΩ / (10kΩ + 40kΩ) = 0.40V

Accordingly, the voltage VRo (the voltage across the resistor Ro) of the detection voltage (node N1) of the resistance voltage dividing circuit is equal to the drain-source voltage V _{DS of the} FET Qo “0.40 V (= 100 A × 4 mΩ)”.

Thus, the ratio of the upper and lower resistance values (Rd / Ro) on the resistance voltage dividing circuit side is opposite to the ratio of the upper and lower resistance values (Ron / Rp) on the side where the drain current ID flows and causes a voltage drop. It sets so that it may become a ratio (Ron / Rp = Ro / Rd). That is, the resistance value ratio (Ro / Rd) between the offset resistance Ro and the detection unit resistance Rd is set to match the resistance value ratio (Ron / Rp) between the on-resistance Ron of the FET Qo and the wiring pattern resistance Rp. To do. Thus, by canceling the voltage drop caused by the wiring pattern resistance Rp (offset), it is possible to detect the drain-source voltage V _DS of FETQo.

  Note that the offset resistance Ro and the detector resistance Rd are set to sufficiently large values with respect to the ON resistance Ron of the FET Qo and the wiring pattern resistance Rp. This is because when the values of the offset resistor Ro and the detection unit resistor Rd are small, the current flowing through the offset resistor Ro and the detection unit resistor Rd (current shunted from the FET Qo side) increases, and the current flowing through the FET Qo is detected. This is because the error increases.

[Second Embodiment]
Next, as a second embodiment of the present invention, an example in which the above-described current detection circuit of the first embodiment is used in a motor control device that controls the rotation of a three-phase AC motor using an inverter will be described.

(Description of the configuration of the motor control device)
FIG. 2 is a diagram showing the configuration of the motor control device according to the embodiment of the present invention. The motor control device 10 shown in FIG. 2 uses, for example, a battery (not shown) as a DC power source, converts the DC voltage of the battery into an AC voltage, and converts it into a three-phase AC motor (a three-phase brushless motor or a three-phase induction motor). 10 is a control device that drives 10.

  In FIG. 2, a three-phase AC motor (also simply referred to as “motor”) 10 is a motor that becomes a starter motor of an engine (internal combustion engine), for example. When the three-phase AC motor 10 is, for example, a three-phase brushless motor, the motor 10 includes a stator having U, V, and W phase coils (coils wound around an iron core) and a permanent magnet. A three-phase (U, V, W) coil is wound around the stator in order in the circumferential direction.

  In the motor control device 11, a three-phase bridge circuit 12 composed of FETs Q1 to Q6 which are Nch type MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) is provided. The three-phase bridge circuit 12 is configured by mounting FETs Q1 to Q6 on a printed wiring board. In the three-phase bridge circuit 12, the drain terminals of the FETs Q1, Q2, and Q3 on the upper arm side are It is commonly connected to the positive electrode terminal A (+) provided on the printed wiring board via each wiring pattern that becomes a current path of the current flowing through the FETs Q1, Q2, and Q3. The positive electrode terminal A (+) is connected to a positive electrode of a DC power source (for example, a battery) (not shown).

  The source terminals of the lower arm side FETs Q4, Q5, and Q6 have respective wiring patterns (paths indicated by wiring pattern resistors Rp1, Rp2, and Rp3) that serve as current paths for the currents flowing through the FETs Q4, Q5, and Q6. To the negative electrode terminal B (-) provided on the printed wiring board. The negative electrode terminal B (−) on the printed wiring board is connected to a negative electrode of a DC power source (not shown) (not shown), and the negative electrode terminal B (−) is a current described later. The circuit is connected to a circuit ground G serving as a reference potential (ground) of a circuit constituting the detection circuit 14, the overcurrent detection circuit 15, the control unit 20, and the like.

  In the three-phase bridge circuit 12, the resistor Rp1 inserted between the source terminal of the FET Q4 and the negative electrode terminal B (−) is a printed wiring board that connects the source terminal of the FET Q4 and the negative electrode terminal B (−). The resistance component (wiring pattern resistance Rp1) of the upper wiring pattern is shown. The resistor Rp2 inserted between the source of the FET Q5 and the negative electrode terminal B (−) is a resistance component (which is included in the wiring pattern on the printed circuit board connecting the source of the FET Q5 and the negative electrode terminal B (−) ( Wiring pattern resistance Rp2) is shown. The resistor Rp3 inserted between the source of the FET Q6 and the negative electrode terminal B (−) is a resistance component (which is included in the wiring pattern on the printed circuit board connecting the source of the FET Q6 and the negative electrode terminal B (−) ( Wiring pattern resistance Rp3) is shown.

  The resistance values of the wiring pattern resistors Rp1, Rp2, and Rp3 vary depending on the arrangement state of the FETs Q1 to Q6 mounted on the printed wiring board. That is, the resistance values of the wiring pattern resistors Rp1, Rp2, and Rp3 vary depending on the length (wiring length), width, and thickness of the wiring pattern. In the example shown in FIG. 2, for example, Rp1 <Rp2 <Rp3. That is, the wiring pattern connecting the source terminal of the FET Q4 and the negative electrode terminal B (-) is the shortest, the wiring pattern connecting the source terminal of the FET Q5 and the negative electrode terminal B (-) is next long, and the source terminal of the FET Q6 It is assumed that the wiring pattern connecting the negative electrode terminal B (−) is the longest.

  The source terminal of the FET Q1 on the upper arm side and the drain terminal of the FET Q4 on the lower arm side are connected, and the connection point between the FETs Q1 and Q4 is connected to the U-phase coil terminal of the three-phase AC motor 10 via the output wiring Lu. It is connected to the. The source terminal of the FET Q2 on the upper arm side and the drain terminal of the FET Q5 on the lower arm side are connected, and the connection point between the FETs Q2 and Q5 is the V-phase coil terminal of the three-phase AC motor 10 via the output wiring Lv. It is connected to the.

  The source terminal of the FET Q3 on the upper arm side and the drain terminal of the FET Q6 on the lower arm side are connected, and the connection point between the FETs Q3 and Q6 is connected to the W-phase coil terminal of the three-phase AC motor 10 via the output wiring Lw. It is connected to the. Each of the FETs Q1 to Q6 has a flywheel diode Dx connected in parallel so that the cathode is in the (+) electrode direction and the anode is in the (-) electrode direction as shown in the figure.

  Further, the motor control device 11 generates a gate signal for generating a gate signal for driving on / off of the switching elements (FETs) Q1, Q2, Q3 on the upper arm side and the switching elements (FETs) Q4, Q5, Q6 on the lower arm side. A circuit (driver circuit) 13 is included. The FETs Q1 to Q6 are driven by the gate drive signal output from the gate drive circuit 13, and the gate drive signal is based on the FET drive signal output from the control unit (control unit configured by a CPU or the like) 20. Is generated.

  The control unit 20 includes an FET drive signal generation unit 21, an energization control unit 22, a synchronization signal generation unit 23, and an overcurrent protection unit (overcurrent protection circuit) 24. The energization control unit 22 is a processing unit for generating an energization signal for driving the three-phase AC motor 10. In the energization control unit 22, for example, when the three-phase AC motor 10 rotates at a low speed, the three-phase AC motor 10 is drive-controlled so that the coil is energized only for a period of 120 degrees during the entire energization period of 180 degrees. To do. In addition, for example, when the three-phase AC motor 10 rotates at high speed, the three-phase AC motor 10 is driven and controlled by 180 ° energization.

  The FET drive signal generation unit 21 generates an FET drive signal based on the energization signal generated by the energization control unit 22, and outputs the FET drive signal to the gate drive circuit 13. The gate drive circuit 13 is a driver circuit for generating a gate drive signal for the FET. The gate drive signal output from the gate drive circuit 13 drives the FETs Q1 to Q6 on / off.

  Further, the synchronization signal generator 23 generates a synchronization signal for driving on / off switches SW1, SW2, and SW3 described later. Further, when an overcurrent detection signal is input from comparators CP1, CP2, CP3, and comparator CP4, which will be described later, the overcurrent protection unit 24 controls the gate drive circuit 13 via the FET drive signal generation unit 21. The gate drive circuit 13 outputs a gate drive signal for turning off the FETs Q1 to Q6 at once.

(Description of the current detection circuit 14)
In the above configuration, the motor control device 11 of the present embodiment detects the drain-source voltage (more precisely, the drain-circuit ground voltage) of the FETs Q4, Q5, and Q6, thereby flowing to the FETs Q4, Q5, and Q6. Detect current. For this reason, the motor control device 11 includes a current detection circuit 14. In addition, an overcurrent detection circuit 15 that compares the current signal detected by the current detection circuit 14 with a predetermined current setting reference voltage is provided.

  In the current detection circuit 14, a resistor series circuit (resistance voltage dividing circuit) including a detection unit resistor R 1 and an offset resistor Ro 1 is inserted between the drain terminal of the FET Q 6 and the circuit ground G. That is, one end of the resistor R1 is connected to the drain of the FET Q6, the other end of the resistor R1 is connected to one end of the resistor Ro1, and the other end of the resistor Ro1 is connected to the circuit ground G. Further, the switch SW1 is connected between the connection point (node N1) of the resistor R1 and the resistor Ro1 and the ground G.

  Further, a resistor series circuit (resistor voltage dividing circuit) composed of the detector resistor R2 and the offset resistor Ro2 is inserted between the drain terminal of the FET Q5 and the ground G. That is, one end of the resistor R2 is connected to the drain terminal of the FET Q5, the other end of the resistor R2 is connected to one end of the resistor Ro2, and the other end of the resistor Ro2 is connected to the ground G. Further, the switch SW2 is connected between the connection point (node N2) of the resistor R2 and the resistor Ro2 and the ground G.

  Similarly, a resistor series circuit (resistor voltage dividing circuit) composed of the detector resistor R3 and the offset resistor Ro3 is inserted between the drain terminal of the FET Q4 and the circuit ground G. That is, one end of the resistor R3 is connected to the drain terminal of the FET Q4, the other end of the resistor R3 is connected to one end of the resistor Ro3, and the other end of the resistor Ro3 is connected to the circuit ground G. Further, the switch SW3 is connected between the connection point (node N3) of the resistor R3 and the resistor Ro3 and the circuit ground G.

  In the above configuration, the switch SW1 is turned on when the FET Q6 is turned off, and turned off at the timing when the FET Q6 is turned on. That is, the switch SW1 is turned off while the FET Q6 is turned on and the W-phase current Iw of the motor 10 flows to the FET Q6. As a result, the voltage generated at the drain of the FET Q6 (voltage proportional to the W-phase current) is divided by the resistors R1 and Ro1 at the timing when the FET Q6 is turned on, and input to one terminal of the comparator CP1 as the voltage of the node N1. can do.

  The switch SW2 is turned on when the FET Q5 is turned off, and turned off at the timing when the FET Q5 is turned on. That is, the switch SW2 is turned off while the FET Q5 is turned on and the V-phase current Iv of the motor 10 flows to the FET Q5. As a result, the voltage generated at the drain of the FET Q5 (voltage proportional to the V-phase current Iv) is divided by the resistors R2 and Ro2 at the timing when the FET Q5 is turned on, and is divided into one terminal of the comparator CP2 as the voltage of the node N2. Can be entered.

  Similarly, the switch SW3 is turned on when the FET Q4 is turned off, and turned off at the timing when the FET Q4 is turned on. That is, in the state where the FET Q4 is turned on and the U-phase current Iu of the motor 10 flows through the FET Q4, the switch SW3 is turned off. As a result, the voltage generated at the drain of the FET Q4 (voltage proportional to the U-phase current Iu) is divided by the resistors R3 and Ro3 at the timing when the FET Q4 is turned on, and the voltage of the node N3 is applied to one terminal of the comparator CP3. Can be entered.

(Explanation about offset generated by wiring pattern resistance)
By the way, the FETs Q4, Q5, and Q6 are FET elements having the same specifications (specifications with the same rated current, breakdown voltage, structure, etc.), and the on-resistance Ron can be regarded as the same value (for example, 4 mΩ). The drain-source voltage V _DS is proportional to the flowing drain current _{ID as shown} in FIG. For this reason, in order to detect the current flowing through the FETs Q4, Q5, and Q6, it is only necessary to detect the respective drain-source voltages _VDS .

However, as described above, the wiring pattern resistances (Rp1, Rp2, Rp3) are interposed between the source terminals of the FETs Q4, Q5, Q6 and the negative electrode terminal B (−). Therefore, when measuring the voltage V _DG between the drain terminals of the FETs Q4, Q5, and Q6 and the circuit ground G in order to measure the current flowing through the FETs Q4, Q5, and Q6, the wiring pattern resistors (Rp1, Rp2) are measured. , Rp3) is included in the offset.

For example, when the motor current Iw flows while the FET Q6 is on, the voltage V _DG 6 generated between the drain terminal of the FET Q6 and the circuit ground G is as follows.

V _DG 6 = Iw × Ron + Iw × Rp3

When the motor current Iv flows when the FET Q5 is on, the voltage V _DG 5 generated between the drain terminal of the FET Q5 and the circuit ground G is as follows.

V _DG 5 = Iv × Ron + Iv × Rp2

When the motor current Iu flows when the FET Q4 is on, the voltage V _DG 4 generated between the drain terminal of the FET Q4 and the circuit ground G is expressed by the following equation.

V _DG 4 = Iu × Ron + Iu × Rp1

Thus, FET Q4, Q5, Q6 drain-circuit ground voltage of the drain-source voltage _{V DS,} the wiring pattern resistance (Rp1, Rp2, Rp3) voltage drop due will be added as offset. Therefore, in order to obtain the drain-source voltages of the FETs Q4, Q5, Q6, it is necessary to cancel the offset.

  Therefore, in the current detection circuit 14 of the present embodiment, as described in the first embodiment, the voltage drop due to the resistance (Rp1, Rp2, Rp3) of the wiring pattern is used as an offset resistance ( Offset by dividing by Ro1, Ro2, Ro3).

  For this purpose, the on-resistance Ron of the FETs Q4, Q5, and Q6, the wiring pattern resistors (Rp1, Rp2, and Rp3), the offset resistors (Ro1, Ro2, and Ro3), and the detection unit resistors (R1, R2, and R3) The relationship is defined as follows.

  That is, for the FET Q6, the on-resistance Ron of the FET Q6, the wiring pattern resistance Rp3, the detection unit resistance R1 corresponding to the FET Q6, and the offset resistance Ro1

On-resistance Ron of FET Q6: wiring pattern resistance (Rp3)
= Offset resistance (Ro1): detection section resistance (R1)

  Set to be.

  Further, regarding the FET Q5, in the ON resistance Ron of the FET Q5, the wiring pattern resistance Rp2, the detection unit resistance R2 corresponding to the FET Q5, and the offset resistance Ro2,

On-resistance Ron of FET Q5: wiring pattern resistance (Rp2)
= Offset resistance (Ro2): detection section resistance (R2)

  Set to be.

  Further, regarding the FET Q4, in the on-resistance Ron of the FET Q4, the wiring pattern resistance Rp1, the detection unit resistance R3 corresponding to the FET Q4, and the offset resistance Ro3,

On-resistance Ron of FET Q4: wiring pattern resistance (Rp1)
= Offset resistance (Ro3): detection section resistance (R3)

  Set to be.

  However, in the above setting, “ON resistance Ron, pattern resistance (Rp1, Rp2, Rp3) << offset resistance (Ro1, Ro2, R03), detection unit resistance (R1, R2, R3)” is set. That is, the resistance values of the offset resistors (Ro1, Ro2, R03) and the detection unit resistors (R1, R2, R3) are sufficiently larger than the resistance values of the on-resistance Ron and the pattern resistors (Rp1, Rp2, Rp3). Set as follows.

  Next, a specific example will be described. FIG. 3 is a diagram for explaining a specific example of canceling the voltage drop (offset) generated by the wiring pattern resistor Rp3. As shown in FIG. 3, the motor current (W-phase current Iw) is 100 A, the on-resistance Ron of the FETs Q4, Q5, and Q6 is 4 mΩ (Ron = 4 mΩ), and the wiring pattern resistance Rp3 of the FET Q6 is 1 mΩ (Rp3 = 1 mΩ). ) And the detection unit resistance R1 is 10 kΩ (R1 = 10 kΩ).

When the offset resistor Ro1 is not provided (Ro1 = ∞), the detection voltage (the voltage at the node N1) is 0.50 V “= 100 A × 5 mΩ”, and the original drain-source voltage V _DS “0.40 V”. (= 100 A × 4 mΩ) ”, the detection error is + 25%.

On the other hand, when the offset resistance Ro1 is 40 kΩ (Ro1 = 40 kΩ), the detection voltage (the voltage at the node N1) is 0.50 V × 40 kΩ / 50 kΩ = 0.40 V, and the original drain-source voltage V _DS “ For “0.400 V (= 100 A × 4 mΩ)”, the detection error is almost 0%.

In this way, the ratio of the resistance values of the upper and lower resistors on the resistance voltage dividing circuit side to the ratio of the resistance values of the upper and lower resistors on the side where the drain current _ID flows and causes a voltage drop (for example, Ron / Rp3). (For example, R1 / Ro1) is set to have an inverse ratio (Ron / Rp3 = Ro1 / R1). That is, the ratio (Ro1 / R1) of the resistance value between the offset resistor Ro1 and the detection unit resistor R1 is set to match the ratio (Ron / Rp3) of the on-resistance Ron of the FET Q6 and the wiring pattern resistance Rp3. To do. Thus, for example, by canceling the voltage drop caused by the wiring pattern resistor Rp3 (offset), it is possible to detect the drain-source voltage V _DS of the FET Q6.

(Description of the configuration of the overcurrent detection circuit 15 and the overcurrent detection operation)
Next, the configuration and operation of the overcurrent detection circuit 15 will be described. As described above, the node N1 of the current detection circuit 14 is connected to one input terminal (−) of the comparator CP1, and the other input terminal (+) of the comparator CP1 has a reference current setting reference voltage. VR1 is input. For this reason, when the current signal of the FET Q6 (the voltage at the node N1) is lower than the current setting reference voltage VR1 (when it is not in the overcurrent state), the output of the comparator CP1 is in the H state, for example, and the current signal of the FET Q6 (the node When the voltage N1 is higher than the current setting reference voltage VR1 (in the case of an overcurrent state), for example, the L state is set.

  The node N2 of the current detection circuit 14 is connected to one input terminal (−) of the comparator CP2, and the reference current setting reference voltage VR2 is input to the other input terminal (+) of the comparator CP2. . For this reason, when the current signal of FET Q5 (the voltage at node N2) is lower than the current setting reference voltage VR2 (when it is not in an overcurrent state), the output of comparator CP2 is in the H state, for example, and the current signal of FET Q6 (node) When the voltage N2) is higher than the current setting reference voltage VR2 (in the case of an overcurrent state), for example, the L state is set.

  Similarly, the node N3 is connected to one input terminal (−) of the comparator CP3, and the current setting reference voltage VR3 serving as a reference is input to the other input terminal (+) of the comparator CP3. For this reason, when the current signal of the FET Q4 (voltage of the node N3) is lower than the current setting reference voltage VR3 (when it is not in an overcurrent state), the output of the comparator CP3 is in the H state, for example, and the current signal of the FET Q4 (node) When the voltage N3 is higher than the current setting reference voltage VR3 (in the case of an overcurrent state), for example, the L state is set.

  The node N1 of the current detection circuit 14 is connected to one input terminal (+) of the amplifier (amplifier) AM11, and the output terminal of the amplifier AM11 is connected to the other input terminal (−) of the amplifier AM11. . Thus, the amplifier AM11 constitutes a voltage follower circuit. This voltage follower circuit functions as a buffer circuit having a high input impedance and a low output impedance, and buffers the voltage signal input from the node N1 and outputs it as it is to the output terminal.

  The node N2 of the current detection circuit 14 is connected to one input terminal (+) of the amplifier (amplifier) AM12, and the output terminal of the amplifier AM12 is connected to the other input terminal (−) of the amplifier AM12. . As a result, the amplifier AM12 constitutes a voltage follower circuit. This voltage follower circuit functions as a buffer circuit having a high input impedance and a low output impedance, and buffers the voltage signal input from the node N2 and directly outputs it to the output terminal.

  Similarly, the node N3 of the current detection circuit 14 is connected to one input terminal (+) of the amplifier (amplifier) AM13, and the output terminal of the amplifier AM13 is connected to the other input terminal (−) of the amplifier AM13. Is done. Thus, the amplifier AM13 constitutes a voltage follower circuit. This voltage follower circuit functions as a buffer circuit having a high input impedance and a low output impedance, and buffers the voltage signal input from the node N3 and outputs it as it is to the output terminal.

The output terminal of the amplifier AM11 is connected to the node N4 via the resistor R11, the output terminal of the amplifier AM12 is connected to the node N4 via the resistor R12, and the output terminal of the amplifier AM13 is connected to the node N4 via the resistor R13. Connected. As a result, the output signals of the amplifier AM11, the amplifier AM12, and the amplifier AM13 are wired-ORed at the node N4. Therefore, the signal with the highest signal level (the signal with the highest voltage level) among the output signal of the amplifier AM11, the output signal of the amplifier AM12, and the output signal of the amplifier AM13 is selected and appears at the node N4.

  The node N4 is connected to one input terminal (−) of the comparator CP4, and the current setting reference voltage VR4 serving as a reference is input to the other input terminal (+) of the comparator CP4. For this reason, when the voltage of the node N4 is lower than the current setting reference voltage VR4 (when not in an overcurrent state), the output of the comparator CP4 is in the H state, for example. Further, when the voltage of the node N4 becomes higher than the current setting reference voltage VR4 (in the case of an overcurrent state), the output of the comparator CP4 is in the L state, for example.

  Therefore, in the circuit system constituted by the amplifiers AM11, AM12, AM13 and the comparator CP4, when any one of the node N1, the node N2, and the node N3 becomes higher than the current setting reference voltage VR4 (FETs Q4, Q5, Q6). When any of the above becomes an overcurrent state), the output of the comparator CP4 becomes, for example, an L state.

  As described above, the comparators CP1, CP2, and CP3 are configured such that the comparator CP1 detects the overcurrent state of the FETQ6, the comparator CP2 detects the overcurrent state of the FETQ5, the comparator CP3 detects the overcurrent state of the FETQ4, etc. The overcurrent state of the FETs Q4, Q5 and Q6 is detected. On the other hand, in the circuit system composed of the amplifiers AM11, AM12, AM13 and the comparator CP4, the overcurrent states of the FETs Q4, Q5, Q6 are collectively detected. In other words, the circuit system composed of the amplifiers AMAM11, AM12, AM13 and the comparator CP4 functions as a spare overcurrent detection system that complements the overcurrent detection system using the comparators CP1, CP2, CP3. Is.

  The output terminals of the comparators CP1, CP2, CP3, and CP4 are commonly connected to the signal line OCL to form a yard OR circuit. For this reason, when the output of any of the comparators CP1, CP2, CP3, and CP4 is in the L state, for example, the signal line OCL is in the L state, and this L state signal is output to the control unit 20 as an overcurrent detection signal. Is done. The overcurrent protection unit (overcurrent protection circuit) 24 in the control unit 20 receives an overcurrent detection signal (L-state signal) from the comparators CP1, CP2, CP3, and the comparator CP4, and thereby generates an FET drive signal generation unit. The gate drive circuit 13 is controlled via 21 and a gate drive signal for turning off the FETs Q1 to Q6 at a time is output from the gate drive circuit 13. As a result, when an overcurrent flows through any of the lower arm side FETs Q4, Q5, and Q6, the FETs Q1 to Q6 can be turned off collectively to protect the FETs Q1 to Q6.

FIG. 4 is a diagram showing the detection timing of the current (drain-source voltage V _DS ) flowing through the FET. In FIG. 4, represents the elapsed time t in the transverse direction, the vertical direction, and the drain-source voltage V _DS of Qn, shown side by side and turned on / off SWn switch, the input voltage of the comparator CPn, the Is.
In FIG. 4, time t1 indicates the time when the FET Qn starts to turn on, and a period ΔT1 from time t1 to time t2 is a dead zone (a period in which current detection is not performed) provided according to the turn-on time of the FET Qn. The time t3 indicates the time when the FET Qn starts to turn off, and the time t4 indicates the time when the FET Qn completes the turn-off. Further, the period ΔT2 from the time t3 to the time t4 is also a dead band period in which current detection is not performed, similar to the above-described ΔT1.

  As shown in FIG. 4, when the FET Qn (eg, FET Q6) before time t1 is in an off state (OFF), the switch SWn (eg, switch SW1) is turned on. Thereby, before the time t1, the current detection signal (for example, the voltage of the node N1) of the FET Qn is not input to the comparator Cpn (for example, the comparator Cp1). That is, by making the input voltage of the comparator Cpn equal to or less than a threshold value (overcurrent setting reference voltage), the comparator Cpn does not detect overcurrent.

At time t1, the lower arm side FET Qn (for example, W-phase FET Q6) starts to turn on. The switch SWn (for example, switch SW1) remains on until the time t2 after the FET Qn starts to turn on at the time t1, and the switch SWn is turned off at the time t2.
In this way, when the switch SWn is turned off, the switch SWn is turned off at time t2, which is delayed by ΔT1 from time t1. By providing the dead zone period ΔT1 in this way, after the FET Qn is turned on, the current that flows in the FET Qn rises from 0 to a steady current value (for example, a spire like that generated in the transient state). Avoiding false detection of peak current, etc.) as overcurrent.

  At time t2, the switch SWn is turned off, whereby the current detection signal of the FET Qn (for example, the voltage at the node N1) is input to the comparator Cpn (for example, the comparator CP1), and the current flowing through the FET Qn is detected ( Overcurrent detection) becomes possible. Thereby, when the current flowing through the FET Qn becomes stable, the comparator Cpn can detect the current (overcurrent) flowing through the FET Qn.

Then, at the time t3 (time t3 before the turn-off time t4 by the period ΔT2), which is the timing at which the FET Qn starts to turn off (or the timing just before starting the turn-off) after starting the current detection at the time t2. The switch SWn is turned on. When the switch SWn is turned on, the current detection signal of the FET Qn is not input to the comparator Cpn after the time t3. That is, the input voltage of the comparator Cpn is set to a threshold value (overcurrent setting reference voltage) or less so that the comparator Cpn does not detect overcurrent.
By providing the period ΔT2 in this way, after the FET Qn starts to turn off, the current flowing in the FET Qn in a transitional state from the steady current to zero (for example, a spire like that generated in the transient state) Avoiding false detection of peak current, etc.) as overcurrent.

  As shown in the timing chart of FIG. 4, when the current flowing through the FET Qn is stabilized by detecting the current by providing dead zones (ΔT1 and ΔT2) during the ON period of the FET Qn (time t1 to t4), The current (overcurrent) flowing through the FET Qn can be detected.

Although the embodiment of the present invention has been described above, the correspondence between the present invention and the above embodiment will be supplementarily described.
That is, in the above embodiment, the current detection circuit in the present invention corresponds to the current detection circuit 1 shown in FIG. 1 and the current detection circuit 14 shown in FIG. 2, and the motor control device in the present invention corresponds to the motor shown in FIG. The control device 11 corresponds. The control circuit in the present invention corresponds to the control unit 20, the current detection circuit 14, the overcurrent detection circuit 15 and the like shown in FIG. Also, the three-phase bridge circuit in the present invention corresponds to the three-phase bridge circuit 12, and the switch element in the present invention corresponds to the FET (Qo) shown in FIG. 1 and the FETs (Q1 to Q6) shown in FIG. Further, the on-resistance Ron corresponds to the on-resistance of the switch element in the present invention, and the wiring pattern resistance in the present invention is the wiring pattern resistance Rp shown in FIG. 1 and the wiring pattern resistance (Rp1, Rp2, Rp3) shown in FIG. The first resistor in the present invention corresponds to the detector resistor Rd shown in FIG. 1 and the detector resistors (R1, R2, R3) shown in FIG. The second resistor in the present invention corresponds to the offset resistor Ro shown in FIG. 1 and the offset resistors (Ro1, Ro2, Ro3) shown in FIG.

  The overcurrent detection circuit in the present invention corresponds to the overcurrent detection circuit 15, and the overcurrent protection unit in the present invention corresponds to the overcurrent protection unit 24 in the control unit 20. Further, the switches SW1, SW2 and SW3 correspond to the switches in the present invention. Further, one input / output terminal of the switch element in the present invention corresponds to the source terminal of the FET (Qo) shown in FIG. 1 or the source terminal of the FETs (Q4, Q5, Q6) shown in FIG. Further, the other input / output terminal of the switch element in the present invention corresponds to the drain terminal of the FET (Qo) shown in FIG. 1 or the drain terminal of the FET (Q4, Q5, Q6) shown in FIG.

  (1) In the above embodiment, as shown in FIG. 1, the current detection circuit 1 is configured such that the source terminal S of the FET (Qo) mounted on the printed wiring board has a wiring pattern on the printed wiring board. And connected to the negative electrode terminal B (-) provided on the printed wiring board, and the negative electrode terminal B (-) is connected to the negative electrode side of the DC power supply for supplying current to the FET (Qo). In the circuit connected to the circuit ground G of the control circuit for controlling the FET (Qo), the current detection circuit for detecting the current flowing through the FET (Qo) based on the voltage drop when the FET (Qo) is conducted is , A resistor series circuit including a first resistor Rd and a second resistor Ro connected between the drain terminal D of the FET (Qo) and the circuit ground G. In the resistor series circuit, Resistance One end of Rd is connected to the drain terminal D of the FET (Qo), the other end is connected to one end of the second resistor Ro, the other end of the second resistor Ro is connected to the circuit ground G, and the second resistor The ratio of the resistance value between Ro and the first resistance Rd (second resistance / first resistance) is the ratio of the resistance value between the on-resistance Ron and the wiring pattern resistance Rp when the FET is conducting (on-resistance / wiring). The voltage of the connection point (node N1) between the first resistor Rd and the second resistor Ro and the voltage VRo with respect to the circuit ground G flowing through the FET (Qo) Output as a detection signal.

  In the current detection circuit having such a configuration 1, as shown in FIG. 1, the first resistor Rd and the second resistor Ro connected between the drain terminal D of the FET (Qo) and the circuit ground G are used. A resistor series circuit is provided. Then, the ratio (Ro / Rd) of the resistance value of the second resistor Ro and the first resistor Rd matches the ratio (Ron / Rp) of the on-resistance Ron of the FET (Qo) and the resistance value of the wiring pattern resistor Rp. Set to do. The voltage VRo between the connection point (node N1) between the first resistor Rd and the second resistor Ro and the circuit ground G is output as a detection signal of the current flowing through the FET (Qo).

Thereby, when the current flowing through the FET (Qo) mounted on the printed circuit board is detected based on the voltage drop V _DG between the drain terminal D and the circuit ground G when the FET (Qo) is on. , it is possible to easily cancel the offset generated by the wiring pattern resistance Rp of the wiring pattern forming a current path of FET (Qo), detecting the drain-source voltage V _DS of the FET (Qo). For this reason, the influence of the wiring pattern resistance Rp can be canceled and the current flowing through the FET (Qo) can be detected.

(2) In the embodiment described above, the current detection circuit 1 has the resistance values of the first resistor Rd and the second resistor Ro as compared with the resistance values of the on-resistance Ron of the FET (Qo) and the wiring pattern resistor Rp. Is set to a sufficiently large value so as to satisfy the tolerance required for detecting the current flowing through the FET (Qo).
As a result, the current flowing through the facet resistor Ro and the detection unit resistor Rd can be reduced, and the detection error of the current flowing through the FET (Qo) can be reduced.

  (3) Moreover, in the said embodiment, as shown in FIG. 2, the motor control apparatus 11 is a direct current power supply using the inverter which consists of the three-phase bridge circuit of FET mounted on a printed wiring board, and its control circuit. Is a motor control device 11 for controlling the rotation of a three-phase AC motor by generating a three-phase AC voltage from a DC voltage input from the DC voltage, and the current path of the current flowing from the DC power source to each FET Q1 to Q6 is on the printed wiring board Each of the wiring patterns that form a current path between each of the FETs Q4, Q5, Q6 on the lower arm side and the negative electrode side of the DC power supply is formed at one end of the corresponding FET Q4 on the lower arm side. Connected to the source terminals S of Q5 and Q6, the other end is connected to a negative electrode terminal B (-) provided on the printed wiring board, and the negative electrode terminal B (-) In the motor control device configured to be connected to the negative electrode side and connected to the circuit ground G of the control circuit, the current flowing through the FET based on the voltage drop when the lower arm FETs Q4, Q5, Q6 are conductive The current detection circuit 14 for detecting the first resistor (R1) connected between the drain terminals D of the FETs Q4, Q5, Q6 and the circuit ground G corresponding to the FETs Q4, Q5, Q6 on the lower arm side. , R2, R3) and a second resistor (Ro1, Ro2, Ro3), each of which is provided with one end of the first resistor (R1, R2, R3). Is connected to the drain terminal of the corresponding FET, the other end is connected to one end of the second resistor (Ro1, Ro2, Ro3), and the other end of the second resistor (Ro1, Ro2, Ro3) is turned. A resistance value ratio (second resistance / first resistance) between the second resistance (Ro1, Ro2, Ro3) and the first resistance (R1, R2, R3) is connected to the ground G. The first resistance (R1, Ron) is set to coincide with the ratio of the resistance values (ON resistance / wiring pattern resistance) between the ON resistance (Ron) and the wiring pattern resistance (Rp1, Rp2, Rp3) when the FET is conducted. R2, R3) and the voltage at the connection point of the second resistor (Ro1, Ro2, Ro3) and the voltage with respect to the circuit ground G is output as a detection signal of the current flowing through each FET (Q4, Q5, Q6).

  In the motor control device 11 having such a configuration, as shown in FIG. 2, the lower arm side FETs (Q4, Q5) are based on the voltage drop when the lower arm side FETs (Q4, Q5, Q6) are conducted. , Q6) is provided with a current detection circuit 14 for detecting the current flowing in the current. The current detection circuit 14 corresponds to each of the lower arm side FETs (Q4, Q5, Q6), and each of them has a first resistor (R1, R2, R3) and a second resistor (Ro1, Ro2, Ro3). A resistance series circuit (resistance voltage dividing circuit). In this resistor series circuit (resistor voltage dividing circuit), one end of the first resistor (R1, R2, R3) is connected to the drain terminal D of the corresponding FET (Q4, Q5, Q6), and the other end is the second. Are connected to one end of each of the resistors (Ro1, Ro2, Ro3) and the other end of the second resistor (Ro1, Ro2, Ro3) is connected to the circuit ground G. The ratio of the resistance values of the second resistors (Ro1, Ro2, Ro3) and the first resistors (R1, R2, R3) (for example, the second resistor Ro1 / the first resistor R1) corresponds. Set to match the ratio of the on-resistance Ron and the wiring pattern resistance (Rp1, Rp2, Rp3) when the FETs (Q4, Q5, Q6) are conductive (for example, the on-resistance Ron / wiring pattern resistance Rp3). The voltage at the connection point (nodes N1, N2, and N3) between the first resistor (R1, R2, and R3) and the second resistor (Ro1, Ro2, and Ro3) and the voltage with respect to the circuit ground G is set to FET ( Q4, Q5, and Q6) are output as detection signals for the current flowing through them.

Thereby, in the motor control device 11, the current flowing through the FETs (Q4, Q5, Q6) mounted on the printed circuit board is changed to the drain terminal D and the circuit ground G when the FETs (Q4, Q5, Q6) are turned on. When detecting based on the voltage drop V _DG between the two, the offset generated by the wiring pattern resistance (Rp1, Rp2, Rp3) of the wiring pattern that forms the current path of the FET (Q4, Q5, Q6) can be easily obtained to cancel, it is possible to detect the drain-to-source voltage _{V DS} of FET (Q4, Q5, Q6) . For this reason, it is possible to detect the current flowing through the FETs (Q4, Q5, Q6) by canceling the influence of the wiring pattern resistances (Rp1, Rp2, Rp3).

(4) Further, in the above embodiment, the motor control device 11 compares the on resistance (Ron) of the FETs (Q4, Q5, Q6) and the resistance values of the wiring pattern resistors (Rp1, Rp2, Rp3). The resistance values of the first resistor (R1, R2, R3) and the second resistor (Ro1, Ro2, Ro3) satisfy the tolerance required to detect the current flowing through the FET (Q4, Q5, Q6). Thus, it is set to a sufficiently large value.
Thereby, the current flowing through the offset resistors (Ro1, Ro2, Ro3) and the detection unit resistors (R1, R2, R3) can be reduced, and the detection error of the current flowing through the FETs (Q4, Q5, Q6) can be reduced. .

  (5) In the above embodiment, the motor control device 11 applies each of the second resistors (Ro1, Ro2, Ro3) in the resistor series circuit corresponding to the lower arm side FETs (Q4, Q5, Q6). The switches (switches SW1, SW2, SW3) connected in parallel are turned off in accordance with the conduction timing of the corresponding FETs (Q4, Q5, Q6) on the lower arm side, and the corresponding FETs (Q4, Q5, Q6) ) Is output only when the FET is turned on (switches SW1, SW2, SW3).

Thereby, the current detection signal of the FET (Q4, Q5, Q6) can be output only when the FET is conductive. For this reason, when the FET is turned off, the output of the current detection signal is stopped, so that the current detection signals of other phases are not affected by noise or the like. Further, in the motor control device described in Patent Document 1 shown in FIG. 4, the analog switches AS ₁ , AS ₂ , and AS ₃ have signal detection paths (paths of signal lines connecting the drain terminals of the FET and the input terminal of the amplifier AM). ), The current detection signal may be affected by the internal impedances of the analog switches AS ₁ , AS ₂ , AS _{3. In} the motor control device 11 of the present embodiment shown in FIG. Since the switch (SW1, SW2, SW3) is not inserted into the signal detection path (the path of the signal line connecting the drain terminal of the FET and the input terminal of the comparator), the switch (SW1, SW2, SW3) is used when detecting the signal. It is not affected by the internal impedance of

(6) Further, in the above embodiment, the motor control device 11 indicates that the current detection signal when the lower arm side FETs (Q4, Q5, Q6) are turned on has a predetermined overcurrent setting reference voltage (VR1, VR2, VR3, Overcurrent detection circuit 15 that outputs an overcurrent detection signal when VR4) is exceeded, and when the overcurrent detection signal is output from overcurrent detection circuit 15, each FET (Q1 to Q6) of three-phase bridge circuit 12 And an overcurrent protection unit 24 that turns off all of the above.
Thus, when an overcurrent state is detected in any of the lower arm side FETs (Q4, Q5, Q6), all the FETs (Q4, Q5, Q6) of the three-phase bridge circuit 12 are immediately turned off all at once. can do. For this reason, it is possible to avoid the FETs (Q4, Q5, Q6) from being damaged by the overcurrent.

  The embodiment of the present invention has been described above, but the current detection circuit of the present invention. The motor control device is not limited to the illustrated example described above, and can be variously modified without departing from the scope of the present invention. In addition, the switching element of the present invention is indicated by FET in the above-described illustrated example, but is not limited to this as long as it is a switching element. The switch of the present invention may be a switch element or an analog switch, and is not limited to this.

1, 14 Current detection circuit,
DESCRIPTION OF SYMBOLS 10 3 phase alternating current motor 11 Motor control apparatus 12 3 phase bridge circuit 13 Gate drive circuit 14 Current detection circuit 15 Overcurrent detection circuit 20 Control part 21 FET signal generation part 22 Current supply control part 23 Synchronization signal generation part 24 Overcurrent protection part Q1 , Q2, Q3 Upper arm side FET
Q4, Q5, Q6 Lower arm FET
CP1, CP2, CP3, CP4 Comparator Ron FET on-resistance Rp1, Rp2, Rp3 Wiring pattern resistance Rd, R1, R2, R3 Detector resistance (first resistance)
Ro, Ro1, Ro2, Ro3 Offset resistance (second resistance)
SW1, SW2, SW3 Switch AM11, AM12, AM13 Amplifier (amplifier)

Claims (6)

One input / output terminal of the switch element mounted on the printed wiring board is connected to a negative electrode terminal provided on the printed wiring board via a wiring pattern on the printed wiring board, and the negative electrode terminal is In a circuit connected to the negative side of a DC power supply that supplies current to the switch element, and connected to a circuit ground of a control circuit that controls the switch element,
A current detection circuit for detecting a current flowing through the switch element based on a voltage drop during conduction of the switch element is a first detection circuit connected between the other input / output terminal of the switch element and the circuit ground. A resistor series circuit comprising a resistor and a second resistor;
In the resistor series circuit,
One end of the first resistor is connected to the other input / output terminal of the switch element, the other end is connected to one end of the second resistor, and the other end of the second resistor is connected to the circuit ground. ,
The ratio of the resistance value between the second resistance and the first resistance (second resistance / first resistance) is the ratio of the resistance value between the ON resistance and the wiring pattern resistance when the switch element is conductive (ON Resistance / wiring pattern resistance),
A current detection circuit that outputs a voltage of a connection point between the first resistor and the second resistor and a voltage with respect to the circuit ground as a detection signal of a current flowing through the switch element. Compared to the on-resistance of the switch element and the resistance value of the wiring pattern resistance, the resistance value of the first resistor and the second resistor has a tolerance required for detecting the current flowing through the switch element. The current detection circuit according to claim 1, wherein the current detection circuit is set to a sufficiently large value so as to satisfy. Using a three-phase bridge circuit of switch elements mounted on a printed circuit board and an inverter comprising its control circuit, a three-phase AC voltage is generated from a DC voltage input from a DC power source to rotate the three-phase AC motor. A motor control device for controlling, wherein a current path of a current flowing from the DC power supply to each switch element is formed by a wiring pattern on the printed circuit board, and each switch element on the lower arm side and a negative electrode of the DC power supply One end of each wiring pattern serving as a current path to the side is connected to one input / output terminal of the corresponding switch element on the lower arm side, and the other end is provided on the printed wiring board. A motor connected to a negative electrode terminal, the negative electrode terminal being connected to the negative electrode side of the DC power supply and connected to the circuit ground of the control circuit In the control device,
A current detection circuit for detecting a current flowing through the switch element based on a voltage drop at the time of conduction of the switch element on the lower arm side corresponds to each switch element on the lower arm side. Each resistor series circuit comprising a first resistor and a second resistor connected between an input / output terminal and the circuit ground,
In each of the resistor series circuits,
One end of the first resistor is connected to the other input / output terminal of the corresponding switch element, the other end is connected to one end of the second resistor, and the other end of the second resistor is connected to the circuit ground. And
The ratio of the resistance value between the second resistor and the first resistor (second resistor / first resistor) is the ratio of the resistance value between the on-resistance and the wiring pattern resistance when the corresponding switch element is conductive. (ON resistance / wiring pattern resistance)
A motor control device that outputs a voltage at a connection point between the first resistor and the second resistor and a voltage with respect to the circuit ground as a detection signal of a current flowing through the switch element. Compared to the on-resistance of the switch element and the resistance value of the wiring pattern resistance, the resistance value of the first resistor and the second resistor has a tolerance required for detecting the current flowing through the switch element. The motor control device according to claim 3, wherein the motor control device is set to a sufficiently large value so as to satisfy. A switch connected in parallel to each of the second resistors corresponding to each switch element on the lower arm side,
4. The switch according to claim 3, further comprising a switch that is turned off in accordance with a conduction timing of the corresponding switch element on the lower arm side and outputs a current detection signal of the corresponding switch element only when the switch element is conductive. Item 5. The motor control device according to Item 4. An overcurrent detection circuit that outputs an overcurrent detection signal when the current detection signal when the lower arm side switch element is on exceeds a predetermined overcurrent setting reference voltage;
An overcurrent protection unit that turns off all the switch elements of the three-phase bridge circuit when an overcurrent detection signal is output from the overcurrent detection circuit;
The motor control device according to claim 3, comprising:

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