JP5714792B2 - Instruction control circuit, instruction control method, and information processing apparatus - Google Patents

Description

  The present invention relates to an instruction control circuit, an instruction control method, and an information processing apparatus, and more particularly to an instruction control circuit, an instruction control method, and an information processing apparatus that realize low power consumption.

  An example of power consumption control is described in Patent Document 1. The data processing apparatus of Patent Literature 1 includes a buffer for storing data, a data supply unit that supplies data to the buffer, and a data supply control unit that controls an operation mode of the data supply unit. The power consumption of the data processing apparatus itself is controlled by shifting the data supply unit to the low power mode or the normal mode based on the data accumulation amount.

  Another example of power consumption control is described in Patent Document 2. The memory management unit of Patent Document 2 includes a memory management unit control circuit, an address translation buffer including a plurality of entries, an entry selection unit, and a power control unit. The power control unit outputs information from the entry selection unit and the memory management unit. The power of the address translation buffer entry is controlled based on the output information.

  Another example of power consumption control is described in Patent Document 3. The parallel processing processor of Patent Literature 3 includes an instruction processing unit having a command decoding unit and a plurality of computing units, and a power control unit, and the power control unit outputs a unit selection signal and a power mode setting signal output from the command decoding unit. Based on the above, the clock and power supply to each arithmetic unit are controlled.

JP 2007-095040 A WO2004 / 104841 publication Japanese Patent Laid-Open No. 2003-263311

  However, in the techniques as described in Patent Documents 1 to 3 described above, when a plurality of instruction buffers each having a plurality of entries are configured, the number of instruction buffer entries that are operable, that is, that consumes power, are included. There is a problem that it cannot be finely controlled according to the dynamic characteristics of the application.

  In the following, this problem will be further described by way of example with reference to FIG. FIG. 4 shows a general processor having the instruction cache 10, the instruction execution unit 60, and the instruction control circuit 900. Regarding the configuration and operation of such a processor, the following Non-Patent Document 1 can be referred to.

David A. Patterson, John L. Hennessy, Mitsue Narita, “Computer Configuration and Design” 3rd edition [bottom] 6.9 Advanced Pipeline Processing: Further Improvements in the Future, 2006.

  Referring to FIG. 4, the instruction control circuit 900 includes an instruction dispatch control unit 920, a buffer A (hereinafter “Abuf”) 941, a buffer B (hereinafter “Bbuf”) 942 and a buffer each having “32” entries. C (hereinafter “Cbuf”) 943.

  The instruction dispatch control unit 920 includes an instruction dispatch control circuit 924, an Abuf registration number counter 21, a Bbuf registration number counter 22, and a Cbuf registration number counter 23 that count the number of entries in which instructions are registered in the Abuf 941, Bbuf 942, and Cbuf 943, respectively. And an instruction register dU 925 for storing an instruction fetched from the instruction cache 10 and an instruction register dL 926.

  The Abuf registration number counter 921, the Bbuf registration number counter 922, and the Cbuf registration number counter 923 input the instruction DSP (Dispatch) -Abuf, the instruction DSP-Bbuf, and the instruction DSP-Cbuf, which are instruction registration instruction signals, respectively, and “1”. Count up, and input entry release signals Erel-Abuf, Erel-Bbuf and Erel-Cbuf, respectively, and count down by "1". Further, the Abuf registered number counter 921, the Bbuf registered number counter 922, and the Cbuf registered number counter 923 generate a Busy signal of Abuf-full / Bbuf-full / Cbuf-full when each registered number counter becomes 32.

  If the Busy signal is raised, the instruction dispatch control circuit 924 holds the instruction register dU 925 and the instruction register dL 926 and postpones the acquisition of the instruction.

  In the instruction control circuit 900, instruction buffer registration control is performed as described above.

FIG. 5 shows that in the above configuration, the instruction dispatch control circuit 924 holds the instruction register dU 925 and the instruction register dL 926 because the Abuf registered number counter 921 becomes “32”, and the instruction DSP-Abuf is postponed. It shows the situation where the movement has stopped (TMG2 ~ TMG5). In this case, even if it is unavoidable that the resource of Abuf 941 is depleted and the instruction supply rate deteriorates, the subsequent Bbuf input instruction and Cbuf input instruction are stopped, and the unused entry “17” of Bbuf 942 and the unused Cbuf 943 are not used. The usage entry “25” remains in a state where power is consumed. This is a problem in terms of performance per power. In the example of Fig. 5, instruction DSP-Abuf is issued in TMG6, and Bbuf input instruction and C-buf input instruction are continuously dispatched in TMG7 and TMG8. . If the instruction execution unit 60 is configured to execute out-of-order execution, dispatch of Bbuf / Cbuf input instructions will be executed at an earlier timing, but out-of-order execution control is possible. Doing so complicates the architecture and increases power consumption. Therefore, it is not effective as a solution to the problem of performance improvement per electric power.

  On the other hand, supplying power to the unused Bbuf 942 and Cbuf 943 is a problem from the viewpoint of power saving. In the example of FIG. 5, the Bbuf registration number counter 22 and the Cbuf registration number counter 23 remain “15” and “7”, respectively, so the maximum entries of Bbuf 942 and Cbuf 943 are “16” and “8”, respectively. However, there is no change in performance. Therefore, the power supply control and the clock of the entries “16” and “24” that are not used by the Bbuf 942 and the Cbuf 943, respectively, are reduced in an efficient power saving control based on the movement of the entire processor. Here, the usage of Abuf 941, Bbuf 942, and Cbuf 943 depends on the application, but a method of determining the buffer capacity based on a static analysis at the time of compiler is not effective.

  That is, there is a problem that even if the technique described in any one of Patent Documents 1 to 3 is used, the power consumption of the instruction buffer entry cannot be dynamically controlled while maintaining the performance balance.

  An object of the present invention is to provide an instruction control circuit, an instruction control method, and an information processing apparatus that solve the above-described problems.

The instruction control circuit of the present invention includes a plurality of instruction buffers each having a plurality of entries,
For each of the plurality of instruction buffers, a time counting unit that measures a buf-full time in which all the entries for each instruction buffer are in use,
A time analysis unit that calculates the number of entries after reduction based on the buf-full time;
And a control unit that controls stop or reduction of power consumption of each of the plurality of entries based on the number of entries after reduction.

In the instruction control method of the present invention, for each of a plurality of instruction buffers each having a plurality of entries, the buf-full time during which all the entries for each instruction buffer are in use is counted,
Calculate the number of entries after reduction based on the buf-full time,
Control of stopping or reducing power consumption of each of the plurality of entries is performed based on the number of entries after reduction.

  According to the present invention, it is possible to dynamically and finely reduce the power consumption of entries unnecessary for maintaining the performance balance among the entries in the instruction buffer.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, the first embodiment of the present invention includes an instruction cache 10, an instruction execution unit 60, and an instruction control circuit 200.

  The instruction cache 10 is a cache memory, for example, and holds an instruction 100 of an application program executed by the instruction execution unit 60.

  The instruction execution unit 60 is, for example, a multiple instruction issue type pipeline, and executes each stage (instruction decode / execute, register file read / write-back, memory access, etc.) of the instruction acquired from the instruction control circuit 200. .

  The instruction control circuit 200 acquires an instruction from the instruction cache 10 by the configuration and operation described in detail below, dispatches the acquired instruction, and passes the acquired instruction to the instruction execution unit 60. The instruction control circuit 200 includes an instruction dispatch control unit 20, an Abuf 41, a Bbuf 42, a Cbuf 43, and a buffer full time analysis control unit 50.

  The instruction dispatch control unit 20 includes an Abuf registration number counter 21, a Bbuf registration number counter 22, a Cbuf registration number counter 23, an instruction dispatch control circuit 24, an instruction register du25, an instruction register dL26, and a Buf number update interval REG27. The “instruction dispatch control unit 20” can be generally called a “control unit”.

  The Abuf registered number counter 21, the Bbuf registered number counter 22, and the Cbuf registered number counter 23 are, for example, counter circuits, and the number of entries in which instructions are registered in the Abuf 41, Bbuf 42, and Cbuf 43, respectively (hereinafter referred to as the registered entry number). Hold. The Abuf registered number counter 21, the Bbuf registered number counter 22 and the Cbuf registered number counter 23 receive the instruction DSP-Abuf signal, the instruction DSP-Bbuf signal and the instruction DSP-Cbuf signal, respectively. When “1” is added and an Abuf entry release signal, a Bbuf entry release signal, and a Cbuf entry release signal are input, “1” is subtracted from the number of registered entries held.

  The instruction dispatch control circuit 24 is, for example, a logic circuit, and controls the operation of the entire instruction dispatch control unit 20 to monitor the number of registered entries so that the Abuf 41, Bbuf 42, and Cbuf 43 do not overflow. The registration control of the instruction to Cbuf 43 is executed. At the same time, the instruction dispatch control circuit 24 instructs to stop or reduce the power consumption of each entry of the Abuf 41, the Bbuf 42, and the Cbuf 43 based on the number of entries after reduction described later.

  Specifically, when the instruction dispatch control circuit 24 receives the instruction fetch dl signal, the instruction dispatch control circuit 24 selects any one of Abuf 41, Bbuf 42, or Cbuf 43 corresponding to the classification of the instruction 126, and selects the selected Abuf 41, Bbuf 42, and Cbuf 43, respectively. The corresponding instruction DSP-Abuf signal and instruction DSP-Abuf signal, instruction DSP-Bbuf signal and instruction DSP-Bbuf signal, instruction DSP-Cbuf signal and instruction DSP-Cbuf signal are output. Each of these signals is a pulse signal, for example.

  In parallel with the above operation, when the instruction dispatch control circuit 24 receives the instruction fetch dl signal, the instruction dispatch control circuit 24 compares the registered entry number of the Abuf registered number counter 21 with the reduced entry number of the A-Buf reduced entry number REG55. If they are equal and the Abuf-full signal is off, it is detected that the Abuf 41 is full, and the Abuf-full signal is turned on. The Abuf-full signal is, for example, a level signal, indicating that the number of registered entries corresponding to the Abuf 41 and the number of entries after reduction are equal in the on state, and the number of registered entries corresponding to the Abuf 41 in the off state is less than the number of entries after reduction. Indicates that Similarly, the instruction dispatch control circuit 24 controls the Bbuf-full signal and the Cbuf-full signal, respectively, based on the number of registered entries corresponding to Bbuf 42 and Cbuf 43 and the number of entries after reduction.

  In addition, when any one or more of the Abuf-full signal, the Bbuf-full signal, and the Cbuf-full signal are turned on, the instruction dispatch control circuit 24 simultaneously turns on the DLHLD signal. The DLHLD signal is a level signal, for example.

  Further, upon receiving the instruction fetch dl signal, the instruction dispatch control circuit 24 receives the reduced entry number REG55 (referred to as the current reduced entry number) and the previous instruction fetch dl signal when the A-Buf reduced entry number is input. The number of entries after reduction that has been read and stored (referred to as the number of entries after pre-reduction) is compared. The instruction dispatch control circuit 24 does nothing as the corresponding operation when the number of entries after the current reduction is equal to the number of entries after the previous reduction, and when the number of entries after the current reduction exceeds the number of entries after the previous reduction. Indicates to Abuf 41 the current number of entries after reduction, and indicates an entry to stop or reduce power consumption. In addition, when the number of entries after the current reduction is less than the number of entries after the previous reduction, the instruction dispatch control circuit 24 determines that the number of registered entries in the Abuf registration number counter 21 is equal to or less than the number of entries after the current reduction. The number of entries after the current reduction is indicated to indicate an entry for stopping or reducing power consumption. By a similar operation, the instruction dispatch control circuit 24 indicates the number of entries after the current reduction to the Bbuf 42 and the Cbuf 43 and instructs an entry for stopping or reducing the power consumption.

  The instruction register du25 is, for example, a register circuit. When the DLHLD signal is off at the instruction fetch timing, the instruction register du25 acquires the instruction 100 from the instruction cache 10 and holds it as the instruction 125, and when the DLHLD signal is on. Does not obtain the instruction 100 from the instruction cache 10.

  The instruction register dL26 is, for example, a register circuit. When the DLHLD signal is off at the instruction fetch timing, the instruction register dL26 acquires the instruction 125 from the instruction register du25 and holds it as the instruction 126, and outputs the instruction fetch dl signal. When the DLHLD signal is on, the instruction 125 is not acquired from the instruction register du25. The instruction fetch dl signal is a pulse signal, for example.

  The Buf number update interval REG27 is, for example, a register circuit that can be accessed by a program, and holds a time interval for executing processing for calculating the number of entries after reduction, which will be described later. This time interval is set, for example, from update interval setting means (not shown) realized as part of process switching processing in an operating system operating on a computer on which the instruction dispatch control unit 20 is mounted. The unit of the set time interval is, for example, the number of clocks of the operation clock (not shown) of the instruction execution unit 60. Alternatively, the unit of the set time interval may be the number of clocks of a dedicated oscillator (not shown) or an operation clock (not shown) of another circuit. The “Buf number update interval REG27” can be generally called a “Buf number update interval holding unit”.

  Abuf 41, Bbuf 42, and Cbuf 43 are, for example, FIFO (First In First Out) buffer circuits, each of which has, for example, 32 entries (maximum number of entries = 32) in this embodiment. Abuf 41, Bbuf 42, and Cbuf 43 to be stored are assigned in accordance with the instruction classification such as an instruction or a branch instruction. It should be noted that the number of entries may be configured to have an arbitrary number in other embodiments, and the storage allocation may correspond to another arbitrary instruction classification.

  When the instruction DSP-Abuf signal, the instruction DSP-Bbuf signal, and the instruction DSP-Cbuf signal are input to the Abuf 41, Bbuf 42, and Cbuf 43, the instruction 126 is acquired from the instruction register dl26 and registered in the respective entries. Further, when the instruction 126 registered in the entry is output to the instruction execution unit 60, the Abuf 41, Bbuf 42, and Cbuf 43 output an Abuf entry release signal, a Bbuf entry release signal, and a Cbuf entry release signal, respectively. The Abuf entry release signal, the Bbuf entry release signal, and the Cbuf entry release signal are, for example, pulse signals.

  Abuf 41, Bbuf 42, and Cbuf 43 respond to an instruction to stop or reduce power consumption from instruction dispatch control circuit 24, stop the clock of each entry, stop the power supply, or shift to the low power mode. In addition, you may refer description of patent document 1, patent document 2, patent document 3, etc. for the concrete implementation | achievement method of such a stop or reduction of power consumption. Note that “Abuf 41”, “Bbuf 42”, and “Cbuf 43” can be generally called “instruction buffers”.

  The buffer full time analysis control unit 50 includes a Buf-full time analysis circuit 51, an Abuf-full time counter 52, a Bbuf-full time counter 53, a Cbuf-full time counter 54, an A-Buf reduced entry number REG55, and a B-Buf. It includes the entry number REG56 after reduction and the entry number REG57 after C-Buf reduction. The “Abuf-full time counter 52”, the “Bbuf-full time counter 53”, and the “Cbuf-full time counter 54” can be generally referred to as a “time counter”.

  The Buf-full time analysis circuit 51 is, for example, a logic circuit, and controls the operation of the entire buffer full time analysis control unit 50. Based on the time when the Abuf 41, Bbuf 42, and Cbuf 43 are in the buffer full state, the execution state of the application program The number of entries after reduction of Abuf 41, Bbuf 42, and Cbuf 43 in accordance with is calculated. The “Buf-full time analysis circuit 51” can be generally called a “time analysis unit”.

  Specifically, the Buf-full time analysis circuit 51 measures the time interval acquired from the Buf number update interval REG 27, and executes the following processing for each time interval.

  First, the Buf-full time analysis circuit 51 sets the Abuf-full for each number of entries after reduction held in the entry number REG55 after A-Buf reduction, the entry number REG56 after B-Buf reduction, and the entry number REG57 after C-Buf reduction. The fullness values of Abuf 41, Bbuf 42, and Cbuf 43 are calculated by multiplying each time held by the time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54. Subsequently, the Buf-full time analysis circuit 51 calculates the ratio of each fullness value to the maximum fullness value among these fullness values, and Abuf41, Bbuf42 and Cbuf43 corresponding to the ratio of each fullness value. The new number of entries after reduction is calculated by multiplying the maximum number of entries.

  Next, the Buf-full time analysis circuit 51 sets the calculated post-reduction entry number to the A-Buf reduction entry number REG55, the B-Buf reduction entry number REG56, and the C-Buf reduction entry number REG57, respectively.

  At the same time, the Buf-full time analysis circuit 51 outputs a count reset signal.

  The Abuf-full time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54 are, for example, counter circuits, and hold the time during which the Abuf 41, Bbuf 42, and Cbuf 43 are full.

  Specifically, the Abuf-full time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54 count the counter while the Abuf-full signal, the Bbuf-full signal, and the Cbuf-full signal are on, respectively. Up. Note that these counter circuits execute counting by an operation clock (not shown) of the instruction dispatch control unit 20 or an operation clock (not shown) of the instruction execution unit 60, for example. Further, the Abuf-full time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54 input a count reset signal and clear the counter to “0”.

  The entry number REG55 after A-Buf reduction, the entry number REG56 after B-Buf reduction, and the entry number REG57 after C-Buf reduction are, for example, register circuits, and Abuf 41, Bbuf 42, and Cbuf 43 set by the Buf-full time analysis circuit 51, respectively. Holds the number of entries after reduction. Note that the initial setting values of the entry number REG55 after A-Buf reduction, the entry number REG56 after B-Buf reduction, and the entry number REG57 after C-Buf reduction are respectively the maximum entries of Abuf 41, Bbuf 42, and Cbuf 43 (in this embodiment, "32").

  Next, the operation of calculating the post-reduction entry number of the Buf-full time analysis circuit 51 will be described with a specific example.

  After the initial setting, the time when Abuf 41, Bbuf 42 and Cbuf 43 were full during the time interval (for example, 1,000,000 clocks) first acquired from Buf number update interval REG27 was 120,000 clocks, 60,000 clocks and 90,000 clocks, respectively. Suppose there was.

  First, the Buf-full time analysis circuit 51 calculates the fullness value as follows.

  (Fullness value of Abuf 41) = (Number of entries after reduction held by REG55 after A-Buf reduction) × (Time held by Abuf-full time counter 52) = 32 × 120,000 = 3,840,000.

  (Fullness value of Bbuf 42) = (Number of post-reduction entries held in the REG 56 after B-Buf reduction) × (Time held by the Bbuf-full time counter 53) = 32 × 60,000 = 1,920,000.

  (Fullness value of Abuf 41) = (Number of entries after reduction held in REG 57 after C-Buf reduction) × (Time held by Cbuf-full time counter 54) = 32 × 90,000 = 2,880,000.

  Subsequently, the Buf-full time analysis circuit 51 calculates a ratio of each fullness value to the maximum fullness value (3,840,000 in this example) among these fullness values.

  (Abuf 41 fullness value ratio) = 3,840,000 ÷ 3,840,000 = 1.

  (Fullness value ratio of Bbuf42) = 1,920,000 ÷ 3,840,000 = 0.5.

  (Fullness value ratio of Cbuf43) = 2,880,000 ÷ 3,840,000 = 0.75.

  Subsequently, the Buf-full time analysis circuit 51 multiplies the maximum number of entries of Abuf 41, Bbuf 42, and Cbuf 43 corresponding to the ratio of the fullness value (rounds up the decimal point) to calculate a new number of entries after reduction.

  (New number of entries after reduction of Abuf 41) = 1 × 32 = 32.

  (New number of entries after reduction of Bbuf 42) = 0.5 × 32 = 16.

  (New number of entries after reduction of Cbuf 43) = 0.75 × 32 = 24.

  After setting the number of entries after reduction calculated in this way, the time when Abuf 41, Bbuf 42 and Cbuf 43 are full during the time interval obtained by measuring the time interval obtained from Buf number update interval REG27 again is 120,000 clocks, 130,000 clocks and 110,000 clocks, respectively. Suppose there was.

  This time, the Buf-full time analysis circuit 51 calculates the fullness value as follows.

  (Fullness value of Abuf 41) = 32 × 120,000 = 3,840,000.

  (Fullness value of Bbuf42) = 16 × 130,000 = 2,080,000.

  (Fullness value of Abuf 41) = 24 × 110,000 = 2,640,000.

  Subsequently, the Buf-full time analysis circuit 51 calculates a ratio of each fullness value to the maximum fullness value (3,840,000 in this example) among these fullness values.

  (Abuf 41 fullness value ratio) = 3,840,000 ÷ 3,840,000 = 1.

  (Fullness value ratio of Bbuf42) = 2,080,000 ÷ 3,840,000 = 0.54.

  (Fullness value ratio of Cbuf43) = 2,640,000 ÷ 3,840,000 = 0.69.

  Subsequently, the Buf-full time analysis circuit 51 multiplies the maximum number of entries of Abuf 41, Bbuf 42, and Cbuf 43 corresponding to the ratio of the fullness value to calculate a new number of entries after reduction.

  (New number of entries after reduction of Abuf 41) = 1 × 32 = 32.

  (New number of entries after reduction of Bbuf 42) = 0.54 × 32 = 18.

  (New number of entries after reduction of Cbuf 43) = 0.69 × 32 = 23.

  The above is the description of the operation for calculating the post-reduction entry count of the Buf-full time analysis circuit 51 according to a specific example.

  FIG. 2 shows a basic configuration of the present embodiment. According to FIG. 2, the instruction control circuit 201 includes an Abuf 41, a Bbuf 42, a Cbuf 43, an Abuf-full time counter 52, a Bbuf-full time counter 53, a Cbuf-full time counter 54, a buf-full time analysis circuit 51, and an instruction dispatch control. Part 20.

  Each of Abuf 41, Bbuf 42, and Cbuf 43 has 32 entries.

  The Abuf-full time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54 are buf-full in which all 32 entries for each Abuf 41, Bbuf 42, and Cbuf 43 are in use. Time is measured.

  The buf-full time analysis circuit 51 calculates the number of entries after reduction based on the buf-full time counted by the Abuf-full time counter 52, the Bbuf-full time counter 53, and the Cbuf-full time counter 54.

  The instruction dispatch control unit 20 controls the stop or reduction of the power consumption of each entry of the Abuf 41, Bbuf 42, and Cbuf 43 based on the number of entries after reduction calculated by the buf-full time analysis circuit 51.

  The first effect of the present embodiment described above is that the power of entries unnecessary for maintaining the performance balance among the entries in the instruction buffer can be dynamically and finely reduced. The reason is that the number of entries used is determined based on the time balance due to the instruction buffer full.

  The second effect in the present embodiment described above is that the first effect can be obtained even when the operation of the application changes significantly dynamically. This is because the interval for determining the number of entries used can be changed.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 3, the configuration of the second embodiment is different from the configuration of the first embodiment shown in FIG. 1 in that a margin REG 32 is added to the instruction dispatch control unit 20. . Further, the second embodiment differs from the first embodiment in the operation of the Buf-full time analysis circuit 51.

  The margin REG32 is a register circuit that can be accessed by a program, for example, and holds a margin for reference when the Buf-full time analysis circuit 51 adjusts the number of entries after reduction. The margin set is an increase / decrease value of the number of entries after reduction calculated based on the buf-full time, for example. Alternatively, the margin may be an increase / decrease value of the buf-full time that is a basis for calculating the number of entries after reduction. The “margin REG32” can be generally referred to as “margin holding unit”.

  The Buf-full time analysis circuit 51 adjusts the new post-reduction entry number by increasing or decreasing the new post-reduction entry number calculated based on the buf-full time based on the spare degree obtained from the spare degree REG32. To do. For example, the Buf-full time analysis circuit 51 adds a margin value to the new post-reduction entry number calculated based on the buf-full time within a range not exceeding the maximum number of entries.

  Next, the Buf-full time analysis circuit 51 sets the adjusted number of entries after reduction to an entry number REG55 after A-Buf reduction, an entry number REG56 after B-Buf reduction, and an entry number REG57 after C-Buf reduction, respectively.

  For example, an operation in which the Buf-full time analysis circuit 51 adjusts the number of entries after reduction when “1” is set in the margin REG32 will be described.

  First, as described in the first embodiment, the Buf-full time analysis circuit 51 calculates a new post-reduction entry number as follows.

  (New number of entries after reduction of Abuf 41) = 1 × 32 = 32.

  (New number of entries after reduction of Bbuf 42) = 0.5 × 32 = 16.

  (New number of entries after reduction of Cbuf 43) = 0.75 × 32 = 24.

  Next, the Buf-full time analysis circuit 51 adjusts the new number of entries after reduction based on the margin “1” as follows.

  (Adjustment result of new number of entries after reduction of Abuf 41) = 32.

  (Adjustment result of new number of entries after reduction of Bbuf 42) = 16 + 1 = 17.

  (Adjustment result of new number of entries after reduction of Cbuf 43) = 24 + 1 = 25.

  The margin may be a negative value such as “−1”. In this case, the number of entries after reduction is adjusted to be small. Further, the margin REG 32 may be configured to correspond to each instruction buffer.

  The effect in the present embodiment described above is that the performance or power saving can be emphasized more than the effect in the first embodiment. The reason is that the new number of entries after reduction is adjusted based on the margin.

  Each component described in each of the above embodiments does not necessarily have to be individually independent, and a plurality of components are realized as a single module, or a single component is realized as a plurality of modules. Alternatively, a configuration in which a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like may be employed.

  Furthermore, in each embodiment described above, a plurality of operations are not limited to being executed at different timings. For example, another operation may occur during the execution of a certain operation, or part or all of the execution timing of a certain operation and the execution timing of another operation may overlap.

  Further, in each of the embodiments described above, it is described that a certain operation becomes a trigger for another operation, but the description does not limit all relationships between the certain operation and the other operations. For this reason, when each embodiment is implemented, the relationship between the plurality of operations can be changed within a range that does not hinder the contents. The specific description of each operation of each component does not limit each operation of each component. For this reason, each specific operation of each component may be changed within a range that does not hinder the functional, performance, and other characteristics in implementing each embodiment.

  In addition, each component in each embodiment described above may be realized by hardware, software, or a mixture of hardware and software, if necessary. May be.

  Further, the physical configuration of each component is not limited to the description in the above embodiment, and may exist independently, may exist in combination, or may be separated. It may be configured.

  The present invention can be applied to, for example, a supercomputer that requires power saving without performance degradation.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a block diagram which shows the basic composition of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of a related command control circuit. It is a time chart which shows operation | movement of a related command control circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Instruction cache 20 Instruction dispatch control part 21 Abuf registration number counter 22 Bbuf registration number counter 23 Cbuf registration number counter 24 Instruction dispatch control circuit 41 Abuf
42 Bbuf
43 Cbuf
50 Buffer full time analysis control unit 51 Time analysis circuit 52 Abuf-full time counter 53 Bbuf-full time counter 54 Cbuf-full time counter 60 Instruction execution unit 200 Instruction control circuit 201 Instruction control circuit 920 Instruction dispatch control unit 921 Number of registered Abuf Counter 922 Bbuf registered number counter 923 Cbuf registered number counter 924 Instruction dispatch control circuit 941 Abuf
942 Bbuf
943 Cbuf

Claims (14)

A plurality of instruction buffers each having a plurality of entries;
For each of the plurality of instruction buffers, a time measuring unit that measures a buf-full time in which all the entries of the instruction buffer are in use,
Is the number of post-entry new reduced on the basis of each of the buf-full first reducing the number after entry indicating the number of use of the entries of the ratio of the time when the counting of the buf-full time of the instruction buffer A time analysis unit for calculating a second post-reduction entry number ;
A control unit that controls stop or reduction of power consumption of each of the plurality of entries based on the second post-reduction entry number;
An instruction control circuit comprising: The time analysis unit, the buf-full time and the multiplying and for each of the instruction buffer corresponding to the number of the first reduction after entry to the first number of reductions after entry corresponding to each of the plurality of instruction buffers Calculate the fullness value,
Calculating the ratio of each fullness value to the maximum fullness value of the fullness values;
And calculates the maximum number of entries and a second number of reductions after entry before SL that corresponds to each of said ratios and each said instruction buffer by multiplying the corresponding to each of said instruction buffer for each said instruction buffer The instruction control circuit according to claim 1. A margin holding unit that holds a predetermined margin with respect to the second post-reduction entry number calculated based on the buf-full time;
The instruction control circuit according to claim 1, wherein the time analysis unit increases or decreases the second post-reduction entry count based on the margin. 4. The instruction control circuit according to claim 3, wherein the margin held by the margin holding unit is rewritable. A Buf number update interval holding unit for holding a predetermined time interval for calculating the second post-reduction entry number;
5. The instruction control circuit according to claim 1, wherein the time analysis unit calculates the second post-reduction entry number based on the time interval. 6. The instruction control circuit according to claim 5, wherein the time interval held by the Buf number update interval holding unit is rewritable. The instruction control circuit according to claim 1, further comprising an instruction dispatch control circuit that suspends instruction acquisition based on the second post-reduction entry count. For each of a plurality of instruction buffers each having a plurality of entries, time the buf-full time during which all the entries in the instruction buffer are in use,
Is the number of post-entry new reduced on the basis of each of the buf-full first reducing the number after entry indicating the number of use of the entries of the ratio of the time when the counting of the buf-full time of the instruction buffer Calculate the second post-reduction entry count ,
A command control method comprising: controlling stop or reduction of power consumption of each of the plurality of entries based on the second number of entries after reduction. By multiplying said buf-full time corresponding to said first number of reductions after entry to the first number of reductions after entry corresponding to each of the plurality of instruction buffers to calculate the full degree value for each of the instruction buffer ,
Calculating the ratio of each fullness value to the maximum fullness value of the fullness values;
And calculates the maximum number of entries and a second number of reductions after entry before SL that corresponds to each of said ratios and each said instruction buffer by multiplying the corresponding to each of said instruction buffer for each said instruction buffer The instruction control method according to claim 8. Claim 8 or 9, wherein the relative buf-full time the second number reduction after entry be calculated based on, increase or decrease the number of post-entry the second reduction based on a predetermined margin Instruction control method as described. Instruction control method according to any one of claims 8 to 10, characterized in that for calculating the number of said rear second reduction entries based on a predetermined time interval to calculate the number of the post-second reduction entry . 12. The instruction control method according to claim 8, wherein instruction acquisition is postponed based on the second post-reduction entry number. An information processing apparatus comprising the instruction control circuit according to claim 1. An information processing apparatus that performs dispatch control of instructions by the instruction control method according to claim 8.

Images