JP5713431B2 - Field effect transistor - Google Patents
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- JP5713431B2 JP5713431B2 JP2010286477A JP2010286477A JP5713431B2 JP 5713431 B2 JP5713431 B2 JP 5713431B2 JP 2010286477 A JP2010286477 A JP 2010286477A JP 2010286477 A JP2010286477 A JP 2010286477A JP 5713431 B2 JP5713431 B2 JP 5713431B2
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- 230000005669 field effect Effects 0.000 title claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 39
- 239000010432 diamond Substances 0.000 claims description 39
- 239000010409 thin film Substances 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 239000010408 film Substances 0.000 claims description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 44
- 239000010931 gold Substances 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- WXRGABKACDFXMG-UHFFFAOYSA-N trimethylborane Chemical compound CB(C)C WXRGABKACDFXMG-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本発明は、電界効果型トランジスターに関し、より詳細には、ダイヤモンド薄膜層を備える電界効果型トランジスターに関する。 The present invention relates to a field effect transistor, and more particularly to a field effect transistor including a diamond thin film layer.
ダイヤモンド半導体は、半導体最大の絶縁耐圧、熱伝導性を有するばかりでなく、電子や正孔の移動度やドリフト速度も高く、もしダイヤモンド薄膜を用いた電界効果トランジスター(以下「ダイヤモンドFET」という。)が実用化できれば、既存の半導体の性能を遥かに越える、最高の性能を持つ高周波電力トランジスターが実用可能になる。 Diamond semiconductors not only have the maximum dielectric strength and thermal conductivity of semiconductors, but also have high electron and hole mobility and drift speed, and if they are field effect transistors using diamond thin films (hereinafter referred to as “diamond FETs”). If it can be put into practical use, a high-frequency power transistor with the highest performance that far exceeds the performance of existing semiconductors can be put into practical use.
図2を用いて、従来の水素終端されたダイヤモンドFETの作製工程を説明する。 With reference to FIG. 2, a conventional process for producing a hydrogen-terminated diamond FET will be described.
まず、ダイヤモンド結晶層201を用意し、その結晶層201をCVDリアクター内で水素プラズマに曝して、ダイヤモンド表面を水素ラジカル(「H」で表す。)で終端する(図2(a))。そのようにして水素終端された表面層202を形成する。次に、表面層202上の一部の領域に、空間的に分離された2つの金薄膜203A、203Bを蒸着する(図2(b))。それが各々ソース電極203A、ドレイン電極203Bになる。次に、ソース電極203Aとドレイン電極203Bとの間に、空間的に分離して、Al薄膜204を蒸着する。これがゲート電極204になる(図2(c))。このように作製されたFETを動作させる場合の配線を図2(d)に示す。
First, a
このような従来技術によって作製した、ゲート長1μmのFETのドレイン電流特性を図3に示す。この従来技術によるFETのゲート電圧−3Vにおける最大ドレイン電流密度は、30℃で100mA/mmであった。さらに、図3に示すように、試料温度を上げて行ったところ、150℃付近でドレイン電流密度は急激に減少し、再び室温に戻してもドレイン電流密度は元に戻らなかった(非特許文献1参照)。 FIG. 3 shows the drain current characteristics of an FET having a gate length of 1 μm manufactured by such a conventional technique. The maximum drain current density at a gate voltage of −3 V of the FET according to the prior art was 100 mA / mm at 30 ° C. Furthermore, as shown in FIG. 3, when the sample temperature was raised, the drain current density decreased rapidly around 150 ° C., and the drain current density did not return to room temperature even when the temperature was returned to room temperature (Non-Patent Document). 1).
上述の従来技術によるダイヤモンドFETでは、(1)室温における最大ドレイン電流密度が低いことと、(2)試料を昇温すると、ある温度以上でドレイン電流が劇的に減少し、劣化してしまうことが問題であり、実用に供することができない。 In the above-described diamond FET according to the prior art, (1) the maximum drain current density at room temperature is low, and (2) when the temperature of the sample is raised, the drain current is dramatically reduced and deteriorated at a certain temperature or higher. Is a problem and cannot be put to practical use.
本発明は、このような問題点に鑑みてなされたものであり、その目的は、ダイヤモンドFETにおいて、ドレイン電流特性を改善することにある。また、本発明の別の目的は、そのようなFETに用いることのできるダイヤモンド薄膜を提供することにある。 The present invention has been made in view of such problems, and an object thereof is to improve drain current characteristics in a diamond FET. Another object of the present invention is to provide a diamond thin film that can be used for such FETs.
このような目的を達成するために、本発明の第1の態様は、ホウ素濃度が2×1020cm-3以上3×1021cm-3以下であり、膜厚が1nm以上5nm以下であることを特徴とするダイヤモンド薄膜である。 In order to achieve such an object, according to the first aspect of the present invention, the boron concentration is 2 × 10 20 cm −3 or more and 3 × 10 21 cm −3 or less, and the film thickness is 1 nm or more and 5 nm or less. It is a diamond thin film characterized by this.
また、本発明の第2の態様は、ダイヤモンド結晶層と、前記ダイヤモンド結晶層上のチャネル層と、前記チャネル層上のソース電極、ドレイン電極およびゲート電極とを備え、前記チャネル層は、第1の態様のダイヤモンド薄膜で構成されていることを特徴とする電界効果トランジスターである。 A second aspect of the present invention includes a diamond crystal layer, a channel layer on the diamond crystal layer, and a source electrode, a drain electrode, and a gate electrode on the channel layer, and the channel layer includes a first layer It is comprised with the diamond thin film of the aspect.
また、本発明の第3の態様は、第2の態様において、前記ソース電極および前記ドレイン電極と前記チャネル層との間に、TiC層をそれぞれ備えることを特徴とする。 According to a third aspect of the present invention, in the second aspect, a TiC layer is provided between the source and drain electrodes and the channel layer.
また、本発明の第4の態様は、第2又は第3の態様において、前記ゲート電極と前記チャネル層との間にAl2O3層を備えることを特徴とする。 According to a fourth aspect of the present invention, in the second or third aspect, an Al 2 O 3 layer is provided between the gate electrode and the channel layer.
本発明によれば、ホウ素濃度が2×1020cm-3以上3×1021cm-3以下であり、膜厚が1nm以上5nm以下であることを特徴とするダイヤモンド薄膜をチャネル層に用いることにより、ダイヤモンドFETにおいて、ドレイン電流特性を大幅に改善することができる。 According to the present invention, a diamond thin film characterized in that the boron concentration is 2 × 10 20 cm −3 or more and 3 × 10 21 cm −3 or less and the film thickness is 1 nm or more and 5 nm or less is used for the channel layer. Thus, the drain current characteristics can be greatly improved in the diamond FET.
以下、図面を参照して本発明の実施形態を詳細に説明する。具体的な材料や数値に言及して説明を行うが、これらの材料や数値に本発明の範囲を限定する意図ではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Although description will be made with reference to specific materials and numerical values, the scope of the present invention is not intended to be limited to these materials and numerical values.
本発明に係るダイヤモンドFETの構造をその作製工程に沿って説明する。 The structure of the diamond FET according to the present invention will be described along the manufacturing process.
まず、ダイヤモンド結晶層1の表面上に、マイクロ波CVD装置でトリメチルボロン(TMB)とメタンを水素で希釈した原料ガスを供給し、ホウ素が高濃度にドープされたダイヤモンド薄膜層102を結晶成長する(図1(a))。結晶成長時のマイクロ波電力を500W、基板温度を600℃、B/C原子濃度比を6000ppmとした。
First, a raw material gas obtained by diluting trimethylboron (TMB) and methane with hydrogen is supplied on the surface of the
次に、ソース電極およびドレイン電極として、Ti層131A、131B、Au層132A、132Bを順に蒸着する(図1(b))。
Next,
次に、試料を400℃でアニールを行い、Tiをダイヤモンドと反応させて、TiC層133A、133Bを形成する(図1(c))。最後に、ソース電極およびドレイン電極から空間的に離れたゲート部にAl2O3膜141を形成し、その上にAl層42をゲート電極として蒸着する(図1(d))。このように作製したダイヤモンドFETを動作させる場合の配線を図1(e)に示す。
Next, the sample is annealed at 400 ° C., and Ti is reacted with diamond to form
図3に、作製したダイヤモンドFETのドレイン電流特性を示す。本発明によるFETの特性は、ゲート電圧−3Vにおける最大ドレイン電流密度が600mA/mmとなり、従来技術による場合の約6倍に増加した。また、温度依存性に関しては、従来技術では室温から150℃付近でドレイン電流密度は急激に減少したが、本発明では900℃まで安定して動作した。 FIG. 3 shows the drain current characteristics of the fabricated diamond FET. The characteristics of the FET according to the present invention were 600 mA / mm at the maximum drain current density at a gate voltage of −3 V, which was about 6 times that of the conventional technique. Regarding the temperature dependency, the drain current density rapidly decreased from room temperature to around 150 ° C. in the prior art, but in the present invention, it stably operated up to 900 ° C.
図4に、ダイヤモンド薄膜層102の厚さを変えた時のシートキャリア濃度を示す。膜厚が1〜5nmの範囲にあるとき、シートキャリア濃度は1×1014cm-2以上あり、良好な特性を示すことが分かった。図5に、ホウ素原子濃度に対するシート正孔濃度を示す。2×1020から3×1021cm-3のときに、シート正孔濃度は1×1014cm-2以上を示し、良好であることが分かった。また、図6に、ダイヤモンド薄膜層の温度依存性を示す。従来技術では温度上昇に従いシート正孔濃度が急激に減少するが、本発明ではほぼ1×1014cm-2で安定している。
FIG. 4 shows the sheet carrier concentration when the thickness of the diamond
以上、説明してきたように、ホウ素濃度が2×1020cm-3以上3×1021cm-3以下であり、膜厚が1nm以上5nm以下であるダイヤモンド薄膜は、シートキャリア濃度および移動度が良好な値をとる。そして、このようなダイヤモンド薄膜をFETのチャネル層として用いることにより、図3を参照して説明したように、ドレイン電流特性に大幅な改善が見られる。最大ドレイン電流密度が大幅に増大する上、温度特性も安定するため、実用化可能なダイヤモンドFETを作製することができる。 As described above, a diamond thin film having a boron concentration of 2 × 10 20 cm −3 or more and 3 × 10 21 cm −3 or less and a film thickness of 1 nm or more and 5 nm or less has a sheet carrier concentration and mobility. Take good value. By using such a diamond thin film as the channel layer of the FET, as described with reference to FIG. 3, the drain current characteristic is greatly improved. Since the maximum drain current density is greatly increased and the temperature characteristics are stabilized, a practically usable diamond FET can be manufactured.
図7に、TiC層133A、133BとTi層131A、131Bがなく、Au層132A、132Bのみがある従来技術に相当する場合((a))と、Au層132A、132Bに加えてTiC層133A、133B及びTi層131A、131Bがある本発明の場合((b))のソース・ドレイン電極間の電流電圧特性を示す。本発明の場合の方が明らかに電流値が高く、抵抗が低いことが分かった。
FIG. 7 shows a case in which the
101 ダイヤモンド結晶層
102 ダイヤモンド薄膜層
131A、131B Ti層
132A、132B Au層
133A、133B TiC層
141 Al2O3膜
142 Al層
101
Claims (2)
前記ダイヤモンド結晶層上のチャネル層と、
前記チャネル層上のソース電極、ドレイン電極およびゲート電極と
を備え、
前記チャネル層は、ホウ素濃度が2×10 20 cm -3 以上3×10 21 cm -3 以下であり、膜厚が1nm以上5nm以下であるダイヤモンド薄膜で構成されており、
前記ゲート電極と前記チャネル層との間にAl 2 O 3 層を備えることを特徴とする電界効果トランジスター。 A diamond crystal layer;
A channel layer on the diamond crystal layer;
A source electrode, a drain electrode and a gate electrode on the channel layer;
The channel layer is composed of a diamond thin film having a boron concentration of 2 × 10 20 cm −3 to 3 × 10 21 cm −3 and a film thickness of 1 nm to 5 nm .
A field effect transistor comprising an Al 2 O 3 layer between the gate electrode and the channel layer .
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