JP5712794B2 - Gate timing control circuit - Google Patents

Description

  The present invention relates to a device in which two or more semiconductor switches typified by IGBTs are connected in series to increase the apparent switch element withstand voltage, and more particularly to a semiconductor power conversion device such as a high-voltage, large-capacity inverter.

  When the semiconductor power converter is increased in voltage, the output voltage is limited by the breakdown voltage of the semiconductor switch. The breakdown voltage of the semiconductor switch has a physical limit. For example, the limit of what is currently marketed in the IGBT is about 6500V. However, there is a need for a high-breakdown-voltage semiconductor switch due to the fact that a higher voltage exists in the system voltage and that it is desired to perform a direct switching operation without using a transformer in order to improve the efficiency of the semiconductor power converter. It has been.

  In order to increase the pressure of a semiconductor power conversion device, a technology for increasing the apparent withstand voltage of a semiconductor switch by connecting two or more semiconductor switches in series and simultaneously performing a switch operation is known (for example, patents). Reference 1).

  Here, the above technique will be briefly described with reference to Patent Document 1.

During the change of the switching operation in the semiconductor switch or at the time of turn-off, all Vce (voltage load Uce in Patent Document 1) is unbalancedly distributed in each semiconductor switch due to the parameter difference. Therefore, in Patent Document 1, Vce of each semiconductor switch connected in series (in Patent Document 1, voltage loads Uce1, Uce2,..., UceN) are measured, and the following (1) and (2) are performed. Thus, the voltage distribution (voltage sharing) between the semiconductor switches is controlled to be equal.
(1) Based on the measured Vce (voltage load Uce1), the operation timing of the semiconductor switch (switching instants Tdon, Tdoff) is determined.
(2) The magnitude of the gate voltage (control voltage level) is determined based on the measured Vce (voltage load Uce1).

Japanese Unexamined Patent Publication No. 7-241080 (paragraphs [0007] to [0013])

  Unless the operation timing of the semiconductor switches is determined so that the voltage distributions (voltage sharing) of the semiconductor switches connected in series are equal, an imbalance occurs in the voltage sharing between the semiconductor switches.

  In Patent Document 1, as shown in FIG. 8, a method is employed in which Vce of each semiconductor switch is detected and the imbalance of the voltage burden is observed at the timing when the surge voltage after the turn-on and turn-off operations of the semiconductor switch is settled. ing.

  However, since the convergence time of the surge voltage differs depending on the semiconductor switch, load current, temperature, surge voltage waveform, etc. depending on the main circuit configuration, it is necessary to adjust the operation timing of the semiconductor switch for each device, and the time required for development is long. There was a problem of becoming.

  Further, for example, in the inverter device, when a semiconductor switch of any phase is switched, the DC voltage fluctuates, so that Vce cannot be detected. For this reason, during the fluctuation period of the DC voltage, the semiconductor switches of other phases cannot be turned on and off, and the output control performance is limited (decreased).

  As described above, a gate that equalizes the voltage sharing of each semiconductor switch without adjusting the operation timing of the semiconductor switch in accordance with the semiconductor switch, load current, temperature, surge voltage waveform depending on the main circuit configuration, etc. Providing a timing control circuit is an issue.

  The present invention has been devised in view of the conventional problems, and one aspect thereof is a gate timing control circuit for adjusting the timing of gate signals output to a plurality of semiconductor switches connected in series, Comparing Vce detection of each semiconductor switch with a preset threshold value and outputting a Vce signal indicating the rising timing in Vce detection, and timing of change of each Vce signal based on the gate signal And a time difference control unit that outputs a gate output generated so as to be matched to the gate driver.

A time difference detection unit that detects a time difference in timing when Vce detection reaches a threshold value based on a deviation of Vce signals of two semiconductor switches among the plurality of semiconductor switches connected in series , and outputs the difference as an adjustment width is provided. The time difference control unit outputs to the gate driver a gate output generated based on the gate signal and the adjustment width so that the timing of change in each Vce signal matches.

  Further, in the time difference control unit, each semiconductor device is configured so that the change timing in each Vce signal matches the target timing based on the time difference between the change timing in the Vce signal and a predetermined target timing. It is characterized in that the gate output of the switch is individually generated and output to the gate driver.

  According to the present invention, it is possible to equalize the voltage sharing of each semiconductor switch without adjusting the operation timing of the semiconductor switch in accordance with the semiconductor switch, load current, temperature, the surge voltage waveform due to the main circuit configuration, and the like. It becomes possible.

1 is a configuration diagram showing a semiconductor power conversion device using a gate timing control circuit in Embodiment 1. FIG. 3 is a graph illustrating Vce detection and a Vce signal in the first embodiment. 3 is a graph illustrating an example of a gate signal, a gate output, and a Vce signal in the first embodiment. 6 is a graph illustrating another example of a gate signal, a gate output, and a Vce signal in the first embodiment. It is a block diagram which shows the semiconductor power converter device using the gate timing control circuit in Embodiment 2. 6 is a graph illustrating an example of a gate signal, a gate output, and a Vce signal in the second embodiment. It is a block diagram which shows the semiconductor power converter device using the gate timing control circuit in Embodiment 3. 10 is a graph showing the detection timing of Vce in Patent Document 1.

  In Patent Document 1, Vce is detected at the timing when the surge voltage after the on / off operation in the semiconductor switch is settled, and the operation timing of the semiconductor switch is determined so that the voltage distribution (voltage sharing) of each semiconductor switch becomes equal. . On the other hand, the present invention determines the operation timing of the semiconductor switch based on the time when the Vce detection reaches the threshold value (set level), prevents the on / off operation timing shift in the gate signal, and distributes the voltage in the semiconductor switch. This is to suppress the unbalance of.

  Hereinafter, the gate timing control circuit in Embodiments 1-3 of this invention is demonstrated in detail based on drawing.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a semiconductor power conversion device using a gate timing control circuit according to the first embodiment.

  As shown in FIG. 1, the semiconductor power conversion device 1 includes semiconductor switches (for example, IGBTs) A and B, a gate driver 2, and a gate timing control circuit 3.

  The semiconductor switches A and B are connected in series, and two resistors R1, R2 and R3, R4 connected in series are connected in parallel to the semiconductor switches A and B, respectively. An intermediate connection point between the two resistors R1, R2 and R3, R4 is connected to input terminals of comparators 4, 4 described later.

  The gate driver 2 includes transistors Q1, Q2, Q3, Q4, power supplies E1, E2, E3, E4, resistors R5, R6. Since the gate driver 2 is a general one, description thereof is omitted here.

  The gate timing control circuit 3 includes comparators 4 and 4, insulators 5 and 5, a subtractor 6, a time difference detection unit 7, a time difference control unit 8, insulators 9 and 9, and diodes 10 and 10. .

  A threshold value is input to the other input terminal of the comparator 4, Vce detection (A), (B) is compared with the threshold value, and the result is obtained as an Vce signal (A), (B) as an insulator ( For example, it is output to the subtracter 6 via the photocouplers 5 and 5. The Vce signals (A) and (B) are logic signals. In the following description, the Vce detection (A) and (B) is “1” when the threshold is larger than the threshold value, and “0” when the Vce detection is smaller. The subtractor 6 calculates a deviation between the two Vce signals (A) and (B), and outputs the calculated deviation to the time difference detection unit 7. Based on the deviation, the time difference detection unit 7 detects a time difference in timing when the Vce detections (A) and (B) reach the threshold value, and outputs the time difference to the time difference control unit 8 as an adjustment width. The time difference control unit 8 receives a gate signal, generates gate outputs (A) and (B) based on the gate signal and the adjustment width, and passes through the insulators 9 and 9 and the diodes 10 and 10. , Output to the gate driver 2.

  The threshold for detecting Vce only needs to detect a time difference. Therefore, it is necessary to satisfy at least “total voltage / number of semiconductor switches related to a plurality of semiconductor switches> threshold value at turn-off”, but it can be set as appropriate.

  Next, a specific control method of the gate timing control circuit 3 will be described.

  Deviations in the timing at which the plurality of semiconductor switches A and B are turned on and off are caused by variations in the gate driver 2 and the gate capacitance.

  Therefore, the rising timing of Vce detection by the turn-off operation of the semiconductor switches A and B is measured, and the timing of the gate outputs (A) and (B) (timing at which the command changes) is adjusted so that the rising timing is matched. This suppresses an imbalance in voltage sharing between the semiconductor switches A and B.

  FIG. 2 is a graph showing Vce detection (A), (B) and Vce signals (A), (B) in the first embodiment. As shown in FIG. 2A, the time difference detector 7 detects the time difference between the Vce signals (A) and (B) and determines the adjustment range. Then, as shown in FIG. 2B, the gate output (A) is controlled by the time difference control unit 8 so that the timings of changes of the Vce signals (A) and (B) are matched based on the gate signal and the adjustment width. , (B). This adjustment range is maintained, and the operation is continued with this adjustment range. If a time difference occurs in the same adjustment range and the timing of changes in the Vce signals (A) and (B), the adjustment range in the next switching is changed. Note that it may be changed gradually by applying PI control or the like.

  FIG. 3 is a graph showing gate signals, gate outputs (A) and (B), and Vce signals (A) and (B) in the first embodiment. 3A is before time difference control, FIG. 3B is after time difference control (when the gate output with the earlier Vce signal is delayed), and FIG. 3C is after time difference control (with the slower Vce signal). This is a graph showing a case where the gate output is accelerated.

  As shown in FIG. 3A, before the time difference control, the gate signal and the gate outputs (A) and (B) have the same waveform. In the example of FIG. 3A, the Vce signal (B) rises with a delay after the Vce signal (A) rises. Then, the time difference detection unit 7 detects the time difference between the timings of change (rise) of the Vce signal (A) and the Vce signal (B) as the adjustment width.

  When the gate output with the earlier Vce signal is delayed, the time difference control unit 8 delays the gate output (A) by the adjustment width as shown in FIG. In the case of FIG. 3B, the gate output (B) is left as it is. As a result, the timings of change (rise) of the Vce signal (A) and the Vce signal (B) are matched.

  When the gate output with the slower Vce signal is advanced, the gate output (B) is advanced by the time difference control unit 8 by the adjustment width as shown in FIG. In the case of FIG. 3C, the gate output (A) is left as it is. As a result, the timings of change (rise) of the Vce signal (A) and the Vce signal (B) are matched.

  However, in order to advance the gate output earlier than the gate signal, it is necessary to adopt a method of “a gate signal that is the source of the gate signal being created at an earlier time” or “predicting a change in the gate signal”.

  However, since the above method is difficult, the method shown in FIG. 4 can be considered. Hereinafter, a description will be given with reference to FIG.

  As shown in FIG. 4A, the gate outputs (A) and (B) are delayed in advance with respect to the gate signal. Then, the time difference detection unit 7 detects the rising time difference between the Vce signal (A) and the Vce signal (B) as an adjustment width. Next, as shown in FIG. 4B, the time difference control unit 8 adjusts the time difference between the gate outputs (A), (B), or both by the adjustment width.

  In FIG. 4B, control is performed such that the Vce signals (A) and (B) rise in the middle of the rise timing of the Vce signals (A) and (B). Then, as shown in FIG. 4B, when the time a [sec] from arbitrary timing t0 to ta and the time from t0 to tb is b [sec], the time becomes (a + b) / 2. The gate output (A) is delayed and the gate output (B) is advanced so that the Vce signals (A) and (B) rise. In FIG. 4B, the delay time and the advance time are made equal, but they may not be equal.

  As described above, according to the gate timing control circuit 3 in the first embodiment, by measuring the rising timing of the Vce detection (A) and (B) and adjusting the gate outputs (A) and (B). The voltage sharing for each switching element can be equalized.

  In addition, since control is performed based on the time difference of the change (rise) timing of the Vce signals (A) and (B), the semiconductor device does not depend on the semiconductor switch, load current, temperature, main circuit configuration, etc. There is no need to adjust the switch operation timing. Therefore, it is possible to shorten the time required for developing the device.

  Furthermore, any DC voltage can be applied to the semiconductor switches A and B. Further, for example, in the case of an inverter, even if a DC voltage fluctuates due to switching of a semiconductor switch, there is no effect on the gate timing control circuit 3 of the first embodiment. It is possible to suppress a decrease in output control performance.

[Embodiment 2]
In the gate timing control circuit 3 according to the first embodiment, when the number of semiconductor switches is two or more in series, the calculation becomes complicated and the calculation load increases. Further, as the number of semiconductor switches in series increases, the calculation load becomes more significant.

  Therefore, in the second embodiment, gate timing control is performed by delaying each gate output longer than the expected maximum delay of the Vce signal, and gate timing control is performed individually for each semiconductor switch, so that the number of semiconductor switches in series is increased. Independent gate timing control is realized.

  FIG. 5 is a block diagram showing a configuration of the semiconductor power conversion device 11 using the gate timing control circuit 13 in the second embodiment. Since the semiconductor switches A and B and the gate driver 2 have the same configuration as that of the first embodiment, description thereof is omitted, and only the gate timing control circuit 13 will be described.

  In the gate timing control circuit 13 of the second embodiment, the subtractor 6 and the time difference detector 7 in the first embodiment are omitted, and instead, a time difference control unit 8 is provided for each gate output (A), (B). ing.

  In the second embodiment, the gate timing control circuit 13 compares the Vce detection (A) and (B) with the threshold value by the comparators 4 and 4, and the result is isolated as the Vce signals (A) and (B). It is output to the time difference control units 8 and 8 via the devices 5 and 5. A gate signal is input to the time difference control units 8 and 8, and the gate output (A ) And (B) are generated and output to the gate driver 2 through the insulators 9 and 9.

  The gate timing control circuit 3 according to the first embodiment detects a time difference between the Vce signal (A) and the Vce signal (B), and performs time difference control based on the time difference (adjustment width). The control circuit 13 detects a time difference between a predetermined target timing and a change (rise) timing in the Vce signals (A) and (B), and performs time difference control based on the time difference (adjustment width). is there.

  The target timing indicates a point in time after a predetermined time has elapsed from the change of the gate signal (an arbitrary time defined in advance). That is, the gate outputs (A) and (B) are individually adjusted so that the change (rise) timing in the Vce signal matches the target timing determined in advance.

  FIG. 6 is a graph showing an example of gate signals, gate outputs (A) and (B), and Vce signals (A) and (B) in the second embodiment. FIG. 6A is a graph showing before time difference control, and FIG. 6B is a graph showing after time difference control.

As shown in FIG. 6A, before the time difference control, the gate outputs (A) and (B) with the gate signal have the same waveform. In the example of FIG. 6A, the Vce signal (B) rises slightly after the rise of the Vce signal (A), and the target timing is set after the rise of the Vce signals (A) and (B). Has been. The time difference between the rise timing of the Vce signal and the target timing is detected as an adjustment width. When the time difference control is performed, as shown in FIG. 6B, the gate outputs (A), ( Delay B) respectively. That is, the time difference (adjustment width) between the change (rise) timing of Vce (A) and (B) and the target timing is detected for each semiconductor switch, and the gate outputs (A) and (B) by the adjustment width. The gate timing control is performed. As a result, the changes (rise) of the Vce signals (A) and (B) are the same as the target timing and are matched.

  As described above, according to the gate timing control circuit 13 of the second embodiment, the same operational effects as those of the first embodiment can be obtained.

  In addition, by controlling the delay time for each semiconductor switch, it is possible to suppress an increase in calculation burden even if the number of semiconductor switches in series increases.

[Embodiment 3]
FIG. 7 is a configuration diagram showing the configuration of the semiconductor power conversion device 21 using the gate timing control circuit 23 in the third embodiment. Since the semiconductor switches A and B and the gate driver 2 have the same configuration as in the first and second embodiments, description thereof is omitted.

  The gate timing control circuit 23 according to the third embodiment includes comparators 4 and 4, insulators 9 and 9, time difference control units 8 and 8, and diodes 10 and 10.

  The Vce detections (A) and (B) are compared with threshold values by the comparators 4 and 4, and the results are output to the time difference control units 8 and 8 as Vce signals (A) and (B), respectively. The gate signal is output to the time difference control units 8 and 8 through the insulators 9 and 9. In the time difference detectors 8 and 8, the gate signals are adjusted so that the Vce signals (A) and (B) are aligned with the target timing to generate gate outputs (A) and (B). Output to the gate driver 2.

  In the case of the second embodiment, since the insulator 5 is used for the detection block of the Vce signal, the Vce detection may vary depending on the insulator. Although depending on the control performance of the time difference control unit 8, the time difference control unit 8 can be arranged on the secondary side of the insulator 9. Thereby, the dispersion | variation in Vce detection can be suppressed.

  Since the time difference control unit 8 is arranged on the secondary side of the insulator 9, it is necessary to insulate when the timing difference of the Vce signal change in the two semiconductor switches is measured. Is not applicable.

  On the other hand, in the second embodiment, since the Vce signals are individually matched with the target timing, it is not necessary to compare the two Vce signals, and there is no need for insulation.

  As described above, according to the gate timing control circuit 23 in the third embodiment, the same operational effects as those in the first and second embodiments can be obtained.

  Furthermore, it is possible to suppress variations in the Vce signal due to the influence of the insulator.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, in the first to third embodiments, only the timing adjustment for the turn-off has been described in detail, but the present invention can also be applied to the turn-on timing adjustment.

  In the first to third embodiments, the gate driver 2 and the semiconductor switches A and B having a specific configuration have been described. However, the present invention is applicable as long as a plurality of semiconductor switches are connected in series.

DESCRIPTION OF SYMBOLS 1,11,21 ... Semiconductor power converter 2 ... Gate driver 3,13,23 ... Gate timing control circuit 4 ... Comparator 6 ... Subtractor 7 ... Time difference detection part 8 ... Time difference control part A, B ... Semiconductor switch

Claims (3)

A gate timing control circuit for adjusting the timing of gate signals output to a plurality of semiconductor switches connected in series,
A comparator that compares the Vce detection of each semiconductor switch with a preset threshold value and outputs a Vce signal indicating the rising timing in the Vce detection;
A time difference control unit that outputs a gate output generated to match the timing of change of each Vce signal based on a gate signal to a gate driver;
A gate timing control circuit comprising: A time difference detection unit that detects a time difference in timing when Vce detection reaches a threshold value based on a deviation of Vce signals of two semiconductor switches among the plurality of semiconductor switches connected in series , and outputs the difference as an adjustment width is provided. ,
In the time difference control unit,
2. The gate timing control circuit according to claim 1, wherein a gate output generated so that a change timing in each Vce signal matches based on the gate signal and an adjustment width is output to a gate driver. In the time difference control unit,
Based on the time difference between the change timing in the Vce signal and a predetermined target timing, the gate output of each semiconductor switch is individually generated so that the change timing in the Vce signal matches the target timing. 2. The gate timing control circuit according to claim 1, wherein the gate timing control circuit outputs the signal to a gate driver.

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