JP5711805B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for reducing defects from an active layer of a semiconductor device is provided. An active layer is a part of a semiconductor in a device, and the active layer is defined by a separation structure at least in a lateral direction, and is physically connected to this by means of a connection interface. Forming a stress-inducing layer 4 adjacent on the common substantially flat surface and patterned on the common substantially flat surface, the stress-inducing layer 4 for inducing a stress field in the active layer The formed and induced stress field becomes a shear stress on the defects present in the active layer, which causes an annealing process to move the defects towards the connection interface and from the common substantially flat surface 23. The patterned stress-inducing layer 4 is removed. [Selection] Figure 3

Description

  The present invention describes a method for manufacturing a semiconductor device. In certain aspects, the present invention relates to a method of manufacturing an active layer of a semiconductor device, such as a channel layer of a transistor device that has reduced defects and improved characteristics.

  Heteroepitaxial growth in which a semiconductor material (eg SiGe or Ge) is grown on another semiconductor material (eg Si) results in defects such as dislocations due to, for example, lattice constant mismatch.

  Growth in a limited space, such as that performed using Aspect Ratio Trapping (ART) technology, is near the edge of the limited space (eg, toward shallow trench isolation (STI)). It is possible to reduce defects grown in the process. See, for example, “Study of the defect elimination mechanism in aspect ratio trapping Ge growth”, Bai, J. et al., Applied Physics Letters, Volume 90, Issue 10, id. 101902 (2007) ”. It is not a solution to reduce defects such as dislocations near the center of the device or active device layer, especially the presence of defects such as dislocations in the active device layer such as the channel layer of transistor devices, There are concerns with FiNFETs and similar devices where high mobility channel material is integrated into a Si wafer.

  The object of the present invention is to provide a method for reducing defects, such as dislocations, from at least one active layer, the active layer being part of the semiconductor in the device, At least laterally defined by the isolation structure and physically connected to it by means of a connection interface, the isolation structure and the active layer are adjacent on a common substantially flat surface.

This object is achieved by the invention using the method showing the technical features of the first independent claim. That is,
A patterned stress-inducing layer is formed on a common substantially flat surface, the stress-inducing layer being provided to induce a stress field in the active layer, the induced stress field being in the active layer It becomes a shear stress against defects such as dislocations existing in
After forming a patterned stress-inducing layer on a common substantially flat surface, an annealing process is performed,
This induces defects like dislocations to move towards the connection interface, and
The patterned stress-inducing layer is removed from the common substantially flat surface.

  A feature of the present invention is that defects such as dislocations, for example, can be greatly reduced or completely removed from the active layer of a semiconductor device.

  A further feature of the present invention is that defects can be greatly reduced or completely removed from the central region of the active semiconductor device layer. The active device layer of a semiconductor device is a layer in which charge carriers flow from one electrode to the other, this flow being controlled essentially like a diode, or like the source and drain of a field effect transistor. It is clearly controlled so that the flow of charge is controlled by the gate. The active layer or stack of layers includes an electrically controllable material, such as a semiconductor material, and provides an electrical function, such as a diode characteristic, or its electrical conductivity is modulated by a control electrode, such as a gate. be able to.

  For the purposes of the present invention, dislocations are crystallographic line defects or irregularities in the crystal structure. A more detailed description of the invention can be obtained, for example, from the book “Introduction to Dislocations” by Derek Hull and D.J.Bacon.

  The actual stress required will depend on the device size, material, and annealing temperature. In a preferred embodiment, the internal stress in the patterned stress-inducing layer is between 100 MPa and 5 GPa. Both compressive and tensile stresses are used.

In a preferred embodiment of the present invention, the active device layer is a germanium layer or comprises germanium. It may be a SiGe layer. In preferred embodiments, the active layer is or includes Si _x Ge _1-x , where x is between 0 and 0.8, or between 0 and 0.7, or between 0 and 0.6. Or blue from 0 to 0.5, or from 0 to 0.4, or from 0 to 0.3, or from 0 to 0.2.

  In an alternative embodiment, the active device layer is a silicon layer or may include silicon. In alternative embodiments, the active device layer is or includes a III-V material such as GeSn alloy, GaN, GaAs, InAs, InSb, InP, ternary or quaternary III-V compounds. .

In a preferred embodiment of the present invention, the patterned stress-inducing layer comprises SiN. In embodiments of the present invention, patterned stress-inducing layer, SiN, _TiN, W, or a combination of _{SiO 2, HfO 2, Al 2} O 3, and mixtures such as hafnium silicate and / or hafnium aluminite Contains oxides.

  In a preferred embodiment of the invention, the thickness of the patterned stress-inducing layer is between 5 nm and 100 nm, more preferably between 10 nm and 30 nm.

  In a preferred embodiment, the method may further comprise forming at least one shielding layer between the patterned stress-inducing layer and the common substantially flat surface, the shielding layer comprising Shielding a portion of the stress field induced by the patterned stress-inducing layer, the stress field in the active layer is a defect (such as dislocation) in the active layer toward the bonding interface during the annealing process. Is the sign and size that contributes to the movement. One, two, or a plurality of shielding layers may be formed.

  By using at least one shielding layer, the stress field induced by the patterned stress-inducing layer in the active layer is, for example, more controlled in its direction and / or uniformity.

  By appropriately selecting at least one shielding layer and stress inducing layer, a substantially unidirectional shear stress field in a relevant portion of the active region is defined for a given active device layer in a given embodiment. Then, it can be formed substantially uniformly.

  In a preferred embodiment, the at least one shielding layer is a complete layer that is not patterned. The at least one shielding layer may preferably cover the entire surface of the underlying substrate.

  It can be seen that such a layer provides improved performance when compared to one or more patterned shielding layers.

  In a preferred embodiment, the at least one shielding layer comprises silicon oxide. The silicon oxide layer can be deposited by a CVD or ALD type process. Silicon oxide may also contain one or more other elements that affect the mechanical properties of the oxide, such as Young's modulus and stiffness, which affects the optimal film thickness of the oxide. To do. These other elements may include, for example, one or more of C, H, N, F.

In a preferred embodiment, the shielding layer may include a first deposition layer mainly containing Si and N, such as SiN, and a second deposition layer mainly containing Si and O, such as SiO _2. good.

  In a preferred embodiment, forming the patterned stress-inducing layer on a common substantially flat surface comprises forming an unpatterned stress-inducing layer and an unpatterned stress-inducing layer. And patterning by etching, wherein the shielding layer or the top layer of the shielding layers may be applied to serve as an etch stop layer for the patterning etch of the patterned stress-inducing layer.

  In a preferred embodiment, the combined total film thickness of one or more shielding layer (s) is between 5 nm and 50 nm.

  Film thicknesses within this range are shown to show the best performance. However, other film thicknesses are not excluded.

In a preferred embodiment, the patterned stress-inducing layer comprises / consists of a nitride layer, the upper shielding layer comprises / consists of SiO ₂ and the lower shielding layer comprises / consists of SiN.

For the purposes of the present invention, when referring to SiN layers or SiN stress-inducing layers, these layers mainly comprise silicon and nitrogen. The silicon nitride may be approximately Si ₃ N ₄ stoichiometry, but this may be different. These layers may further contain impurity elements such as C, H, O, for example, which is generally the case for films deposited by industrial standard chemical vapor deposition techniques.

  In a preferred embodiment, the annealing step is performed at a temperature between 450 ° C. and 1100 ° C. In a preferred embodiment, the annealing step is performed at a temperature between 500 ° C. and 650 ° C.

  In a preferred embodiment, the time of the annealing process is selected to have a time that is approximately sufficient for defects such as dislocations to move to the bonding interface. This time is from one or more milliseconds to several hours, for example 6 hours. In general, a relatively long time is required at a relatively low temperature. This time is a function of the size of the active layer and the migration rate of typical defects or dislocations.

In a preferred embodiment, the method further comprises removing the patterned stress-inducing layer of SiN in an aqueous solution containing phosphoric acid, removing the top shielding layer in an aqueous solution containing hydrofluoric acid, Removing the lower shielding layer of SiN in an aqueous solution containing phosphoric acid. In a specific embodiment, two shielding layers (SiO _x / SiN) are combined with a patterned stress-inducing layer of SiN. The top shielding layer (SiO _x ) is formed as an etch stop for the patterned stress-inducing layer of SiN.

The lower shielding layer (SiN) is formed as an etch stop for the upper shielding layer SiO ₂ and protects the underlying isolation oxide. Finally, the SiN bottom shielding layer is removed by hot etching in hot phosphoric acid.

In a preferred embodiment, the isolation structure comprises SiN _x . The isolation structure includes or consists of, for example, a shallow trench isolation structure (STI structure). The STI structure includes or consists of silicon oxide.

  In a preferred embodiment, the common flat surface is prepared by chemical mechanical polishing.

  In a preferred embodiment, the step of forming the patterned stress-inducing layer includes the step of forming the stress-inducing layer and the step of patterning the stress-inducing layer, and the patterning step of the patterned stress-inducing layer is active. A common substantially flat surface feature having a boundary substantially parallel to the layer boundary is defined.

  Their substantially parallel boundaries are at a close distance, for example within a distance of less than 30 nm, from the boundary of the active layer.

  In another aspect, the protrusions of the patterned stress-inducing layer on the common substantially flat surface define a boundary that is at least partially parallel or substantially parallel to the boundary of the active layer. This substantially parallel boundary is located at a close distance, such as within a distance of less than 30 nm from the boundary of the active layer. The protrusion is preferably a protrusion perpendicular to the common main surface. The protrusion may be a protrusion perpendicular to the main surface of the underlying substrate.

  The patterned stress inducing layer may form a plurality of stress inducing structures. Some of these structures are connected with other stress-inducing structures. It is understood that for the connected stress-inducing structures, their respective stress fields are dependent. Some of these structures are not connected to other stress-inducing structures. The patterned stress-inducing layer may form a plurality of unconnected structures. It is understood that for stress-inducing structures that are not connected, each stress field is substantially independent.

  Advantageously, the stress-inducing layer, or each stress-inducing structure, is formed at a location close to the boundary of the active device layer, giving the best effect. In a preferred embodiment, the stress-inducing layer, or stress-inducing structure, forms a protrusion boundary whose boundary is parallel to the active device layer boundary. It will be appreciated that the active device layer may be the channel layer of a transistor device. The transistor device may be a planar type or a non-planar type. Non-planar type transistor devices may be, for example, FINFET types or similar types of transistors known to those skilled in the art. It generally has an elongated shape. The protruding boundaries of the active device layer on a common major surface, or on the major surface of the virtual substrate, can be, for example, a rectangle, a rounded rectangle, an ellipse, or any other shape known to those skilled in the art as appropriate. Have.

  The protruding boundaries of the patterned stress-inducing layer may be substantially parallel to, or at least partially substantially parallel to, the respective boundaries of the active device layer, eg, the active device layer, such as the channel layer length A plurality of parallel portions having a length corresponding to the length may be included.

  In a preferred embodiment, adjacent protruding substantially parallel boundaries of the patterned stress inducing layer are located within a distance of less than 30 nm from different adjacent adjacent channel layers.

  This provides the advantage that the alignment requirements are relatively relaxed as described below. Adjacent channel regions (eg, active device layers) may be considered to have a substantially rectangular shape with elongated protrusions and the boundaries of several or different channel regions along the length are parallel. . One stress-inducing structure (eg, the protrusions are rectangular) may be provided and function on the longitudinal boundaries of different adjacent channel regions. Adjacent protruding substantially parallel boundaries of the patterned stress-inducing layer are located within a close distance, eg, within a distance of less than 30 nm, from different adjacent adjacent channel layers, while 1 The two stress-inducing structures may themselves extend beyond at least one of the adjacent channel regions. The stress-inducing structure may thus have a width equal to or greater than the distance between two adjacent active channel regions. The stress-inducing structure may have a width that is greater than the combined width of two adjacent channel regions and the distance between them (ie, the distance between two adjacent channel regions). “Closeness” requirements are given independently to each boundary, such as the requirement to be within a range of, for example, less than 30 nm from the boundary of the channel region and the stress-inducing layer / stress-inducing structure. Furthermore, deviations within this range do not substantially affect the effectiveness of the method according to the present embodiment.

  In a preferred embodiment, the patterned stress-inducing layer is formed over the isolation structure, such as an STI structure. In a preferred embodiment, the patterned stress-inducing layer is formed at least partially over the active region, for example at least partially overlapping the active region.

  In a preferred embodiment, the stress inducing structure extends over at least two adjacent active layers.

In a further embodiment of the invention, a method according to some of the previous embodiments is further provided:
A patterned stress-inducing layer is formed on a common substantially flat surface, the stress-inducing layer being applied to induce stress on the active layer, and the induced stress is introduced into the active layer A process that results in shear stress on existing defects such as dislocations;
An annealing process;
Removing the patterned stress-inducing layer from the common planar surface, and one or more iterations.

  In a preferred embodiment, each patterned stress-inducing layer includes a different pre-patterned pattern, and the combination of stresses induced by successive stress-inducing layers can cause defects such as dislocations at the connection interface. Move towards.

  In a preferred embodiment, the method may further comprise performing a CMP process after the last iteration of removing the patterned stress-inducing layer and (if applicable) optionally the shielding layer.

  In a preferred embodiment, the method may further comprise performing a CMP process after removal of the patterned stress-inducing layer or at each iteration thereof.

  In preferred embodiments, the methods may further include the step of removing the upper portion of the active layer. This provides the advantage that defects remaining in the upper part of the active layer can be effectively removed, for example due to excessively high stresses or stresses applied in the wrong direction. Thus, the remaining high crystal quality part of the active layer is obtained for device fabrication.

  For the purposes of the present invention, it is intended to disclose those ranges in closed, open, and two half-opened forms whenever the ranges are determined.

  The invention is further illustrated by means of the following description and the attached drawings.

Shows the processed wafer of a standard shallow trench isolation module The 1st example of this invention is shown. The further example of this invention is shown. The further example of this invention is shown. The simulation result which supports the specific example of this invention is shown. The simulation result which supports the specific example of this invention is shown. The simulation result which supports the specific example of this invention is shown. The simulation result which supports the specific example of this invention is shown. The simulation result which supports the specific example of this invention is shown. The specific example concerning this invention is shown. The specific example concerning this invention is shown. The specific example concerning this invention is shown.

  The present invention will be described with respect to particular embodiments and with reference to certain drawings but is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements are enlarged for illustrative purposes and are not drawn to scale. The dimensions and relative dimensions need not correspond to actual reductions in the practice of the invention.

  Furthermore, terms such as first, second, third, etc. in the description and claims are used to distinguish between similar elements and need not describe an order or a chronological order. The terms are interchangeable in appropriate contexts and embodiments of the invention can operate in other orders than those described or illustrated herein.

  Further, terms such as up, down, up, down, etc. in the description and claims are used for illustrative purposes and do not require a relative position. The terms so used are interchangeable under appropriate circumstances, and the invention described herein can operate in a different location than that described or illustrated herein.

  Further, the various embodiments referred to as “preferred” are to be construed as illustrative means by which the present invention can be practiced, rather than limiting the scope of the invention.

  The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, features, numbers, steps, or ingredients referred to are construed accordingly and exclude the presence or addition of one or more other features, numbers, steps, or ingredients, or combinations thereof. must not. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices comprising only components A and B; rather, for the present invention, the device configurations listed below: The elements are simply A and B, and the claims should be construed to include equivalents of those components.

  FIG. 1 shows a schematic wafer cross-section after a standard shallow trench isolation flow. This is because, for example, in a base substrate 1 such as a silicon substrate, a dielectric layer 2 formed on the first main surface of the base substrate 1 such as a silicon oxide layer, and a dielectric layer connected to the base substrate A set of three active lines. The active lines are electrically isolated from each other by means of part of the dielectric layer 2. At this point in the process flow, the active line 3 is typically made of the same material as the base substrate, which is typically Si.

  FIG. 2 discloses a process flow according to an embodiment of the present invention. In the active line 3 of FIG. 1, a recess is formed by etching silicon in a trench, for example. Next, selective epitaxial growth of germanium or silicon germanium is performed in the trench to form the layer or structure of the active device region 30. Optionally, an annealing step may be performed. A planarization step, such as a CMP (Chemical Mechanical Polishing) step, is performed to remove SiGe (or Ge) overgrowth over the trench openings and form a flat surface 23, which is Seen as a common substantially flat surface for the active device layer or active layer. For illustration purposes, one threading dislocation line 31 is shown for each active device region 30.

  Next, the stress inducing layer 4 is formed on the common flat surface 23. For example, a stressed SiN layer or film may be deposited. Next, the stressed SiN layer is patterned using standard lithography and etching techniques.

  Next, an annealing step is performed at a temperature sufficient for the threading dislocations 31 to move toward the interface 32 between the active region or layer 30 and the isolation structure 2. However, the annealing temperature should not be so high that the patterned stress-inducing layer is excessively relaxed. A typical annealing temperature is between 450 ° C. and 1100 ° C. and depends on the shape of the structure and the composition of the active line. Next, the patterned stress-inducing layer is removed or removed by etching means using hot phosphoric acid, for example, for the SiN stress film. Optionally, a planarization step such as a CMP process may be performed to remove the shape and damage from the inserted step. Next, standard downstream processing may be performed.

  In FIG. 3, a further embodiment is described, in which a single shielding layer 5 is formed between the stress-inducing layer 4 and a common substantially flat surface 23. The shielding layer may be, for example, silicon oxide or silicon nitride, and may include these.

  In FIG. 4 a further embodiment is described, in which a plurality of shielding layers, for example two shielding layers 51, 52, are interposed between the stress-inducing layer 4 and a common standard flat plane 23. It is formed.

  In FIG. 5, for example, simulation results showing the nature of the shear stress field induced by the stress-inducing layer 4 corresponding to FIG. 4 are described. Here, the germanium active layer 30 in the silicon oxide dielectric layer 2 is stress-induced by an internal stress of 2 Pa by a 20 nm-thickness stress inducing layer made of silicon nitride. The first shielding layer 51 includes silicon nitride and has a thickness of 10 nm. The second shielding layer 52 contains silicon oxide and has a thickness of 10 nm.

  The shielding layer shields a part of the stress field, and the supplemental portion in the active layer 3 is in a shear stress state having a large and constant sign (in this case, negative). Since the sign of the applied shear stress determines the direction in which the dislocation moves, having a substantially constant sign in the depth direction of the active layer is the same direction along the depth of the active line (left Ensure that the dislocation moves consistently (depending on the Burgers vector of the dislocation, either right).

The shielding layers 51, 52 (eg, SiO ₂ , SiN) under the stress-inducing layer 4 are not patterned and better “absorb” the sign of the upper part of the shear stress, for the shear stress in the active layer. Only one code is allowed. The active layer may be a fin of a transistor device, for example for a FINFET device.

  In a preferred embodiment, the total thickness of the shielding layer is about 20 nm, which may be sufficient, but may be thicker or thinner than 20 nm. FIG. 6 shows the same conditions as FIG. 5 except that the shielding nitride is thinned to 5 nm and the total thickness of the shielding layer is 15 nm. Before the stress-inducing layer, the first shielding layer 51 containing silicon nitride is deposited, and then the second shielding layer 52 containing silicon oxide is deposited, so that the silicon oxide becomes the stress-inducing layer. It becomes an etch stop for removal, and the silicon nitride protects a dielectric layer such as STI, while it becomes an etch stop for removal of the shielding oxide.

  FIG. 7 shows the simulation results under the same conditions as FIG. 5 except that there is no 10 nm shielding oxide and 10 nm shielding nitride. Here, large values of positive and negative shear stress are observed in the active layer, for example the channel layer 30. The removal of the shielding layer causes shear stress to be induced in the deeper, lower part of the active layer, and the direction of the shear stress in the upper or upper part of the active layer is different from the direction in the rest of the line. In certain embodiments of the invention, the method may further comprise removing this upper portion of the active layer. This portion can be removed by etching or polishing (for example, CMP).

  Optionally, the upper part of the active layer may be replaced with a different material, i.e. a new upper part may be formed on the lower part. Different materials include, for example, high mobility channel materials with high electron mobility and / or hole mobility. Removal is performed, for example, after removal of the stress-inducing layer, or after removal of the shielding layer, if present.

  Preferably, the mask boundary of the stress-inducing layer 4 with the patterned shielding layers 5, 51, 52 is formed on the active layer (eg on the fin), eg photolithography registration error Characteristically, small deviations due to errors) are not substantially affected. The alignment of each boundary of the stress inducing layer 4 with the interface 32 is shifted to the right by 10 nm in FIG. 8 compared to FIG.

  The conditions are the same as in FIG. The stress field in the Ge active layer is the same despite the 10 nm shift in photolithography drawing.

FIG. 9 further shows a simulation result of an example using a single unpatterned shielding layer, where the shielding layer is unpatterned silicon oxide. Here, the conditions are the same as those used in FIG. 5 except that a single 20 nm SiO ₂ shielding layer is used. Again, the magnitude of the shear stress in the Ge layer is the same as in FIG.

  In FIGS. 10, 11 and 12, different embodiments of the present invention are described, where different relative orientations and dimensions of the stress-inducing layer 4 and the active layer or region 30 are considered. Is done. In FIG. 10, the shear stress is maximized in the active layer 30, which causes the stress inducing layer (or layer structure) 4 to partially overlap two adjacent active layers or regions 30. Thereby, the boundary of the stress inducing layer 4 is arranged, for example, in the center of each active layer 3.

  In FIG. 11, the stress-inducing layer (or layer structure) 4 completely overlaps two adjacent active layers or regions 30. Such an overlap is asymmetric with respect to the active layer 3.

  FIG. 12 describes a further embodiment, in which the stress-inducing layer 4 is formed only between the active layers, i.e. only on the isolation or dielectric layer.

  A common point between the embodiments described in FIGS. 10, 11 and 12 and other embodiments is the problem of optimizing the limitations of lithography, integration, and reduction of dislocations.

  One skilled in the art will appreciate that the annealing process can be performed for a suitable time in a predetermined process. This is based, for example, on the material and dimensions of the active layer, the material system used, the magnitude of the induced shear stress, and the annealing temperature.

  Background information is described, for example, in “Velocities of Individual Dislocations in Germanium”, Journal of Applied Physics, 42, 3298-3303 (1971) (“PATEL”) by J.R.Patel and P.E.Freeland.

Table 1 was based on the “PETEL” model and data. Figure 7 shows dislocation rate calculations in germanium at temperatures of 500 ° C and 580 ° C. Here, v = v ₀ (tau / tau ₀ ) ^m is used. In the equation, v is the dislocation speed, tau is the extinguished stress field, v ₀ , tau ₀ , and m are fitting parameters. The values of V ₀ , tau ₀ , and m depend on the temperature and material. For example, at 500 ° C., a dislocation transfer rate of 1 nm / s is achieved with a shear stress of about 1.5 MPa on germanium. In the same material system, at the temperature of 580 ° C., the same dislocation transfer rate of 1 nm / s can be achieved only with a shear stress of 50 kPa.

Claims (13)

A method of reducing defects from at least one active layer, wherein the active layer is part of a semiconductor in the device and is a germanium-containing layer, the active layer is defined at least in a laterally isolated manner, and are physically connected in the connection and separation structure interface, the isolation structure and the active layer adjacent to each other on a common substantially planar surface, the method,
Forming at least a stress-inducing layer patterned on the active layer, the stress-inducing layer being formed to induce a stress field in the active layer, wherein the induced stress field is against defects present in the active layer; A process that becomes shear stress ;
Forming at least one shielding layer between the patterned stress-inducing layer and a common substantially flat surface, the shielding layer shielding a portion of the stress field induced by the patterned stress-inducing layer; A process formed into
Forming a patterned stress-inducing layer on at least the active layer , and then annealing .
This moves the defect towards the connection interface,
The stress field in the active layer is a sign and magnitude that moves defects in the active layer toward the connection interface during the annealing process , and
Comprising the step, of removing the patterned stress inducing layer from a common substantially planar surface.   The method of claim 1, wherein the patterned stress-inducing layer comprises SiN.   The method according to claim 1 or 2, wherein the patterned stress-inducing layer has a thickness between 5 nm and 100 nm.   The method according to claim 1, wherein the at least one shielding layer is a complete layer that is not patterned.   The method according to claim 1, wherein the at least one shielding layer comprises silicon oxide. The at least one shielding layer includes a first deposition layer containing mainly Si and N such as SiN, and a second deposition layer containing mainly Si and O such as SiO _2. The method in any one of.   Forming the patterned stress-inducing layer on the common substantially flat surface includes forming an unpatterned stress-inducing layer and patterning the unpatterned stress-inducing layer by etching, the shielding layer The method of any of claims 1-6, wherein the top layer of the plurality of shielding layers is formed to provide an etch stop for an etch that patterns the patterned stress-inducing layer.   The method according to claim 1, wherein the total film thickness of the at least one shielding layer is between 5 nm and 50 nm. Patterned stress-inducing layer comprises SiN layer or an SiN layer, the upper shielding layer is made of comprises a SiO ₂ / or SiO _2, the lower shielding layer according to claim 1 consisting comprises / or SiN and SiN 9. The method according to any one of 8. The method according to claim 1, wherein the active layer is a Si _x Ge _1-x containing layer, and x is between 0 and 0.8.   The method according to claim 1, wherein the annealing step is performed at a temperature between 450 ° C. and 1100 ° C.   The step of forming the patterned stress-inducing layer includes the step of forming the stress-inducing layer and the step of patterning the stress-inducing layer, and the patterning step of the patterned stress-inducing layer is substantially at the boundary of the active layer. 12. A method according to any preceding claim, wherein the shape is defined on a common substantially flat surface so as to have a boundary parallel to the surface.   The method according to claim 1, further comprising removing an upper portion of the active layer.

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