CN109671675B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109671675B
CN109671675B CN201710957393.9A CN201710957393A CN109671675B CN 109671675 B CN109671675 B CN 109671675B CN 201710957393 A CN201710957393 A CN 201710957393A CN 109671675 B CN109671675 B CN 109671675B
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isolation layer
forming
fin
temporary
groove
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CN109671675A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a temporary fin part and a pseudo fin part which protrude out of the substrate; forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the temporary fin part and the side wall of the pseudo fin part; removing the pseudo fin part, and forming a first groove in the first isolation layer; forming a second isolation layer which is filled in the first groove; removing the temporary fin part, and forming a second groove in the first isolation layer; forming a substitute fin part filled in the second groove, wherein the material of the substitute fin part is different from that of the temporary fin part; and removing part of the first isolation layer and the second isolation layer, wherein the top of the first isolation layer and the top of the second isolation layer are lower than the top of the substitute fin portion. The formation method can obtain the substitute fin part with good width uniformity, so that the electrical performance of the semiconductor structure can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has correspondingly continued to decrease. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and short-channel effects (SCE) are more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part at least from two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger channel control capability, and the short channel effect can be well inhibited.
Carrier mobility has an important influence on the electrical performance of the FinFET, and in order to improve carrier mobility, a new channel material is introduced to fabricate the FinFET, for example: and taking III-V group compound InGaAs as an NMOS channel material and taking compound SiGe as a PMOS channel material. FinFETs made of the novel channel material have higher carrier mobility and wide application prospect.
However, even with the introduction of new channel materials in the FinFET fabrication process, the electrical performance of prior art semiconductor structures is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can obtain a substitute fin part with good uniformity, thereby improving the electrical performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a temporary fin part and a pseudo fin part which protrude out of the substrate; forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the temporary fin part and the side wall of the pseudo fin part; removing the pseudo fin part, and forming a first groove in the first isolation layer; forming a second isolation layer which is filled in the first groove; removing the temporary fin part, and forming a second groove in the first isolation layer; forming a substitute fin part filled in the second groove, wherein the material of the substitute fin part is different from that of the temporary fin part; and removing part of the first isolation layer and the second isolation layer, wherein the top of the first isolation layer and the top of the second isolation layer are lower than the top of the substitute fin portion.
Optionally, the substitute fin portion is formed by a selective epitaxy process.
Optionally, before forming the substitute fin portion, the method further includes: and forming an epitaxial transition layer at the bottom of the second groove by adopting a selective epitaxial process.
Optionally, the material of the epitaxial transition layer is the same as the material of the substrate.
Optionally, the material of the epitaxial transition layer is the same as the material of the substitute fin, and the growth temperature of the epitaxial transition layer is lower than the growth temperature of the substitute fin.
Optionally, the material of the substitute fin portion is silicon germanium or indium gallium arsenide.
Optionally, the second isolation layer is formed first, and then the substitute fin portion is formed.
Optionally, the process of forming the second isolation layer includes: forming a second isolation film on the top of the first isolation layer, the top of the temporary fin part, the first groove and the top of the first groove; and removing the second isolation films positioned at the top of the first isolation layer, the top of the temporary fin part and the top of the first groove to form the second isolation layer.
Optionally, the second isolation film is formed by an atomic layer deposition process.
Optionally, the process step of forming the first groove includes: forming a first photoresist layer on the top of the first isolation layer and the top of the temporary fin part; etching the pseudo fin part by taking the first photoresist layer as a mask to form the first groove; and removing the first photoresist layer.
Optionally, the process step of forming the second groove includes: forming a second photoresist layer on top of the first isolation layer and on top of the second isolation layer; etching the temporary fin part by taking the second photoresist layer as a mask to form a second groove; and removing the second photoresist layer.
Optionally, the substitute fin portion is formed first, and then the second isolation layer is formed.
Optionally, the widths of the temporary fin portion and the dummy fin portion are the same; the temporary fin portion and the dummy fin portion have the same height.
Optionally, before the first isolation layer is formed, the temporary fin portions and the dummy fin portions are arranged in parallel on the substrate at equal intervals.
Optionally, the substrate includes an edge region and a central region surrounded by the edge region; wherein the dummy fin portion is located above the edge region, and the temporary fin portion is located above the central region.
Accordingly, the present invention also provides a semiconductor structure comprising: a substrate having a first isolation layer thereon; a second isolation layer located within and penetrating the first isolation layer; and the replacing fin part is positioned in the first isolation layer and penetrates through the first isolation layer, and the top of the replacing fin part is higher than the top of the first isolation layer and the top of the second isolation layer.
Optionally, an epitaxial transition layer is arranged between the bottom of the substitute fin portion and the substrate.
Optionally, the material of the substitute fin portion is silicon germanium or indium gallium arsenide.
Optionally, the substitute fin portions and the second isolation layer are arranged in parallel at equal intervals in the first isolation layer.
Optionally, the width of the substitute fin is the same as that of the second isolation layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the semiconductor structure forming method provided by the invention, the pseudo fin part is removed, and a first groove is formed in the first isolation layer; forming a second isolation layer which is filled in the first groove; removing the temporary fin part, and forming a second groove in the first isolation layer; and forming a replacing fin part filled in the second groove. The distance between the first groove and the second groove is equal to the distance between the dummy fin portion and the temporary fin portion, so that the distance between the first groove and the second groove is long, that is, the width of the first isolation layer between the first groove and the second groove is large. Therefore, when the second isolation layer is formed firstly and then the substitute fin portion is formed, in the process of forming the second isolation layer, the first isolation layer located between the first groove and the second groove plays a sufficient protection role on the side wall of the temporary fin portion, loss of the temporary fin portion caused by the process of forming the second isolation layer is avoided, the temporary fin portion is guaranteed to have good width uniformity, and the width uniformity of the substitute fin portion formed at the position of the temporary fin portion is improved. When the substitute fin portion is formed first and then the second isolation layer is formed, in the process of forming the second isolation layer, the first isolation layer located between the first groove and the second groove plays a sufficient protection role for the substitute fin portion, loss of the substitute fin portion caused by the process of forming the second isolation layer is avoided, the width uniformity of the substitute fin portion is further improved, and the electrical performance of the formed semiconductor structure is improved.
In the alternative scheme, the second isolation film is formed by adopting an atomic layer deposition process, the atomic layer deposition process does not need to introduce flowing oxygen and water vapor and can be carried out in a low-temperature environment, so that when the second isolation layer is formed firstly and then the substituted fin portion is formed, the loss of the temporary fin portion side wall caused by the process of forming the second isolation film can be avoided, the width uniformity of the temporary fin portion is ensured, and the width uniformity of the substituted fin portion formed at the position of the temporary fin portion is improved. When the substitute fin portion is formed first and the second isolation layer is formed later, the loss of the side wall of the substitute fin portion caused by the forming process of the second isolation film can be prevented, the width uniformity of the substitute fin portion is ensured, and therefore the electrical performance of the formed semiconductor structure is enhanced. In addition, the second isolation film formed by the atomic layer deposition process has better uniformity and good step coverage at the bottom corner of the first groove.
In an alternative, before forming the substitute fin portion, the method further comprises the steps of: and an epitaxial transition layer is formed at the bottom of the second groove by adopting a selective epitaxial process, the epitaxial transition layer is well matched with the substituted fin part, a certain buffering effect can be achieved, the problem of large lattice mismatch between the substituted fin part and the substrate can be effectively improved, so that the defects of dislocation and the like in the substituted fin part are reduced, the surface flatness of the substituted fin part is improved, and the high-quality substituted fin part is formed.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Detailed Description
As is apparent from the background art, the electrical properties of the semiconductor structure manufactured by the prior art semiconductor structure forming method need to be improved.
Now, an analysis is performed in combination with a method for forming a semiconductor structure, and fig. 1 to 6 are schematic structural diagrams corresponding to respective steps in the method for forming a semiconductor structure, where the process steps for forming the semiconductor structure mainly include:
referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes an edge region i and a central region ii surrounded by the edge region i, the central region ii has a temporary fin 110 protruding from the substrate 100 thereon, the edge region i has a dummy fin 120 protruding from the substrate 100 thereon, the substrate 100 further has a first isolation layer 400 thereon, and the first isolation layer 400 covers sidewalls of the temporary fin 110 and sidewalls of the dummy fin 120;
referring to fig. 2, the dummy fins 120 and the temporary fins 110 are removed, and a groove 130 is formed in the first isolation layer 400;
referring to fig. 3, an alternative fin 600 filling the recess 130 is formed;
referring to fig. 4, removing a portion of the thickness of the replacement fin 600 and a portion of the thickness of the first isolation layer 400 on the edge region i, where the top of the remaining replacement fin 600 and the top of the remaining first isolation layer 400 on the edge region i are lower than the top of the replacement fin 600 on the central region ii;
referring to fig. 5, a second isolation layer 500 is formed on top of the dummy fin 600 and on top of the first isolation layer 400 on the edge region i by using a Fluid Chemical Vapor Deposition (FCVD);
referring to fig. 6, a portion of the thickness of the second isolation layer 500 on the edge region i is removed, and a portion of the thickness of the first isolation layer 400 on the central region ii is removed, leaving the top of the first isolation layer 400 and the top of the second isolation layer 500 lower than the top of the replacement fin 600 on the central region ii.
The semiconductor structure formed by the method has poor electrical properties, and the reason for analyzing the poor electrical properties is as follows:
after removing the partial thickness of the dummy fin 600 (refer to fig. 4) and the partial thickness of the first isolation layer 400 on the edge region i, widths of the first isolation layers on two sides of the dummy fin 600 at the periphery of the central region ii are different, where a width of the first isolation layer on a sidewall close to the edge region i is a first width x, and a width of the first isolation layer on a sidewall far from the edge region i is a second width y, obviously, the second width y is greater than the first width x.
In forming the second isolation layer 500 (see fig. 5) by the FCVD process, a flowable oxygen and water vapor are introduced, and the FCVD process first deposits a precursor (not shown) of the second isolation layer 500, the precursor is annealed to be transformed into the second isolation layer 500, the annealing temperature of the annealing process is high (greater than or equal to 700 ℃), which helps to accelerate the diffusion of the oxygen and water vapor, and the oxygen and water vapor easily passes through the first isolation layer with the first width x and oxidizes the sidewalls of the replacement fin 600 located at the periphery of the central region ii, which causes the sidewalls of the replacement fin 600 near the edge region i to be lost. Therefore, after removing a portion of the first isolation layer 400 on the central region ii, the width of the replacement fin 600 at the periphery of the central region ii is smaller, and the width of the replacement fin 600 at the inside of the central region ii is larger, that is, the uniformity of the replacement fin 600 in the central region ii is poorer, thereby resulting in a reduction in the electrical performance of the semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a temporary fin part and a pseudo fin part which protrude out of the substrate; forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the temporary fin part and the side wall of the pseudo fin part; removing the pseudo fin part, and forming a first groove in the first isolation layer; forming a second isolation layer which is filled in the first groove; removing the temporary fin part, and forming a second groove in the first isolation layer; forming a substitute fin part filled in the second groove, wherein the material of the substitute fin part is different from that of the temporary fin part; and removing part of the first isolation layer and the second isolation layer, wherein the top of the first isolation layer and the top of the second isolation layer are lower than the top of the substitute fin portion.
Removing the pseudo fin part, forming a first groove in the first isolation layer, and then forming a second isolation layer which is filled in the first groove; and removing the temporary fin part, and forming a substitute fin part filled in the second groove after forming the second groove in the first isolation layer. The distance between the first groove and the second groove is equal to the distance between the dummy fin portion and the temporary fin portion, so that the distance between the first groove and the second groove is long, that is, the width of the first isolation layer between the first groove and the second groove is large. Therefore, when the second isolation layer is formed firstly and then the substitute fin portion is formed, in the process of forming the second isolation layer, the first isolation layer located between the first groove and the second groove plays a sufficient protection role on the side wall of the temporary fin portion, loss of the temporary fin portion caused by the process of forming the second isolation layer is avoided, the temporary fin portion is guaranteed to have good width uniformity, and the width uniformity of the substitute fin portion formed at the position of the temporary fin portion is improved. When the substitute fin portion is formed first and then the second isolation layer is formed, in the process of forming the second isolation layer, the first isolation layer located between the first groove and the second groove plays a sufficient protection role for the substitute fin portion, loss of the substitute fin portion caused by the process of forming the second isolation layer is avoided, the width uniformity of the substitute fin portion is further improved, and the electrical performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 7, a substrate 10 is provided, and the substrate 10 has a temporary fin portion 11 and a dummy fin portion 12 protruding from the substrate 10.
In this embodiment, the substrate 10 includes an edge region i and a central region ii surrounded by the edge region i; the dummy fin portion 12 is located above the edge region i, and the temporary fin portion 11 is located above the central region ii.
In this embodiment, the substrate 10 is made of silicon, in other embodiments, the substrate may also be made of germanium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the temporary fin portion 11 is the same as the material of the dummy fin portion 12, and is the same as the material of the substrate 10, in this embodiment, the materials of the temporary fin portion 11 and the dummy fin portion 12 are silicon, and in other embodiments, the materials of the temporary fin portion and the dummy fin portion may also be germanium.
Specifically, the process steps for forming the substrate 10, the temporary fin portion 11 and the dummy fin portion 12 include: providing an initial substrate; forming a patterned mask layer 20 on top of the initial substrate; and etching the initial substrate by taking the mask layer 20 as a mask, wherein the etched initial substrate is taken as the substrate 10, and the bulges on the substrate 10 are taken as the temporary fin parts 11 and the pseudo fin parts 12.
The temporary fin portions 11 and the dummy fin portions 12 are arranged on the substrate 10 in parallel at equal intervals, and the dummy fin portions 12 are used for enabling two sides of each temporary fin portion 11 to be in the same etching environment in the process of etching the initial substrate, so that good uniformity of each formed temporary fin portion 11 is guaranteed.
In this embodiment, the widths of the temporary fin portion 11 and the dummy fin portion 12 are the same; the temporary fin portion 11 and the dummy fin portion 12 have the same height.
In this embodiment, after the temporary fin portion 11 and the dummy fin portion 12 are formed, the mask layer 20 on the top of the temporary fin portion 11 and the top of the dummy fin portion 12 is retained. When a planarization process is performed subsequently, the top of the mask layer 20 is used to define a stop position of the planarization process, so as to protect the temporary fin portion 11 and the dummy fin portion 12.
After the temporary fin portion 11 and the dummy fin portion 12 are formed, the method for forming a semiconductor structure further includes: a liner oxide layer 30 is formed on the top and sidewalls of the dummy fin 12, the top of the substrate 10, and the top and sidewalls of the temporary fin 11.
In this embodiment, the material of the pad oxide layer 30 is germanium oxide, and in other embodiments, the material of the pad oxide layer may also be silicon oxide.
The process of forming the liner oxide layer 30 is an oxidation process, and since the temporary fin portion 11 and the dummy fin portion 12 are formed by etching the initial substrate 10, the top of the temporary fin portion 11 and the top of the dummy fin portion 12 generally have convex corners. In the process of forming the pad oxide layer 30, the edge has a larger specific surface and is more easily oxidized. And subsequently, the liner oxide layer 30 is removed, and the edges and corners are removed together with the liner oxide layer 30, so that the temporary fin 11 and the dummy fin 12 with smooth surfaces are obtained, the phenomenon of point discharge is avoided, and the performance of the semiconductor structure is improved.
Referring to fig. 8, a first isolation layer 40 is formed on the substrate 10, and the first isolation layer 40 covers sidewalls of the temporary fin 11 and sidewalls of the dummy fin 12.
The material of the first isolation layer 40 is an insulating material, the material of the first isolation layer 40 is different from the material of the mask layer 20, in this embodiment, the material of the first isolation layer 40 is silicon nitride, and in other embodiments, the material of the first isolation layer may also be silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Specifically, the process of forming the first isolation layer 40 includes: forming a first isolation film (not shown) on the substrate 10 not occupied by the temporary fin portion 11 and the dummy fin portion 12, wherein the top of the first isolation film is higher than the top of the mask layer 20; and removing the first isolation film higher than the top of the mask layer 20 by adopting a planarization process to form a first isolation layer 40.
In this embodiment, the process of forming the first isolation film is a high aspect ratio chemical vapor deposition process.
Subsequently removing the pseudo fin part, and forming a first groove in the first isolation layer; forming a second isolation layer which is filled in the first groove; removing the temporary fin part, and forming a second groove in the first isolation layer; and forming a substitute fin part filled in the second groove, wherein in the embodiment, the second isolation layer is formed first, and then the substitute fin part is formed. In other embodiments, the replacement fin may be formed first, and then the second isolation layer may be formed. Referring to fig. 9 to 12, a process of forming the second isolation layer and then forming the replacement fin portion in this embodiment is described in detail.
Referring to fig. 9, the dummy fin 12 is removed, and a first groove 13 is formed in the first isolation layer 40.
The process steps for forming the first recess 13 include: forming a first photoresist layer (not shown) on top of the first isolation layer 40 and on top of the temporary fin portion 11, the first photoresist layer exposing the top of the dummy fin portion 12; etching the pseudo fin portion 12 by using the first photoresist layer as a mask to form the first groove 13; and removing the first photoresist layer.
In this embodiment, the first photoresist layer exposes the mask layer 20 on the top of the dummy fin 12, so the method for forming the semiconductor structure further includes: in the process step of forming the first recess 13, the mask layer 20 on top of the dummy fin 12 is removed.
In this embodiment, the dummy fin 12 is completely etched away, and the bottom of the first groove 13 is exposed on the surface of the substrate 10.
Referring to fig. 10, a second isolation layer 50 filling the first groove 13 is formed.
The second isolation layer 50 is made of an insulating material, in this embodiment, the second isolation layer 50 is made of silicon oxide, and in other embodiments, the second isolation layer may also be made of germanium oxide, silicon oxycarbonitride, or silicon oxynitride.
The process steps for forming the second isolation layer 50 are as follows: forming a second isolation film (not shown) on top of the first isolation layer 40, on top of the temporary fin 11, on top of the pad oxide layer 30, in the first recess 13, and on top of the first recess 13; and removing the second isolation films on the top of the first isolation layer 40, the top of the temporary fin 11, the top of the pad oxide layer 30 and the top of the first groove 13 to form the second isolation layer 50.
In this embodiment, the second isolation film is formed by an atomic layer deposition process, and the formed second isolation film has better uniformity and good step coverage at the bottom corner of the first groove 13.
The parameters of the atomic layer deposition process comprise: the precursor is tetraethoxysilane; the temperature is 80-700 ℃; the air pressure is 5 millitorr-50 torr; the number of cycles is 20 to 500.
The atomic layer deposition process can be carried out in a low-temperature environment without introducing flowing oxygen and water vapor, so that loss of the side wall of the temporary fin part 11 caused by the process of forming the second isolation film can be avoided, the width uniformity of the temporary fin part 11 is ensured, the temporary fin part 11 is removed subsequently to form a second groove, and then a substitute fin part filled with the second groove is formed, namely, the substitute fin part is formed at the position of the temporary fin part 11, so that the temporary fin part 11 has good width uniformity, the width uniformity of the subsequently formed substitute fin part can be ensured, and the electrical performance of the formed semiconductor structure is improved.
In this embodiment, a Chemical Mechanical Polishing (CMP) process is used to remove the second isolation films on the top of the first isolation layer 40, the top of the temporary fin 11, and the top of the first recess 13.
After the first recess 13 (see fig. 9) is formed, for the temporary fin 11 on the periphery of the central region ii, the width of the first isolation layer 40 on the sidewall close to the edge region i is a third width m, and the width of the first isolation layer 40 on the sidewall far from the edge region i is a fourth width n, where m ═ n.
Compared with the technical scheme that the first isolation layer with partial thickness on the edge region needs to be removed, the width value of the first isolation layer 40 on the side wall of the temporary fin portion 11 on the periphery of the central region ii close to the edge region i is larger, that is, the third width m (refer to fig. 9) is larger, so that in the process of forming the second isolation layer 50, the first isolation layer 40 between the first groove 13 (refer to fig. 9) and the temporary fin portion 11 can play a sufficient protection role on the side wall of the temporary fin portion 11, loss of the temporary fin portion 11 caused by the process of forming the second isolation layer 50 is avoided, the temporary fin portion 11 is ensured to have good width uniformity, and further the width uniformity of a substitute fin portion formed at the position of the temporary fin portion 11 in the following process is improved, so that the electrical performance of the formed semiconductor structure is improved.
Referring to fig. 11, the temporary fin 11 is removed, and a second groove 14 is formed in the first isolation layer 40.
Specifically, the process steps for forming the second groove 14 include: forming a second photoresist layer (not shown) on top of the first isolation layer 40 and on top of the second isolation layer; etching the temporary fin part 11 by taking the second photoresist layer as a mask to form the second groove 14; and removing the second photoresist layer.
In this embodiment, the second photoresist layer exposes the mask layer 20 on the top of the temporary fin 11, so the method for forming a semiconductor structure further includes: in the process step of forming the second recess 14, the masking layer 20 on top of the temporary fin 11 is removed.
In this embodiment, the temporary fin 11 is completely etched away, and the bottom of the second groove 14 exposes the surface of the substrate 10.
Referring to fig. 12, a substitute fin 60 filling the second recess 14 is formed, and the material of the substitute fin 60 is different from that of the temporary fin 11 (see fig. 10).
In this embodiment, the substitute fin portion 60 is made of silicon germanium, and in other embodiments, the substitute fin portion may also be made of ingaas.
In this embodiment, the substitute fin 60 is formed using a selective epitaxy process. In other embodiments, the replacement fin may be formed by a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the parameters of the selective epitaxy process include: the temperature is 600-850 ℃, the air pressure is 8-300 torr, and the process gas comprises GeH4、H2Cl2Si, HCl and H2Said GeH4The flow rate of (A) is 10 to 500 standard ml/min, the ratio of (B) to (C) is H2Cl2The flow rate of Si is 20 standard ml/min-2000 standard ml/min, the flow rate of HCl is 10 standard ml/min-200 standard ml/min, and H2The flow rate of (a) is 10 to 3000 standard ml/min.
Prior to forming the dummy fin 60, the method of forming a semiconductor structure may further include: an epitaxial transition layer 70 is formed at the bottom of the second groove 14 by using a selective epitaxial process.
In the selective epitaxy process, the epitaxial transition layer 70 is well matched with the substitute fin portion 60, and can play a certain role in buffering, so that the problem of large lattice mismatch between the substitute fin portion 60 and the substrate 10 can be effectively solved, the occurrence probability of defects such as dislocation in the substitute fin portion 60 is reduced, the surface flatness of the substitute fin portion 60 is improved, and the substitute fin portion 60 with high quality is formed.
In this embodiment, the material of the epitaxial transition layer 70 is the same as the material of the substrate 10, and the material of the epitaxial transition layer 70 is silicon.
If the thickness of the epitaxial transition layer 70 is too small, the stress generated by lattice mismatch cannot be released well, so that the formed substitute fin portion 60 contains a large amount of dislocations and defects; if the epitaxial transition layer 70 is too thick, the resulting replacement fin 60 may be affected by its crystalline quality and surface finish. In this embodiment, the thickness of the epitaxial transition layer 70 is 3.2 nm to 8 nm.
In other embodiments, the material of the epitaxial transition layer 70 is the same as the material of the substitute fin 60, and the growth temperature of the epitaxial transition layer 70 is lower than the growth temperature of the substitute fin 60.
It should be noted that, in other embodiments, the substitute fin portion may also be directly formed on the surface of the substrate exposed by the second groove.
The substitute fin portion 60 is formed at the position of the temporary fin portion 11, and the width of the first isolation layer 40 on the sidewall of the temporary fin portion 11 at the periphery of the central region ii near the edge region i is larger, that is, the third width m (refer to fig. 9) is larger, so that the first isolation layer 40 on the sidewall near the edge region i plays a certain role in protecting the temporary fin portion 11, and the loss of the sidewall of the temporary fin portion 11 in the process of forming the second isolation layer 50 can be avoided, so that the temporary fin portion 11 has good width uniformity, and the substitute fin portion 60 formed at the position of the temporary fin portion 11 has good width uniformity, so that the electrical performance of the formed semiconductor structure can be improved.
It should be noted that, in other embodiments, the substitute fin portion may be formed first, and then the second isolation layer is formed.
It should be noted that, in other embodiments, if the substitute fin portion is formed first and then the second isolation layer is formed, in the process of forming the second isolation layer, the first isolation layer located between the first groove and the second groove can sufficiently protect the substitute fin portion, so that loss of the substitute fin portion caused by the process of forming the second isolation layer can be avoided, the uniformity of the width of the substitute fin portion is improved, and the electrical performance of the formed semiconductor structure is improved.
Referring to fig. 13, a portion of the thickness of the first isolation layer 40 and the second isolation layer 50 is removed, leaving the top of the first isolation layer 40 and the top of the second isolation layer 50 below the top of the replacement fin 60.
In this embodiment, the method for forming a semiconductor structure further includes: when removing part of the thickness of the first isolation layer 40 and the second isolation layer 50, part of the pad oxide layer 30 is removed, and the top of the pad oxide layer 30 is flush with the top of the first isolation layer 40 and the top of the second isolation layer 50.
In summary, in the technical solution of the method for forming a semiconductor structure provided in the present invention, the dummy fin 12 is removed, and a first groove 13 is formed in the first isolation layer 40 (see fig. 9); forming a second isolation layer 50 filling the first groove 13 (refer to fig. 10); removing the temporary fin portion 11, and forming a second groove 14 in the first isolation layer 40 (refer to fig. 11); forming the replacement fin 60 (refer to fig. 12) filling the second groove 14, a distance between the first groove 13 and the second groove 14 is long, that is, a width of the first isolation layer 40 between the first groove 13 and the second groove 14 is large. Therefore, when the second isolation layer 50 is formed first and then the substitute fin portion 60 is formed, in the process of forming the second isolation layer 50, the first isolation layer 40 located between the first groove 13 and the second groove 14 plays a sufficient role in protecting the sidewall of the temporary fin portion 11, so that the process of forming the second isolation layer 50 is prevented from causing loss to the temporary fin portion 11, the temporary fin portion 11 is ensured to have good width uniformity, and the width uniformity of the substitute fin portion 60 formed at the position of the temporary fin portion 11 is further improved. When the substitute fin portion 60 is formed first and then the second isolation layer 50 is formed, in the process of forming the second isolation layer 50, the first isolation layer 40 located between the first groove 13 and the second groove 14 plays a sufficient role in protecting the substitute fin portion 60, so that the substitute fin portion 60 is prevented from being lost by the process of forming the second isolation layer 50, the width uniformity of the substitute fin portion 60 is improved, and the electrical performance of the formed semiconductor structure is improved.
Referring to fig. 13, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: a substrate 10, the substrate 10 having a first isolation layer 40 thereon; a second spacer layer 50 positioned within the first spacer layer 40 and extending through the first spacer layer 40; a replacement fin 60 located within the first isolation layer 40 and penetrating the first isolation layer 40, and a top of the replacement fin 60 is higher than a top of the first isolation layer 40 and a top of the second isolation layer 50.
In this embodiment, the substrate 10 is made of silicon, in other embodiments, the substrate may also be made of germanium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The first isolation layer 40 and the second isolation layer 50 are made of insulating materials, in this embodiment, the first isolation layer 40 is made of silicon nitride, and the second isolation layer 50 is made of silicon oxide; in other embodiments, the material of the first isolation layer may also be silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the material of the second isolation layer may also be germanium oxide, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the substitute fin portion 60 is made of silicon germanium, and in other embodiments, the substitute fin portion may also be made of ingaas.
In this embodiment, the substitute fin portions and the second isolation layer are arranged in parallel at equal intervals in the first isolation layer, and the substitute fin portions and the second isolation layer have the same width.
An epitaxial transition layer 70 may also be provided between the bottom of the dummy fin 60 and the substrate 10.
In this embodiment, the material of the epitaxial transition layer 70 is the same as the material of the substrate 10, and the material of the epitaxial transition layer 70 is silicon, and the thickness is 3.2 nm to 8 nm.
In other embodiments, the material of the epitaxial transition layer 70 is the same as the material of the substitute fin 60, and the growth temperature of the epitaxial transition layer 70 is lower than the growth temperature of the substitute fin 60.
In summary, in the embodiment, the distance between the substitute fin 60 and the second isolation layer 50 is relatively long, and the first isolation layer 40 with a large width value exists therebetween, so that the process of forming the second isolation layer 50 can be prevented from affecting the width uniformity of the substitute fin 60, and the substitute fin 60 has good width uniformity, so that the electrical performance of the semiconductor structure is enhanced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a temporary fin part and a pseudo fin part which protrude out of the substrate;
forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the temporary fin part and the side wall of the pseudo fin part;
removing the pseudo fin part, and forming a first groove in the first isolation layer;
forming a second isolation layer which is filled in the first groove;
removing the temporary fin part, and forming a second groove in the first isolation layer;
forming a substitute fin part filled in the second groove, wherein the material of the substitute fin part is different from that of the temporary fin part;
removing the first isolation layer and the second isolation layer with partial thickness, wherein the top of the first isolation layer and the top of the second isolation layer are lower than the top of the substitute fin portion;
the process for forming the second isolation layer comprises the following steps: forming second isolation films on the top of the first isolation layer, the top of the temporary fin part, the first groove and the top of the first groove by adopting an atomic layer deposition process; the parameters of the atomic layer deposition process comprise: the precursor is tetraethoxysilane; the temperature is 80-700 ℃; the air pressure is 5 millitorr-50 torr; the cycle number is 20-500; and removing the second isolation films positioned at the top of the first isolation layer, the top of the temporary fin part and the top of the first groove to form the second isolation layer.
2. The method of claim 1, wherein the dummy fin is formed using a selective epitaxy process.
3. The method of forming a semiconductor structure of claim 2, further comprising, prior to forming said dummy fin: and forming an epitaxial transition layer at the bottom of the second groove by adopting a selective epitaxial process.
4. The method of forming a semiconductor structure of claim 3, wherein a material of the epitaxial transition layer is the same as a material of the substrate.
5. The method of claim 3, wherein a material of the epitaxial transition layer is the same as a material of the dummy fin, and a growth temperature of the epitaxial transition layer is lower than a growth temperature of the dummy fin.
6. The method of claim 1, wherein the substitute fin is formed of silicon germanium or indium gallium arsenide.
7. The method of claim 1, wherein the second isolation layer is formed prior to forming the dummy fin.
8. The method of forming a semiconductor structure of claim 7, wherein the process step of forming the first recess comprises: forming a first photoresist layer on the top of the first isolation layer and the top of the temporary fin part; etching the pseudo fin part by taking the first photoresist layer as a mask to form the first groove; and removing the first photoresist layer.
9. The method of forming a semiconductor structure of claim 7, wherein the process step of forming the second recess comprises: forming a second photoresist layer on top of the first isolation layer and on top of the second isolation layer; etching the temporary fin part by taking the second photoresist layer as a mask to form a second groove; and removing the second photoresist layer.
10. The method of claim 1, wherein the temporary fin portion and the dummy fin portion have the same width; the temporary fin portion and the dummy fin portion have the same height.
11. The method of claim 1, wherein the temporary fin and the dummy fin are equally spaced apart and juxtaposed on the substrate prior to forming the first isolation layer.
12. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises an edge region and a central region surrounded by the edge region; wherein the dummy fin portion is located above the edge region, and the temporary fin portion is located above the central region.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
CN103426882A (en) * 2012-05-16 2013-12-04 台湾积体电路制造股份有限公司 CMOS device and method for forming the same
CN106960793A (en) * 2016-01-11 2017-07-18 中芯国际集成电路制造(上海)有限公司 The forming method of fin and the forming method of fin field effect pipe
WO2017171717A1 (en) * 2016-03-28 2017-10-05 Intel Corporation Aligned pitch-quartered patterning for lithography edge placement error advanced rectification

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426882A (en) * 2012-05-16 2013-12-04 台湾积体电路制造股份有限公司 CMOS device and method for forming the same
CN106960793A (en) * 2016-01-11 2017-07-18 中芯国际集成电路制造(上海)有限公司 The forming method of fin and the forming method of fin field effect pipe
WO2017171717A1 (en) * 2016-03-28 2017-10-05 Intel Corporation Aligned pitch-quartered patterning for lithography edge placement error advanced rectification

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