JP5707812B2 - Current detection circuit - Google Patents

Description

  The present invention relates to a current detection circuit that detects an overcurrent with respect to a pulse current.

2. Description of the Related Art Conventionally, a technique for providing an overcurrent detection circuit that does not erroneously detect a load that generates a pulsating current or generation of pulsed noise has been considered. (For example, Patent Document 1)
In Patent Document 1, the output of the current detection resistor is input to a comparison circuit via a filter circuit configured by an RC integration circuit, and an overcurrent is detected by comparison with a predetermined current value. In the filter circuit, the filter constant can be appropriately set according to the conditions.

In another patent document, a technique has been considered in which a delay in a current detection circuit including a filter circuit is solved to detect a current change having a steep waveform. (For example, Patent Document 2)
In this Patent Document 2, the magnitude of the change in output voltage (load current change) from the detection resistor is greater than or equal to the Vf (forward drop) voltage of the diode due to the diode connected in parallel with R (resistance) of the RC filter. If the resistance R is passed, and the resistance R functions if the voltage is equal to or lower than the same Vf voltage, the filter constant becomes two steps depending on the input voltage.

JP 2005-341663 A JP 2009-159745 A

  In the technique of the above-mentioned Patent Document 1, the degree of quality varies depending on the setting, but in any case, it cannot cope with a steep error and cannot be detected.

  Further, although the technique of Patent Document 2 can detect even a short error pulse depending on conditions, it has a problem that the filter effect varies depending on the duty of the current and the detected voltage varies depending on the pulse width.

  FIG. 3 shows the concept of the basic configuration of the detection circuit common to the above-mentioned patent documents. In the figure, an input terminal IN is connected to the drain of an N-channel FET Q1, and a PWM (pulse width modulation) signal for on / off control is applied to the gate of the FET Q1. The source of the FET Q1 is connected to one end of a resistor RS that detects the magnitude of the current by converting a current amount into a voltage amount by a voltage drop method via the point C, and the other end of the resistor RS is grounded. .

  A current line that includes the resistor RS and becomes an overcurrent detection target is indicated by an arrow CL1 in the figure. One end of the resistor R1 is connected to the source of the FET Q1 and one end of the resistor RS, and the other end of the resistor R1 is connected to the other end of the capacitor C1 whose one end is grounded, and serves as a detection output terminal OUT. The The resistor R1 and the capacitor C1 constitute an RC low-pass filter circuit.

  In such a circuit configuration, if the noise removal characteristic of the RC low-pass filter circuit is improved, the noise component can be surely removed, but part of the signal that should be detected is lost. For this reason, there is a problem that the responsiveness when an overcurrent peak actually occurs decreases.

  Thus, when considering overcurrent detection for a pulsed current, it is very difficult to provide optimum conditions for all of the pulse duty, noise filter characteristics, and overcurrent response.

  The present invention has been made in view of the above-described circumstances, and the object of the present invention is to eliminate the influence of noise in the overcurrent detection with respect to an electric signal given in a pulse form, and to improve the response. The object is to provide an excellent current detection circuit.

The invention according to claim 1 is a current detection circuit, wherein a first comparison unit that converts an input current value into a voltage signal and compares it with a first limit value set in advance; A time constant providing unit for extending the comparison result of the comparison unit as a pulse of a certain period based on a predetermined time constant; a voltage conversion unit for integrating the number of pulses of the output signal of the time constant providing unit and converting the pulse number into a voltage value; And a second comparator that outputs an error pulse by comparing the output of the voltage converter with a second limit value set in advance.

  According to a second aspect of the present invention, in the first aspect of the invention, the voltage conversion unit uses the difference in time constants of charge and discharge of the capacitor of the voltage conversion unit to pulse the output signal of the time constant applying unit. The number is integrated and converted into a voltage value.

  According to the present invention, in overcurrent detection with respect to an electric signal given in a pulse shape, it is possible to improve the responsiveness while reliably removing the influence of noise.

The figure which shows the structure of the overcurrent detection circuit which concerns on one Embodiment of this invention. The timing chart which shows the operation signal waveform in each site | part of the circuit of FIG. 1 which concerns on the embodiment. The figure which shows the circuit structure of a general overcurrent detection.

  Hereinafter, as an embodiment of the present invention, a case where a pulsed current is flowing in a current path to be detected will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration of an overcurrent detection circuit 10 according to the present embodiment. In the figure, an input terminal IN is connected to the drain of an N-channel FET Q1, and a PWM (pulse width modulation) signal for on / off control is applied to the gate of the FET Q1. The source of the FET Q1 is connected to one end of a resistor RS for detecting the magnitude of the current by converting a current amount into a voltage amount by a voltage drop method via the point a, and the other end of the resistor RS is grounded. Is done.

  A current line including the resistor RS and serving as an overcurrent detection target is indicated by an arrow CL11 in the drawing. One end of the resistor Rin1 is connected to the source of the FET Q1 and one end of the resistor RS, and the other end of the resistor Rin1 is connected to the negative input terminal of the first comparator (COMP1) 11.

  A first reference potential Vref1 obtained by dividing the voltage VCC / ground by resistors Ru1 and Rd1 is applied to the plus input terminal of the comparator 11. The comparison output Vo of the first comparator 11 is given to the point b.

  The first comparator 11, the resistor Rin1, the resistor Ru1, and the resistor Rd1 constitute a comparison circuit, and a comparison with the first reference potential Vref1 as a current limit value of the circuit 10 is performed.

  The point b which is the output terminal of the first comparator 11 is applied with the voltage VCC via the resistor Rup and grounded via the capacitor Co. These resistor Rup and capacitor Co constitute a time constant circuit.

  Further, one end of the resistor RB is connected to the point b. The other end of the resistor RB is a point c, and the same point c is grounded via the resistor RBE and is connected to the base of an NPN type transistor Q2.

  The collector of the transistor Q2 is applied with the voltage VCC via the resistor R1 and is connected to the anode of the diode D. The emitter of the transistor Q2 is grounded.

  The cathode of the diode D is connected as a point d to the other end of the capacitor C1 having one end grounded, the resistor R2 having one end grounded, and one end of the resistor Rin2. Further, the other end of the resistor Rin2 is connected to the plus input terminal of the second comparator (COMP2) 12.

  The resistors RB and RBE, the transistor Q2, the diode D, the resistors R1 and R2, and the capacitor C1 are circuits that integrate the number of pulses and convert it to a voltage level by using the difference between the charge and discharge time constants of the capacitor C1. .

  A second reference potential Vref2 obtained by dividing the voltage VCC / ground by resistors Ru2 and Rd2 is applied to the negative input terminal of the second comparator 12. The comparison output of the second comparator 12 is fed back to the positive input terminal via the resistor Rf and is connected to the other end of the resistor Rup to which the voltage VCC is applied at one end to serve as a detection output terminal OUT. The

Next, the operation of the above embodiment will be described.
FIG. 2 is a timing chart showing signal waveforms at various points in the circuit of FIG.

  As shown in FIG. 2A, a pulsed current flows through the current line CL11 when the FET Q1 performs a switching operation by the PWM signal applied to the gate of the FET Q1. When the resistor RS converts the current into a voltage, the potential at the point a has a pulse-like waveform indicating the magnitude of the current flowing through the current line CL11 as shown in FIG.

  The potential at this point a is compared with a first reference voltage AVref1 set as a predetermined overcurrent limit value by a comparison circuit including the first comparator 11. The output format of the first comparator 11 is an open collector. When the potential at the point a does not exceed the reference voltage, the output is opened, the capacitor Co is charged by the resistor Rup, and the voltage at the point b gradually increases. To do.

  Therefore, in an initial state where the potential at the point a does not exceed the first reference voltage AVref1, the capacitor Co is sufficiently charged by the resistor Rup and is at the “H” level as shown in the figure.

  Here, when the current flowing through the current line CL11 increases and the voltage at the point a gradually increases and exceeds the reference voltage as shown in the figure, the output transistor of the comparator 11 is turned on, and the low resistance Therefore, the capacitor Co is rapidly discharged, and the point b immediately becomes the GND potential.

  Next, when the pulse current is turned off and the potential at the point a falls below the detection potential, the output of the comparator 11 is opened again, the capacitor Co is charged by the resistor Rup, and the voltage at the point b gradually increases. Therefore, the potential at the point b which is the output of the first comparator 11 has a waveform as shown in FIG.

  Due to the operation of the output of the first comparator 11 and the operation of the time constant circuit of the resistor Rup and the capacitor Co described above, even if the current limit value is exceeded for a short time, a certain level of “L” level signal is output to the subsequent stage. Pulse width is guaranteed.

  As shown in FIG. 2D, at the point c connected to the base of the transistor Q2, the signal at the point b is divided by the action of the resistors RB and RBE, and the operating point voltage of the transistor Q2 is adjusted.

  The transistor Q2 performs an on / off switching operation as shown in FIG. 2 (E) in accordance with the signal at the point c. In response to this on / off operation, the capacitor C1 is charged through the path of the resistor R1 and the diode D when the transistor Q2 is in the off state. Thereafter, when the transistor Q2 is turned on, the charge accumulated in the capacitor C1 is slowly discharged by the resistor R2.

  Due to this difference in charge / discharge time constant, the voltage of the capacitor C1 increases as the number of pulses of the peak current detected as overcurrent increases. As shown in FIG. 2 (F), the potential at the point d can be understood as a state in which the voltage of the capacitor C1 is accumulated and sequentially increased by the number of pulses of the peak current exceeding the limit.

  With respect to the potential at the point d, the second reference potential Vref2 is applied to the negative input terminal of the second comparator 12 as shown in FIG. The second reference potential Vref2 is a comparison potential set as a detection condition based on how many times a pulse exceeding the current limit value is generated continuously.

  Therefore, as shown in FIG. 2G, in the second comparator 12, the comparison output becomes “H” level when the voltage of the capacitor C1 exceeds the second reference potential Vref2, and this is the overcurrent detection circuit. 10 detection signals are output to a control circuit (not shown) in the subsequent stage.

  As described above in detail, according to this embodiment, in overcurrent detection for an electric signal given in a pulse shape, a pulse exceeding an intended overcurrent level is not missed even in a short time while being recognized as a detection target waveform. Since it is not determined as an overcurrent unless the intended number of times continues, an overcurrent detection operation excellent in responsiveness can be performed while reliably removing the influence of short noise that occurs by accident.

  In the above embodiment, the number of pulses is accumulated by the resistors RB and RBE, the transistor Q2, the diode D, the resistors R1 and R2, and the capacitor C1 using the difference in the charge / discharge time constant of the capacitor C1 to obtain the voltage level. The circuit to be converted was configured.

  Thus, the number of pulses detected as an overcurrent can be counted with a simple configuration and compared with the second reference potential Vref2 that can be arbitrarily set by the second comparator 12. Therefore, the degree of freedom in setting can be increased. Can be increased.

  In the above embodiment, an example has been described in which a pulse-like current is flowing in a current line for detecting an overcurrent. However, when a current to be detected continues, removal of spike-like noise riding on the current is removed. Is possible as well. In the present invention, since the condition for error determination is that two conditions, that is, a signal exceeding the intended level and that it continues for a plurality of times or for the same time, are met, the short-term occurrence that occurs irregularly. The noise component can be reliably excluded.

  In the above-described embodiment, an example of a specific circuit element configuration has been described. However, the present invention is not limited to the above-described configuration, and can be similarly configured using other circuit elements.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the functions executed in the above-described embodiments may be combined as appropriate as possible. The above-described embodiment includes various stages, and various inventions can be extracted by an appropriate combination of a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, if the effect is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 10 ... Overcurrent detection circuit, 11 ... 1st comparator (COMP1), 12 ... 2nd comparator (COMP2).

Claims (6)

A first comparison unit that converts an input current value into a voltage signal and compares the voltage value with a preset first limit value;
A time constant providing unit for extending the comparison result of the first comparison unit as a pulse of a certain period based on a predetermined time constant;
A voltage conversion unit that integrates the number of pulses of the output signal of the time constant applying unit and converts it to a voltage value;
A current detection circuit comprising: a second comparison unit that outputs an error pulse by comparing the output of the voltage conversion unit with a preset second limit value.   The voltage conversion unit integrates and converts the number of pulses of the output signal of the time constant applying unit into a voltage value by using a difference in charge / discharge time constant of the capacitor of the voltage conversion unit. 1. A current detection circuit according to 1. When the voltage converter outputs the pulse of the output signal of the time constant applying unit continuously several times, or when a continuous signal exceeding the total time corresponding to the integrated amount of the plurality of times is input Only, the difference in the time constant is adjusted so that the output voltage of the voltage converter exceeds the second limit value and the comparator circuit output in the second comparator is inverted and an error pulse is output. The current detection circuit according to claim 2, wherein the current detection circuit is provided. The time constant providing unit includes a CR time constant circuit including a capacitor and a time constant setting resistor connected in series to charge the capacitor,
2. The open circuit or the open drain output which cancels the charging current of the time constant setting resistor and discharges the capacitor charge in a short time. 3. The current detection circuit according to any one of 3.   The current detection circuit according to claim 4, wherein an output of the first comparison unit is connected to a connection between the capacitor and the time constant setting resistor.   6. The current detection circuit according to claim 4, wherein the output of the first comparison unit is not fed back to the input unit.

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