JP5704081B2 - Data collection device - Google Patents

Description

  The present invention relates to a data collection device that collects digital data converted by an analog / digital converter (hereinafter abbreviated as “ADC”) and stores the digital data in a memory. More specifically, the same analog signal is parallelized by a plurality of ADCs. The present invention relates to a data collection device that converts the data and collects the obtained data.

  In an analyzer such as a time-of-flight mass spectrometer (hereinafter referred to as “TOFMS”), an analog detection signal obtained by a detector is generally converted into digital data by an ADC and temporarily stored in a memory or a data buffer. In addition, data processing such as spectrum creation processing is performed. For example, in recent high-performance TOFMS, an extremely high A / D conversion rate (sampling rate) of 1 GHz or more is required for data collection at the time of measurement execution, but such a high-speed ADC generally has a low bit resolution. It is difficult to ensure a sufficient dynamic range. Therefore, a method of operating a plurality of ADCs in parallel is known as a method for compensating for the shortage of ADC bit resolution (see Patent Document 1).

  Specifically, two ADCs capable of high-speed operation are prepared, amplifiers having different gains are arranged in front of these ADCs, and the two ADCs are operated in parallel so that different digital signals are applied to the same input signal. Acquire each data. By selecting digital data on the high gain side for input signals with low signal strength, and selecting digital data on the low gain side for input signals with high signal strength, data for high signal strength can be obtained. Saturation is avoided, and high resolution and wide dynamic range data acquisition is possible.

  As described above, in the case of a configuration in which digital data is acquired in parallel by two or more ADCs, the data obtained by the ADC is temporarily stored in a memory such as SRAM, and after acquiring all the data, In general, processing is performed by sending data to a processing unit such as a CPU or a digital signal processor (DSP). At this time, there are the following two methods for storing data obtained from the ADC in the memory.

[Method A] All data is temporarily stored in the memory for each ADC, the signal strength is determined when the data is read from the memory, and if the signal strength is low, the data on the high gain side is selected and the high gain is selected. On the side, if the signal intensity is high so that the signal intensity is saturated, the data on the low gain side is selected. In this case, no data is selected when writing data to the memory.
[Method B] When data obtained from a plurality of ADCs is stored in the memory, the signal strength is determined. If the signal strength is low, data on the high gain side is selected, and the signal strength is on the high gain side. If the data has high signal intensity that would saturate, data on the low gain side is selected and written to the memory. In this case, data selection is not performed when data is read from the memory.

Each of the above two methods has advantages and disadvantages. That is, the advantage of Method A is that all the data for each gain is stored in the memory, so that it is possible to read the data for each ADC later. For example, the two data can be compared or the data from one ADC can be compared. It is easy to debug hardware such as ADC (detection of defects) by confirming the temporal connection of the hardware. On the other hand, since it is necessary to store all data for each ADC, the required memory capacity is large, and the wiring of the circuit board on which the memory is mounted becomes complicated, which is disadvantageous in terms of cost.
On the other hand, the advantage of the method B is that even if there are a plurality of ADCs, the memory capacity for storing data is only one ADC. On the other hand, since only a part of the data obtained by the ADC is stored in the memory, there is a drawback that it is difficult to debug the hardware as described above.
In other words, the conventional data acquisition method emphasizes either ease of hardware debugging or a small amount of memory for storing data, and if one is emphasized, the other is sacrificed to some extent. It cannot be avoided.

JP 2007-256251 A (paragraphs [0003]-[0004])

  The present invention has been made to solve the above-described problems, and the object of the present invention is to reduce the cost of memory by suppressing the capacity of a memory for storing data while ensuring the ease of hardware debugging such as an ADC. It is an object of the present invention to provide a data collection device that can reduce the amount of data.

The present invention made to solve the above problems is a data collection device for converting an input analog signal into a digital signal and collecting it as digital data,
a) high gain side A / D conversion means for amplifying an input analog signal with a first gain and then converting it to a digital signal;
b) In parallel with the high gain side A / D conversion means, the input analog signal is amplified with a second gain lower than the first gain and then converted into a digital signal, and then converted into a digital signal. D conversion means;
c) Multiplying the low gain side data by the low gain side A / D conversion means by a constant corresponding to the difference between the first and second gains, or using this constant, the high gain side by the high gain side A / D conversion means After performing the process of removing the data, difference data calculation means for obtaining a difference between the low gain side data or high gain side data and the high gain side data or low gain side data after the process;
d) memory means for storing the low gain side data and difference data by the difference data calculating means;
e) data restoration means for restoring the high gain side data using the low gain side data and the difference data read from the memory means;
f) Determine or estimate whether the high gain side data restored by the data restoration means is in a signal saturated state, and based on the result, the low gain side data read from the memory means and the data Data selection means for selecting and outputting one of the high gain side data restored by the data restoration means;
It is characterized by having.

  Note that one of the first gain and the second gain may have a gain of “1”, that is, an input analog signal may be converted into a digital signal without substantially amplifying or attenuating.

  There is no time lag in the sampling timing of the analog signal between the high gain side A / D conversion means and the low gain side A / D conversion means, the ratio between the first and second gains is accurate, and further the A / D conversion means In the ideal state where there is no offset or drift, the low gain side data or high gain side data after the multiplication or division processing by the differential data calculation means and the high gain side data or low gain without processing are processed. The side data is almost equivalent until the high gain side data is saturated, and the bit width of the difference data is about the bit width corresponding to the gain difference. Even if there are fluctuation factors such as sampling time lag, the bit width of the difference data may be smaller than the bit width of the original data. Therefore, in the data collection device according to the present invention, the amount of data to be stored in the memory means can be reduced as compared with the case where both the high gain side data and the low gain side data are stored in the memory means.

  On the other hand, if the high gain side data is not saturated, the difference data completely reflects the difference information between the high gain side data and the low gain side data. Therefore, the high gain side data restored by the data restoring means is the same as the output of the high gain side A / D conversion means, and the low gain side data and the high gain side data can be obtained in parallel if necessary. . High resolution data without signal saturation can be acquired by the data selection means. For example, when hardware debugging is desired, the low gain side data and the high gain side data before selection by the data selection means are extracted. Therefore, it is possible to ensure the ease of hardware debugging.

  In general, once a signal exceeding the input range is input to the ADC, it takes a little time to recover to a state where a normal conversion operation can be performed even if the level of the signal decreases. Therefore, in the data selection means, the low gain side data read from the memory means for at least a predetermined time from the time when it is determined or estimated that the high gain side data restored by the data restoration means is in a signal saturation state. May be configured to selectively output.

  According to the data collection device of the present invention, the amount of data to be stored in the memory is reduced compared to the conventional configuration in which all the data obtained by the A / D conversion is stored in the memory in parallel by a plurality of ADCs. All data obtained by A / D conversion can be acquired as needed while reducing. Therefore, it is possible to reduce the cost by saving the capacity of a memory for storing data, and it is possible to easily perform hardware debugging using all data.

1 is a block configuration diagram of a data collection device according to an embodiment of the present invention. FIG. 2 is a block diagram when N = 4 in the data collection device shown in FIG. 1. The schematic diagram for demonstrating the data collection operation | movement in the data collection device shown in FIG.

Hereinafter, an embodiment of a data collection device according to the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram of the data collection device according to this embodiment, and FIG. 2 is a block diagram of N = 4 in the data collection device shown in FIG. FIG. 3 is a schematic diagram for explaining a data collection operation in the data collection apparatus shown in FIG.

  The data collection device of the present embodiment includes a high gain side amplifier 2a having a gain of 1, a low gain side amplifier 2b having a gain of 1 / N (N> 1), a high gain side ADC 3a, a low gain side ADC 3b, an FPGA ( It comprises a data collection processing unit 4 and a memory 5 realized by a field-programmable gate array (ASIC) or an application specific integrated circuit (ASIC). The high gain side ADC 3a and the low gain side ADC 3b are both high-speed ADCs having a sampling rate of 1 to 4 GHz and a bit width of n bits.

  For example, an analog detection signal d obtained by a TOFMS detector is input to the analog signal input terminal 1. The input analog signal d is input in parallel to the high gain side amplifier 2a and the low gain side amplifier 2b, and the outputs d and d / N of both amplifiers 2a and 2b are input to the high gain side ADC 3a and the low gain side ADC 3b, respectively. Is done. Both ADCs 3a and 3b sample signals at the same time (ideally at the same time, but actually have a slight time lag), perform A / D conversion, and perform A / D conversion one sample at a time from the n-bit data bus. Output the converted data.

  The n-bit data D / N output from the low gain side ADC 3 b is input to the N-times multiplier 41, and the difference obtained by subtracting the n bit data D ′ output from the high gain side ADC 3 a from the output of the multiplier 41. Data ΔD = DD ′ is calculated by the differentiator 42. That is, every time data is output sample by sample from the ADCs 3a and 3b, difference data ΔD corresponding to the sample is output from the differencer 42. The n-bit low gain side digital data D / N output from the low gain side ADC 3 b and the m bit difference data ΔD output from the differentiator 42 are stored in the memory 5 as a set.

When data is transmitted to perform data processing by a later stage CPU or DSP (not shown), the low gain side digital data D / N and the difference data ΔD stored as described above are stored from the memory 5 one by one. Read out. The read low gain side digital data D / N is input to a multiplier 43 that is N times the same as the multiplier 41. When the difference data ΔD (= DD ′) is subtracted from the output data D of the multiplier 43 by the difference unit 44, the high gain side digital data D ′ corresponding to the output of the high gain side ADC 3a is restored. Then, the restored high gain side digital data D ′ and the N times multiplied low gain side digital data D are input to the data selection unit 45 and selected based on an instruction from the selection control unit 46. Data is output from the data output terminal 6. Although the input data to the data selection unit 45 is n bits, the data selection unit 45 adds “0” to the log ₂ N bit on the LSB side when the low gain side data is selected, and the high gain side data is When selected, “0” is added to the log ₂ N bit on the MSB side. That is, the bit width of the data output from the data selection unit 45 is expanded from n to n + log ₂ N.

  When the analog signal input from the analog signal input terminal 1 is at a level exceeding the full-scale input range of the high gain side ADC 3a, the ADC 3a is saturated and correct data is not output. On the other hand, the level of the analog signal input to the low gain side ADC 3b at this time is multiplied by 1 / N (N> 1). Therefore, if N is set to a certain value, saturation does not occur in the low gain side ADC 3b. Thus, it is possible to output correctly A / D converted data. Therefore, when the data is selectively output, the selection control unit 46 determines whether the high gain side digital data is saturated or at a level corresponding thereto, and if so, the low gain side digital data is determined. If not, the switching control is performed so that the high gain side digital data is selected.

  In general, once an excessive analog signal is input and saturation occurs in the ADC, an appropriate A / D conversion operation cannot be performed immediately even if the level of the input analog signal decreases. Since the saturation recovery time from when saturation occurs until the A / D conversion operation returns to normal is defined in advance as ADC characteristics, the digital data on the high gain side is saturated or at a level equivalent thereto. Once the determination is made, it is determined that the high gain side digital data has not been saturated. Continue selection, then switch to high gain side digital data selection. Thereby, it is possible to avoid outputting digital data having a large conversion error.

Next, the operation of the data collection apparatus of this embodiment will be described in detail with reference to FIGS. Here, it is assumed that 12-bit ADCs with 1 GHz sampling are used as the ADCs 3a and 3b, and the data width of the memory 5 is 18 bits, which is common in DDR memories. In FIG. 1, n is 12, and the bit width of the difference data is set to 6 so that the low gain side digital data and difference data corresponding to one sample can be simultaneously read from and written to the memory 5. Further, N that determines the gain is set to 2 ² = 4. As a result, the bit width of the data output from the data collection processing unit 4 is 14 bits.

  In this case, as shown in FIG. 3A, 12-bit width data is output from the ADCs 3a and 3b every half cycle of the 500 MHz basic clock. As shown in FIG. 3B, the value of the analog signal input to the high gain side ADC 3a is “100”, “94”,..., And the value of the analog signal input to the low gain side ADC 3b is “30”. ”,“ 22 ”,... Ideally, the latter value should be 1/4 (1 / N) of the former, but due to factors such as sampling timing shifts and variations in the gains of the amplifiers 2a and 2b, 1/4 is not exactly accurate. (However, this numerical example is an extreme value for easy understanding of the explanation). Data obtained by digitizing the values shown in FIG. 3B are output from the ADCs 3a and 3b, respectively. Note that the values after FIG. 3C are actually binarized digital data, but here they are written in ordinary decimal numbers for easy understanding.

  FIG. 3C shows the output data of the multiplier 41, and FIG. 3D shows the difference data ΔD by the differentiator 42. The value of the analog signal “1023” in FIG. 3B is a value exceeding the full-scale input range of the high gain side ADC 3a, and at that time, the difference data indicates MAX. The 12-bit width data obtained by A / D converting the analog signal value in FIG. 3B and the 6-bit width difference data shown in FIG. Simultaneously written to the memory 5.

  At the time of data transmission, the 18-bit data is read from the memory 5 every half cycle of the basic clock of 500 MHz (see FIG. 3E). FIG. 3F shows the output data of the multiplier 43, which has the same value as in FIG. FIG. 3G shows output data obtained by calculating the difference between FIG. 3F and the lower part of FIG. Unless the input analog signal exceeds the input range of the high gain side ADC 3a, the value shown in FIG. 3G is the same as the input analog signal to the high gain side ADC 3a shown in FIG. It can be seen that the digital data on the high gain side can be completely restored. The selection control unit 46 determines whether signal saturation has occurred based on the value of the high gain side digital data (or the value of the low gain side digital data) that is the difference result, and based on the result, the data selection unit 45 selects and outputs low gain side digital data or high gain side digital data (see FIG. 3H).

  In this example, the digital data on the high gain side is selected immediately after the signal saturation is determined, but in reality, the digital data on the low gain side is selected in consideration of the saturation recovery time as described above. It is good to continue for a predetermined time.

  In the conventional configuration in which both the 12-bit high gain digital data and the low gain digital data obtained by the ADCs 3a and 3b are stored in the memory, two 18-bit DDR memories are required. On the other hand, in the configuration of the above embodiment, the low gain side digital data of 12 bits and the difference data of 6 bits are allocated to the memory area of 18 bits, so that only one DDR system memory is required. become. As described above, in the data collection device according to the present embodiment, the number of necessary memories can be reduced to reduce the cost. Further, for example, by extracting data from the two input sides of the data selection unit 45 or by allowing the selection control unit 46 to forcibly select one of the data, the high gain side digital data and the low data are reduced. It is possible to extract all of the gain side digital data, and hardware debugging can be easily performed using these data.

  It should be noted that the above embodiment is an example of the present invention, and it is obvious that any modification, correction, or addition as appropriate within the scope of the present invention is included in the scope of the claims of the present application.

DESCRIPTION OF SYMBOLS 1 ... Analog signal input terminal 2a ... High gain side amplifier 2b ... Low gain side amplifier 3a ... High gain side ADC
3b ... Low gain ADC
4 ... Data collection processing units 41, 43 ... Multipliers 42, 44 ... Difference unit 45 ... Data selection unit 46 ... Selection control unit 5 ... Memory 6 ... Data output terminal

Claims (1)

A data collection device that converts an input analog signal into a digital signal and collects it as digital data,
a) high gain side A / D conversion means for amplifying an input analog signal with a first gain and then converting it to a digital signal;
b) In parallel with the high gain side A / D conversion means, the input analog signal is amplified with a second gain lower than the first gain and then converted into a digital signal, and then converted into a digital signal. D conversion means;
c) Multiplying the low gain side data by the low gain side A / D conversion means by a constant corresponding to the difference between the first and second gains, or using this constant, the high gain side by the high gain side A / D conversion means After performing the process of removing the data, difference data calculation means for obtaining a difference between the low gain side data or high gain side data and the high gain side data or low gain side data after the process;
d) memory means for storing the low gain side data and difference data by the difference data calculating means;
e) data restoration means for restoring the high gain side data using the low gain side data and the difference data read from the memory means;
f) Determine or estimate whether the high gain side data restored by the data restoration means is in a signal saturated state, and based on the result, the low gain side data read from the memory means and the data Data selection means for selecting and outputting one of the high gain side data restored by the data restoration means;
A data collection device comprising:

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