JP5696485B2 - Inverter device and electric motor drive system - Google Patents

Description

  The present invention relates to an inverter device and an electric motor drive system.

  Conventionally, an inverter device described in Patent Document 1 is known as an example of an inverter device including a failure detection unit that detects a failure of a switching element.

  This patent document 1 includes an inverter circuit that has a plurality of switching elements and outputs a three-phase current, a current detection circuit that detects a current value of a three-phase current output from the inverter circuit, and a current detection circuit that detects the current value. An inverter device is disclosed that includes failure element determination means (failure detection unit) that determines a failure of a switching element based on the magnitude of the current value of each phase. In this inverter device, a fuse is inserted in series with respect to each of the plurality of switching elements so that the switching element is opened even when a short circuit failure occurs.

Japanese Patent Laid-Open No. 2004-120883

  However, since the fuse is additionally used to open the inverter device even when the switching element is short-circuited, the configuration of the inverter device is complicated accordingly, and the failed switching element is The configuration was such that it could not be distinguished whether it was a short circuit failure or an open failure.

  One object of the present invention is to specify a faulty switching element without complicating a circuit configuration, and to determine an inverter device and an electric motor that can determine whether the fault of the switching element is a short-circuit fault or an open fault To provide a drive system.

In order to achieve the above object, an inverter device according to a first aspect of the present invention includes a DC voltage source and a plurality of switching elements, wherein the plurality of switching elements are controlled by a gate signal based on a PWM signal. A power converter that converts a direct current supplied from a plurality of phases into an alternating current, a voltage detector that detects an output voltage of the power converter and outputs a voltage detection signal, a PWM signal or a gate signal, and a voltage detection signal And a failure determination unit that determines a failure of the switching element based on the configuration, and the plurality of switching elements are configured to be driven by a gate signal generated by including a dead time in the PWM signal. Is switched on when the time when the polarity of the voltage detection signal and the polarity of the PWM signal do not match is greater than a predetermined time equal to or greater than the dead time. Element is configured to determine that is faulty.

An inverter device according to a second aspect of the present invention includes a DC voltage source and a plurality of switching elements, wherein the plurality of switching elements are controlled by a gate signal based on the PWM signal, and a plurality of DCs supplied from the DC voltage source are supplied. Based on the power conversion unit that converts to phase alternating current, the voltage detector that detects the output voltage of the power conversion unit and outputs the voltage detection signal, the PWM signal or the gate signal, and the voltage detection signal, A fault determination unit for determining a fault, a current detector that detects an output current of the power conversion unit and outputs a current detection signal, and is provided between the DC voltage source and the power conversion unit, and is input to the power conversion unit And a smoothing capacitor for smoothing the direct current, and the failure determination unit has a short circuit failure or an open failure based on at least the current detection signal. If the switching element is determined to be short-circuited by the failure determination unit when the DC voltage source is shut off, the switching element is paired with the switching element that is short-circuited. The switching element of the opposite arm is kept off, and the charge accumulated in the smoothing capacitor is discharged using the switching element of the opposite arm that is in a phase different from that of the switching element that is short-circuited. It is configured.
An inverter device according to a third aspect of the present invention includes a DC voltage source and a plurality of switching elements, wherein the plurality of switching elements are controlled by a gate signal based on the PWM signal, and a plurality of DCs supplied from the DC voltage source are controlled. Based on the power conversion unit that converts to phase alternating current, the voltage detector that detects the output voltage of the power conversion unit and outputs the voltage detection signal, the PWM signal or the gate signal, and the voltage detection signal, A failure determination unit for determining a failure, and when the failure of the switching element is detected as a short-circuit failure by the failure determination unit, the gate signal of the arm opposite to the short-circuited switching element is always set to L level, A load can be driven by a switching element other than the detected phase.
An electric motor drive system according to a fourth aspect of the present invention includes a DC voltage source and a plurality of switching elements, wherein the plurality of switching elements are controlled by a gate signal based on a PWM signal, and a plurality of DCs supplied from the DC voltage source are controlled. Based on the power converter that converts the phase AC into the voltage, the voltage detector that detects the output voltage of the power converter and outputs the voltage detection signal, the PWM signal or the gate signal, and the polarity of the voltage detection signal, An inverter device including a failure determination unit that determines a failure of the switching element; and an electric motor connected to the inverter device, wherein the plurality of switching elements are driven by a gate signal generated by including a dead time in the PWM signal The failure determination unit determines that the time when the polarities of the voltage detection signal and the PWM signal do not match is the dead time. If more greater than the predetermined time during are configured to determine that the switching element is faulty.

  According to the present invention, it is possible to identify a faulty switching element and to determine whether the fault of the switching element is a short-circuit fault or an open fault.

It is a block diagram which shows the structure of the inverter apparatus by 1st Embodiment of this invention. It is a block diagram of the failure determination part of the inverter apparatus by 1st Embodiment of this invention. It is a block diagram which shows the structure of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of failure judgment based on gate signal Gup of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of the failure determination based on the gate signal Gun of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of failure determination based on the gate signal Gvp of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of failure determination based on the gate signal Gvn of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of failure determination based on the gate signal Gwp of the inverter apparatus by 2nd Embodiment of this invention. It is a truth table of failure judgment based on gate signal Gwn of the inverter apparatus by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the inverter apparatus by the modification of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, about the same structure, the same code | symbol is attached | subjected and duplication description is abbreviate | omitted suitably.

(First embodiment)
First, with reference to FIG. 1, the structure of the inverter apparatus 101 which the electric motor drive system 100 by 1st Embodiment of this invention has is demonstrated.

  FIG. 1 is a block diagram showing a configuration of an inverter device 101 according to the first embodiment of the present invention. As shown in FIG. 1, the inverter device 101 includes a DC voltage source 1, smoothing capacitors 2 a and 2 b, a power conversion unit 3, a voltage command calculation unit 4, a PWM signal generation unit 5, and a gate drive circuit 6. , Selector switches 7a (S1), 7b (S2) and 7c (S3), a voltage detector 8, a current detector 9, and a failure determination unit 10. An electric motor 11 is connected to the output side of the inverter device 101.

  The DC voltage source 1 includes an AC power supply 21 and a rectifier circuit 22 including a plurality of diodes, and supplies a DC voltage to the power conversion unit 3. The smoothing capacitor 2a has a positive electrode connected to the positive electrode side of the DC voltage source 1 and a negative electrode connected to the positive electrode of the smoothing capacitor 2b. Further, the negative electrode of the smoothing capacitor 2 b is connected to the negative electrode side of the DC voltage source 1.

  Smoothing capacitors 2 a and 2 b smooth the DC voltage from DC voltage source 1 and supply the smoothed DC voltage to power conversion unit 3.

  The power conversion unit 3 includes six switching elements 31 to 36. The switching element 31 includes a transistor Up made of an IGBT (insulated gate bipolar transistor) and a diode Bup. Similarly, the switching element 32 (33, 34, 35, 36) includes a transistor Aun (Avp, Avn, Awp, Awn) and a diode Bun (Bvp, Bvn, Bwp, Bwn), which will be described later. It is driven by gate signals Gup, Gun, Gvp, Gvn, Gwp, Gwn.

One terminal of the switching elements 31, 33, and 35 constituting the upper arm of the power conversion unit 3 is connected to the positive electrode side of the DC voltage source 1, and the other terminals are changeover switches 7a, 7b, and 7c, which will be described later, respectively. Terminal A. One terminal of the switching elements 32, 34 and 36 constituting the lower arm of the power conversion unit 3 is connected to the negative electrode side of the DC voltage source 1, and the other terminal is a terminal of a changeover switch 7a, 7b and 7c described later. Connected to A. The power conversion unit 3 outputs a three-phase AC voltage to the motor 11 based on voltage commands Vu ^* , Vv ^* , and Vw ^* described later with the above configuration.

Although not shown, the voltage command calculation unit 4 calculates the voltage commands Vu ^* , Vv ^* , Vw ^* using the speed command and detection speed of the motor 11 and outputs the calculated voltage command to the PWM signal generation unit 5. To do.

The PWM signal generator 5 includes three comparators 40. The PWM signal generation unit 5 generates the PWM signals Su, Sv, Sw by comparing the voltage commands Vu ^* , Vv ^* , Vw ^* with the carrier wave by the comparator 40, and the gate drive circuit 6 and the failure determination unit 10 Output to.

  The gate drive circuit 6 outputs the PWM signals Su, Sv, Sw to the switching elements 31, 33, 35 constituting the upper arm as the gate signals Gup, Gvp, Gwp, respectively, and the switching elements 32, 34 constituting the lower arm. , 36, the inverted signals of the PWM signals Su, Sv, Sw are output as gate signals Gun, Gvn, Gwn, respectively. The gate signals Gup, Gun, Gvp, Gvn, Gwp, and Gwn are signals that consider dead time. The dead time is a time for delaying an ON operation that is provided in order to prevent the switching elements that constitute the upper arm and the switching elements that constitute the lower arm from being simultaneously turned on.

  The changeover switches 7a, 7b and 7c are configured such that their terminals B can be connected to neutral points N1, N2 and N3 between the smoothing capacitor 2a and the smoothing capacitor 2b, respectively, and the terminal C is connected to the electric motor 11. During normal operation, the terminals A and C of the changeover switches 7a, 7b and 7c are connected. For this reason, when the failure determination unit 10 is used so as to perform failure determination only during normal operation, the motor 11 may be connected to the terminal A of the changeover switches 7a, 7b, and 7c.

  The voltage detector 8 detects the U-phase, V-phase, and W-phase voltages output from the power conversion unit 3, generates a signal obtained by performing insulation processing and potential conversion from these detection values, and detects the voltage detection signal Vu, It outputs to the failure determination part 10 as Vv and Vw. Each phase voltage detected by the voltage detector 8 is the potential on the positive side of the smoothing capacitor 2a when the switching element of the upper arm is ON and the switching element of the lower arm is OFF, the switching element of the upper arm is OFF, When the switching element is ON, the potential is on the negative polarity side of the smoothing capacitor 2b.

  The current detector 9 detects each phase current flowing between the terminal C of the changeover switches 7a, 7b and 7c and the motor 11, generates a signal obtained by performing insulation processing and potential conversion from these detected values, and generates a current detection signal. Output to the failure determination unit 10 as Iu, Iv, and Iw.

  The failure determination unit 10 has a function of determining a failure of the switching elements 31 to 36 constituting the power conversion unit 3. FIG. 2 is a block diagram of the failure determination unit 10 of the inverter device 101. As shown in FIG. 2, the failure determination unit 10 includes an XOR circuit 41, a monostable multivibrator 42, two AND circuits 43 and 44, a counter 45, two latch circuits 46 and 47, and an OR circuit 48. And. Although not shown, the failure determination unit 10 determines the polarities of the voltage detection signals Vu, Vv, and Vw input from the voltage detector 8 and generates voltage polarity signals Vu_pol, Vv_pol, and Vw_pol. FIG. 2 shows one phase (U phase).

  Next, the operation of the failure determination unit 10 will be described. The XOR circuit 41 compares the PWM signal Su (Sv, Sw) from the PWM signal generator 5 with the voltage polarity signal Vu_pol (Vv_pol, Vw_pol), and the polarity of the command (PWM signal Su) and the actually output voltage. When (Vu_pol) does not match, an H level signal is output to one input side of the AND circuit 43 and one input side of the AND circuit 44. The AND circuit 43 performs an AND process on the output of the XOR circuit 41 and the clock signal CLK and outputs the result to the counter 45.

  The counter 45 is configured to count an input signal (output of the AND circuit 43) and output a carry signal (H level signal) when a predetermined time elapses. The counter 45 outputs a carry signal to the latch circuit 46 when a predetermined time (for example, 10 μs) equal to or greater than the dead time added by the gate drive circuit 6 is counted. Note that the predetermined time is set to be equal to or shorter than a time during which secondary breakdown to other failed switching elements can be prevented.

  The latch circuit 46 is configured to output a carry signal from the counter 45 as a failure 1 to one input side of the OR circuit 48. The failure 1 is detected when the voltage polarity signal Vu_pol (Vv_pol, Vw_pol) does not change even after the predetermined time has elapsed although the PWM signal Su (Sv, Sw) has changed.

  The monostable multivibrator 42 has a function of outputting a signal having a certain width (H level signal) when an input signal rises or falls. The monostable multivibrator 42 receives the voltage polarity signal Vu_pol (Vv_pol, Vw_pol) as an input signal, and outputs a signal having a constant width (H level signal) from the AND circuit 44 when the input signal rises or falls. Output to the other input side. The AND circuit 44 performs an AND process on the output of the XOR circuit 41 and the output of the monostable multivibrator 42 and outputs the result to the latch circuit 47.

  The latch circuit 47 is configured to output the signal from the AND circuit 44 to the other input side of the OR circuit 48 as a failure 2. The failure 2 is detected when the voltage polarity signal Vu_pol (Vv_pol, Vw_pol) changes even though the PWM signal Su (Sv, Sw) has not changed.

In addition, the failure determination unit 10 performs the following operation when the switching elements 31 to 36 are normal and no failure occurs. The PWM signal Su (Sv, Sw) corresponding to the voltage command Vu ^* (Vv ^* , Vw ^* ) and the voltage polarity signal Vu_pol (Vv_pol, Vw_pol) match except for the dead time period. Since the XOR circuit 41 is at L level during the coincidence period, no failure is detected. In the dead time period, both of the above do not match (XOR circuit 41 becomes H level), but XOR circuit 41 becomes L level before counter 45 outputs a carry signal (H level signal). As a result, the output of the AND circuit 43 becomes L level and the counter 45 is initialized.

  The V phase and W phase failure determination is performed in the same manner.

  With the above configuration, the failure determination unit 10 detects at least one of the failure 1 and the failure 2 based on the output of the OR circuit 48, and any one of the switching elements 31 to 36 has failed due to this detection. judge.

  Next, the determination of a failed switching element and the determination process of a short circuit failure or an open failure will be described by taking as an example a case where the failure determination unit 10 determines that the U-phase switching element 31 or 32 has failed.

(Determination of faulty switching element)
Failure determination unit 10 turns off switching elements 31 and 32 and then outputs a PWM signal for turning on only switching element 31 for a predetermined time to switching elements 31 and 32 (outputs failure determination signal J1). Then, a determination process for a short circuit failure of the switching element 32 is performed. Here, the failure determination unit 10 determines whether or not the current detection signal Iu from the current detector 9 is an abnormal current when only the switching element 31 is turned on, and the current detection signal Iu is the abnormal current. Is determined, it is determined that the switching element 32 is short-circuited. This is to detect the current that flows when the smoothing capacitors 2a and 2b are short-circuited when the switching element 31 is on and the switching element 32 is off. Therefore, the detection level at the time of detecting abnormality detection may be set to be equal to or greater than the offset error of current detection, for example. Similarly, the failure determination unit 10 performs a determination process for a short circuit failure of the switching element 31 by outputting only the switching element 32 in an ON state for a predetermined time (outputs a failure determination signal J2).

  When the current detection signal Iu does not reach a predetermined value or more even though it is determined that at least one of the switching element 31 and the switching element 32 has failed due to the output of the OR circuit 48 described above. Is determined that the switching element (switching element 32) of the opposite arm that is paired with the switching element (for example, switching element 31) that has been subjected to the determination process of the short-circuit failure has an open failure.

  As described above, it is determined which switching element is faulty and whether the fault of the switching element is a short-circuit fault or an open fault. The same applies to the V phase and the W phase.

  Next, the operation after detecting the failure of the switching element will be described.

(Display failure information)
Although not shown in the figure, the inverter device 101 uses the failure information of the switching element detected by the failure determination unit 10 (which switching element has failed, a short-circuit failure or an open failure), for example, a PC (personal computer). ), Etc., and can be displayed on a PC display or the like. As a result, the failure information can be surely grasped, so that the information useful for the recovery work can be obtained.

(Operation at the time of short-circuit failure)
In the inverter device 101, when the switching element 31 or the switching element 32 is short-circuited, the changeover switch 7a (7b, 7c) switches the terminal C from the terminal A to the terminal B, that is, the smoothing capacitor 2a and the smoothing capacitor 2b. A neutral point N1 (a point at which DC voltage is equally divided) and the electric motor 11 are electrically connected, the phase voltage of the failed U phase is set to zero, and the remaining two phases (V phase, Single phase operation 1 in W phase) is enabled. In the single-phase operation 1, the voltage range that can be output is limited to half of the normal time.

(Operation at open failure)
In the inverter device 101, when the switching element 31 or the switching element 32 has an open failure, the changeover switch 7a (7b, 7c) keeps the terminal C connected to the terminal A and the open side of the arm on the opposite side where the open failure has occurred. The gate signal is always off, and single phase operation 2 with the remaining two phases (V phase and W phase) is enabled. In single-phase operation 2, the current range that can be output is limited to 1 / √3 of normal. In addition, when it determines with the single-phase driving | operation 2, you may drive | operate as the single-phase driving | operation 1 by changing to the connection demonstrated by (operation | movement at the time of a single phase failure).

(Operation when the DC voltage source is shut off)
When the DC voltage source 1 is cut off or disconnected from the smoothing capacitors 2a and 2b, the inverter device 101 performs an operation with the current command or voltage command set to zero while the motor 11 is not rotating, and is stored in the smoothing capacitors 2a and 2b. A process for discharging the charged electric charge is performed. When it is determined by the failure determination unit 10 that the switching elements 31 to 36 have not failed, the current command or voltage is used by using all of the switching elements 31 to 36 without performing the following limited operations. The operation with the command set to zero is performed to discharge the charges accumulated in the smoothing capacitors 2a and 2b. In addition, you may discharge-process so that some switching elements may not be used among the switching elements 31-36 in the range which is not short-circuited up and down.

  When it is determined by the failure determination unit 10 that one of the switching element 31 or the switching element 32 has an open failure, the opposite side of the switching element (for example, the switching element 31) that is paired with the open failure The switching element (switching element 32) of the arm maintains the OFF state, and switching elements 33 to 36 of phases (V phase, W phase) different from the phase (U phase) of the switching element (switching element 31) that has failed open. A gate signal for operating only the current command or the voltage command is given to give an operation. As a result, the charges accumulated in the smoothing capacitors 2a and 2b are discharged.

  In addition, when it is determined by the failure determination unit 10 that one of the switching element 31 or the switching element 32 is short-circuited, the reverse of the pair that is paired with the switching element that is short-circuited (for example, the switching element 31). The switching element (switching element 32) of the arm on the side maintains the OFF state, and is in a phase different from the phase of the switching element (switching element 31) that is short-circuited, and the switching elements (switching elements 34 and 36) on the opposite side. ) Only the gate signal to operate is given, and the operation with the current command or voltage command set to zero is performed. As a result, the charges accumulated in the smoothing capacitors 2a and 2b are discharged.

  In this way, when operating with the current command or voltage command set to zero, the charges accumulated in the smoothing capacitors 2a and 2b can be discharged without using a faulty switching element.

  In the above description, the failure determination is performed using the PWM signals Su, Sv, Sw, but the failure determination can be performed using the gate signals Gup, Gvp, Gwp, or Gun, Gvn, Gwn. In other words, the PWM signals Su, Sv, Sw and the gate signals Gup, Gvp, Gwp are different signals to which a dead time is added, and thus are similarly implemented only by changing the time at which the carry signal is output from the counter 45. it can. When the gate signals Gun, Gvn, and Gwn are used, it can be implemented by inverting the signal and changing the time when the carry signal from the counter 45 is output.

  Since the inverter device 101 according to the first embodiment and the electric motor drive device 100 having the same are configured as described above, the following effects are obtained.

  Since the short circuit failure of the switching elements 31 to 36 can be determined without using a fuse, the circuit of the inverter device 101 can be configured easily. Further, the faulty switching element can be specified, and the fault of the switching element can be determined up to the distinction between a short circuit fault and an open fault. In addition, since the switching element can be shortened until it is detected, secondary destruction of the power conversion unit can be prevented.

  Furthermore, even when the switching element is broken, when the DC voltage source is shut off, the charge accumulated in the smoothing capacitor can be reliably discharged, and the failed switching element can be replaced safely. In addition, since the detected failure information of the switching element (which switching element has failed, whether it is a short-circuit failure or an open-circuit failure) can be reliably grasped, recovery work such as replacement of the switching element can be performed safely and reliably.

  Thus, the emergency operation can be easily performed without using the failed switching element. This is effective when it is necessary to continue operation even if the drive performance is lower than normal.

(Second Embodiment)
Next, the inverter apparatus 102 of 2nd Embodiment is demonstrated with reference to FIG. FIG. 3 is a block diagram showing the configuration of the inverter device 102 according to the second embodiment of the present invention.

  The inverter device 102 according to the second embodiment includes a failure determination unit 53 instead of the failure determination unit 10. In the following, for convenience of explanation, the description overlapping with that of the first embodiment will be omitted as appropriate, and different points will be mainly described.

Similarly to the first embodiment, the power conversion unit 3 converts the DC voltage from the DC voltage source 1 into AC by PWM control and outputs the voltage commands Vu ^* , Vv ^* , and Vw ^* to the electric motor 11. At this time, the gate drive circuit 6 is configured to output the gate signals Gup, Gun, Gvp, Gvn, Gwp, Gwn to the switching elements 31, 32, 33, 34, 35, 36 and the failure determination unit 53, respectively. Has been. The voltage detector 8 and the current detector 9 output the voltage detection signals Vu, Vv, Vw and the current detection signals Iu, Iv, Iw to the failure determination unit 53, respectively, as in the first embodiment. It is configured.

  The failure determination unit 53 determines the polarities of the voltage detection signals Vu, Vv, and Vw, and generates voltage polarity signals Vu_pol, Vv_pol, and Vw_pol. Similarly, the polarity of the current detection signals Iu, Iv, and Iw is determined, and current polarity signals Iu_dir, Iv_dir, and Iw_dir are generated. Further, the failure determination unit 53 uses the gate signals Gup, Gun, Gvp, Gvn, Gwp, Gwn, the voltage polarity signals Vu_pol, Vv_pol, Vw_pol, and the current polarity signals Iu_dir, Iv_dir, Iw_dir, as shown in FIGS. Based on the truth table shown, the failure information of the switching elements 31 to 36 is determined as in the first embodiment. In the truth tables shown in FIGS. 4 to 9, the positive polarity is indicated as H, and the negative polarity is indicated as L.

  Next, the failure determination operation using the gate signal Gup of the upper arm switching element 31 performed by the failure determination unit 53 will be described with reference to FIG. FIG. 4 is a truth table for failure determination based on the gate signal Gup of the inverter device 102.

(Normal)
The failure determination unit 53 is shown in FIG. 4 when an H level gate signal Gup is supplied to the switching element 31, that is, when an ON command is given to the switching element 31 and the U-phase voltage polarity signal Vu_pol is positive. Based on the truth table, it is determined that the switching element 31 has not failed. The same applies when the L-level gate signal Gup is supplied to the switching element 31 and the U-phase voltage polarity signal Vu_pol becomes negative.

(At the time of failure judgment when the gate signal is H level)
The failure determination unit 53 supplies the switching element 31 with the H-level gate signal Gup, that is, if the U-phase voltage polarity signal Vu_pol is negative in spite of being given an ON command to the switching element 31. It is determined that a failure has occurred.

  The failure determination unit 53 determines that the switching element 31 has an open failure when the U-phase current polarity signal Iu_dir is positive. When this determination is made, the changeover switch 7a (7b, 7c) always keeps the gate signal Gun of the switching element 32 at the L level (off) while the terminal C is connected to the terminal A, and the remaining two phases (V phase, Single phase operation 2 in W phase) is enabled.

  Further, when the U-phase current polarity signal Iu_dir has a negative polarity, the failure determination unit 53 determines that the switching element 31 has an open failure and the switching element 32 has a short-circuit failure. When this determination is made, the changeover switch 7a (7b, 7c) switches the connection of the terminal C from the terminal A to the terminal B, that is, the neutral point N1 (DC direct current) between the smoothing capacitor 2a and the smoothing capacitor 2b. Single phase operation 1 in the remaining two phases (V phase, W phase) with the phase voltage of the failed U phase set to zero by switching to a state in which the voltage is equally divided) and the electric motor 11 Is possible.

(At the time of failure judgment when the gate signal is L level)
The failure determination unit 53 receives the L-level gate signal Gup to the switching element 31, that is, if the U-phase voltage polarity signal Vu_pol is positive even though the switching element 31 is given an off command. Judge that it is out of order.

  The failure determination unit 53 determines that the switching element 31 has a short circuit failure when the U-phase current polarity signal Iu_dir is positive. When this determination is made, the changeover switch 7a (7b, 7c) switches the connection of the terminal C from the terminal A to the terminal B, that is, the neutral point N1 (DC direct current) between the smoothing capacitor 2a and the smoothing capacitor 2b. Single phase operation 1 in the remaining two phases (V phase, W phase) with the phase voltage of the failed U phase set to zero by switching to a state in which the voltage is equally divided) and the electric motor 11 Is possible.

  Further, when the U-phase current polarity signal Iu_dir has a negative polarity, the failure determination unit 53 determines that a current is flowing through the diode Bup (see FIG. 3) of the switching element 31, and the switching element 32 is opened. Determine that there is a failure. When this determination is made, the changeover switch 7a (7b, 7c) always keeps the gate signal Gun of the switching element 32 at the L level (off) while the terminal C is connected to the terminal A, and the remaining two phases (V phase, Single phase operation 2 in W phase) is enabled.

  Next, the failure determination operation using the gate signal Gun of the switching element 32 of the lower arm performed by the failure determination unit 53 will be described with reference to FIG. FIG. 5 is a truth table for failure determination based on the gate signal Gun of the inverter device 102.

(Normal)
The failure determination unit 53 is shown in FIG. 5 when an H level gate signal Gun is supplied to the switching element 32, that is, when an ON command is given to the switching element 32 and the U-phase voltage polarity signal Vu_pol is negative. Based on the truth table, it is determined that the switching element 32 has not failed. The same applies when the L-level gate signal Gun is supplied to the switching element 32 and the U-phase voltage polarity signal Vu_pol becomes positive.

(At the time of failure judgment when the gate signal is H level)
The failure determination unit 53 receives the H level gate signal Gun to the switching element 32, that is, the U phase voltage polarity signal Vu_pol is positive even though the ON signal is given to the switching element 32. Judge that it is out of order.

  When the U-phase current polarity signal Iu_dir is positive, failure determination unit 53 determines that switching element 31 has a short circuit failure and switching element 32 has an open failure. When this determination is made, the changeover switch 7a (7b, 7c) switches the connection of the terminal C from the terminal A to the terminal B, that is, the neutral point N1 (DC direct current) between the smoothing capacitor 2a and the smoothing capacitor 2b. Single phase operation 1 in the remaining two phases (V phase, W phase) with the phase voltage of the failed U phase set to zero by switching to a state in which the voltage is equally divided) and the electric motor 11 Is possible.

  The failure determination unit 53 determines that the switching element 32 has an open failure when the U-phase current polarity signal Iu_dir has a negative polarity. When this determination is made, the changeover switch 7a (7b, 7c) always sets the gate signal Gup of the switching element 31 to the L level (off) while the terminal C is connected to the terminal A, and the remaining two phases (V phase, Single phase operation 2 in W phase) is enabled.

(At the time of failure judgment when the gate signal is L level)
When the switching element 32 is supplied with the L-level gate signal Gun, that is, the failure determination unit 53 is in a case where the U-phase voltage polarity signal Vu_pol has a negative polarity even though an OFF command is given to the switching element 32. It is determined that a failure has occurred.

  The failure determination unit 53 determines that the switching element 32 has an open failure when the U-phase current polarity signal Iu_dir is positive. When this determination is made, the changeover switch 7a (7b, 7c) always sets the gate signal Gup of the switching element 31 to the L level (off) while the terminal C is connected to the terminal A, and the remaining two phases (V phase, Single phase operation 2 in W phase) is enabled.

  The failure determination unit 53 determines that the switching element 32 has a short-circuit failure when the U-phase current polarity signal Iu_dir has a negative polarity. When this determination is made, the changeover switch 7a (7b, 7c) switches the connection of the terminal C from the terminal A to the terminal B, that is, the neutral point N1 (DC direct current) between the smoothing capacitor 2a and the smoothing capacitor 2b. Single phase operation 1 in the remaining two phases (V phase, W phase) with the phase voltage of the failed U phase set to zero by switching to a state in which the voltage is equally divided) and the electric motor 11 Is possible.

  Note that the restrictions during operation in the single-phase operations 1 and 2 are the same as those in the first embodiment.

  The failure determination operation (see FIG. 6) using the gate signal Gvp of the failure determination unit 53 and the failure determination operation (see FIG. 8) using the gate signal Gwp are the failure determination operation using the gate signal Gup. It is the same. The failure determination operation using the gate signal Gvn of the failure determination unit 53 (see FIG. 7) and the failure determination operation using the gate signal Gwn (see FIG. 9) are the failure determination operations using the gate signal Gun. It is the same. The operation when the DC voltage source 1 is cut off is the same as that in the first embodiment.

  As described above, in the second embodiment, the failure type determination can be performed based on the gate signal, the voltage polarity signal, and the current polarity signal instead of the additional operation as in the first embodiment.

  The effect of the second embodiment is the same as that of the first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, the failure detection in the first embodiment may be combined with the failure type determination in the second embodiment, and the failure detection process (a part or all of the failure determination process) may be performed by hardware. It does not matter which of the software processes.

  In the first and second embodiments, the DC voltage source supplies the direct current by rectifying the AC power supply using the rectifier circuit. However, the present invention is not limited to this, and the rectifier circuit is used instead. It may be a PWM converter. Further, for example, a DC power source such as a battery may be used as the DC voltage source 1a as in the inverter device 103 of the modification shown in FIG.

  In addition, when the failure determination unit 10 or 53 determines that the switching element has failed, the inverter device stops operation in the base block process, and then performs failure determination and switching of the changeover switches 7a, 7b, and 7c. Also good. Note that the switching of the changeover switches 7a, 7b, and 7c may be automatic processing or manual processing. Furthermore, it goes without saying that the present invention can be implemented if the change-over switches 7a, 7b, 7c are not provided and the connection described above can be implemented by changing the wiring or the like.

  In the first and second embodiments, an example in which a three-phase AC power is output using a three-phase AC power supply has been described. However, the present invention is not limited to this. The present invention can be applied to an inverter device that uses an AC power supply having a number of phases other than three phases, and is also applicable to an inverter device that outputs an alternating current having a number of phases other than three phases.

  In the first and second embodiments, the example in which the switching element including the IGBT is used as the switching element has been described. However, the present invention is not limited to this. For example, a switching element including a MOSFET (field effect transistor) may be used as the switching element.

  Moreover, although the example which connects an electric motor to an inverter apparatus as a load was shown in the said 1st and 2nd embodiment, this invention is not limited to this. In the present invention, a load other than the electric motor may be connected to the inverter device.

DESCRIPTION OF SYMBOLS 1, 1a DC voltage source 2a, 2b Smoothing capacitor 3 Power conversion part 8 Voltage detector 9 Current detector 10, 53 Failure determination part 11 Electric motor 31, 32, 33, 34, 35, 36 Switching element 100 Electric motor drive system 101, 102, 103 Inverter device

Claims (13)

  A DC voltage source;
  A power converter that includes a plurality of switching elements, controls the plurality of switching elements by a gate signal based on a PWM signal, and converts a direct current supplied from the direct-current voltage source into a plurality of phases of alternating current;
  A voltage detector that detects an output voltage of the power converter and outputs a voltage detection signal;
  A failure determination unit that determines failure of the switching element based on the PWM signal or the gate signal and the voltage detection signal;
  The plurality of switching elements are configured to be driven by a gate signal generated by including a dead time in the PWM signal,
  The failure determination unit determines that the switching element has failed when a time when the polarities of the voltage detection signal and the PWM signal do not match is greater than a predetermined time equal to or greater than the dead time. An inverter device configured as described above. The failure determination unit, in a state where the PWM signal does not change, when the polarity of the voltage detection signal has changed, the switching element is configured to determine that has failed, according to claim 1 Inverter device. A current detector for detecting an output current of the power conversion unit and outputting a current detection signal;
3. The device according to claim 1, wherein the failure determination unit is configured to determine whether the switching element has a short circuit failure or an open failure based on at least the current detection signal. Inverter device. The failure determination unit is configured to determine whether the switching element has a short-circuit failure or an open-circuit failure based on polarities of the current detection signal and the voltage detection signal. 3. The inverter device according to 3 . A smoothing capacitor provided between the DC voltage source and the power conversion unit, for smoothing the DC input to the power conversion unit;
When shutting down the DC voltage source, if it is determined by the failure determination unit that the switching element has not failed, the charge accumulated in the smoothing capacitor is discharged using all of the switching element. The inverter apparatus of Claim 3 or 4 comprised . A smoothing capacitor provided between the DC voltage source and the power conversion unit, for smoothing the DC input to the power conversion unit;
When the failure determination unit determines that the switching element has an open failure when shutting off the DC voltage source, the switching element of the opposite arm that is paired with the switching element having the open failure is turned off. hold state, the open failing with switching elements of a phase different from the phase of the switching device is configured to discharge the charge accumulated in the smoothing capacitor, according to claim 3 or 4 Inverter device. A smoothing capacitor provided between the DC voltage source and the power conversion unit, for smoothing the DC input to the power conversion unit;
When the failure determination unit determines that the switching element is short-circuited when the DC voltage source is shut off, the switching element of the opposite arm that is paired with the switching element that is short-circuited is turned off. The electric charge accumulated in the smoothing capacitor is discharged using a switching element of an arm on the opposite side and in a phase different from the phase of the switching element having a short circuit failure. Item 5. The inverter device according to Item 3 or 4 . Said failure information to the failure by the determination unit identifies the switching element is detected, the which is configured to output the type of fault in switching elements, the inverter apparatus according to any one of claims 3-7 . When a failure of the switching element is detected by the failure determination unit, the output point of the arm of the phase where the failure is detected is connected to a neutral point that substantially divides a DC voltage, and the neutral point The inverter according to any one of claims 1 to 8 , wherein the inverter is configured such that a phase voltage of a phase connected to the zero is made zero and a load can be operated by a switching element other than the phase in which the failure is detected. apparatus. When a failure of the switching element is detected as a short-circuit failure by the failure determination unit, the gate signal of the arm opposite to the switching element in which the short-circuit failure has occurred is always set to L level, and a switching element other than the phase in which the failure is detected It is operable to configure the load, the inverter device according to any one of claims 1-9. A DC voltage source;
A power converter that includes a plurality of switching elements, controls the plurality of switching elements by a gate signal based on a PWM signal, and converts a direct current supplied from the direct-current voltage source into a plurality of phases of alternating current;
A voltage detector that detects an output voltage of the power converter and outputs a voltage detection signal;
A failure determination unit for determining a failure of the switching element based on the PWM signal or the gate signal and the voltage detection signal;
A current detector that detects an output current of the power converter and outputs a current detection signal;
A smoothing capacitor provided between the direct-current voltage source and the power conversion unit, for smoothing the direct current input to the power conversion unit,
The failure determination unit is configured to determine whether the switching element has a short circuit failure or an open failure based on at least the current detection signal,
When the failure determination unit determines that the switching element is short-circuited when the DC voltage source is shut off, the switching element of the opposite arm that is paired with the switching element that is short-circuited is turned off. An inverter configured to discharge the electric charge accumulated in the smoothing capacitor using a switching element of an arm on the opposite side and in a phase different from a phase of the switching element in which the short circuit failure occurs. apparatus. A DC voltage source;
A power converter that includes a plurality of switching elements, controls the plurality of switching elements by a gate signal based on a PWM signal, and converts a direct current supplied from the direct-current voltage source into a plurality of phases of alternating current;
A voltage detector that detects an output voltage of the power converter and outputs a voltage detection signal;
A failure determination unit that determines failure of the switching element based on the PWM signal or the gate signal and the voltage detection signal;
When a failure of the switching element is detected as a short-circuit failure by the failure determination unit, the gate signal of the arm opposite to the switching element in which the short-circuit failure has occurred is always set to L level, and a switching element other than the phase in which the failure is detected An inverter device configured to be able to operate a load by means of.   A DC voltage source;
  A power converter that includes a plurality of switching elements, controls the plurality of switching elements by a gate signal based on a PWM signal, and converts direct current supplied from the direct current voltage source into alternating current of a plurality of phases; and the power conversion unit A voltage detector that detects the output voltage of the switching element and outputs a voltage detection signal; a failure determination unit that determines a failure of the switching element based on the PWM signal or the gate signal and the polarity of the voltage detection signal; An inverter device comprising:
  An electric motor connected to the inverter device,
  The plurality of switching elements are configured to be driven by a gate signal generated by including a dead time in the PWM signal,
  The failure determination unit determines that the switching element has failed when a time when the polarities of the voltage detection signal and the PWM signal do not match is greater than a predetermined time equal to or greater than the dead time. An electric motor drive system configured as described above.

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