JP5694673B2 - Display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display device and a manufacturing method thereof, and more particularly to a display device including a thin film transistor on a substrate and a manufacturing method thereof.

  The display device includes a large number of pixels arranged in a matrix in the display unit, and displays an image by independently driving these pixels.

  In this case, when the display device is a liquid crystal display device, each pixel includes, for example, a thin film transistor including a switching element for selecting a pixel group including pixels arranged in parallel in the row direction along the column direction. When the display device is an organic EL display device, each pixel includes a thin film transistor including a current control element in addition to the switching element described above. Further, a peripheral circuit for driving each pixel by supplying a signal or the like to each pixel is formed on the same substrate on which the display unit is formed, around the display unit of the display device. A large number of thin film transistors are provided.

  When a semiconductor film of a thin film transistor is formed on a substrate, polycrystalline silicon or microcrystalline silicon with good crystallinity has been used in place of conventional amorphous silicon. For example, Patent Document 1 below discloses a technique for forming polycrystalline silicon using a reactive thermal CVD method. Here, the reactive thermal CVD method is a method in which a semiconductor hydrogenation gas and a halogenated gas are chemically reacted on the substrate surface to form a polycrystalline film directly on the substrate.

The thin film transistor disclosed in Patent Document 1 has a bottom gate structure in which after forming a gate insulating film on a substrate on which a gate electrode is formed, a polycrystalline semiconductor thin film is formed. Then, the polycrystalline semiconductor thin film is formed with a film thickness of 45 nm by the reactive thermal CVD method. In the reactive thermal CVD method, disilane gas (Si ₂ H ₆ ) and fluorine gas ( F ₂ ) and an inert gas such as helium (He) or argon (Ar) or hydrogen gas (H ₂ ) is supplied as a dilution gas.

JP 2005-57098 A

  Here, when forming a uniform polycrystalline silicon film with good crystallinity using reactive thermal CVD, it is important to form high-quality and uniform crystal nuclei on the surface of the insulating film as the underlayer It becomes.

  In this case, for the formation of crystal nuclei, it is indispensable to form Si atom and hydrogen (H) atom bonds as nucleation sites on the surface of the insulating film. It is necessary to supply H atoms.

However, in Patent Document 1 described above, the molecular H ₂ gas is supplied simultaneously with the film forming gas. In reactive thermal CVD, a temperature as low as 450 ° C. to 500 ° C. is usually used, and it is inevitable that the generation efficiency of H atoms from H ₂ molecules is lowered. This makes it difficult for Si atom-H atom bonds to be formed on the surface of the insulating film, lowering the formation density of crystal nuclei on the surface of the insulating film, and causing a disadvantage that a semiconductor film with poor crystallinity is likely to grow. Further, since there are few nucleation sites, a large crystal nucleus and a small crystal nucleus are simultaneously formed on the surface of the insulating film, resulting in inconvenience that the crystal nucleus size varies.

  An object of the present invention is to provide a display device including a thin film transistor having a semiconductor film with good crystallinity and uniform crystal nuclei, and a manufacturing method thereof.

  The configuration of the present invention can be as follows, for example.

(1) A method for manufacturing a display device according to the present invention is a display device including a thin film transistor in which a gate electrode, a gate insulating film, a semiconductor film, and a source / drain electrode are sequentially stacked on a substrate having a display portion. A manufacturing method comprising:
The gate insulating film comprises a first gate insulating film formed on the side close to the substrate, and a second gate insulating film formed so as to cover the surface of the first gate insulating film,
Forming the first gate insulating film;
Forming the second gate insulating film having a hydrogen concentration higher than the hydrogen concentration of the first gate insulating film on the upper surface of the first gate insulating film;
A silicon germanium semiconductor crystal nucleus is directly formed on the upper surface of the second gate insulating film having a hydrogen concentration higher than that of the first gate insulating film by using a reactive thermal CVD method. A step of forming the semiconductor film of silicon germanium, using as a seed ,
The germanium composition ratio of the semiconductor crystal nuclei is higher than that of the semiconductor film, and the semiconductor layer formed on the upper surface of the second gate insulating film is only silicon germanium between the semiconductor crystal nuclei and the semiconductor film. in is formed, characterized in Rukoto.

(2) A display device of the present invention is a display device including a thin film transistor formed by sequentially laminating a gate electrode, a gate insulating film, a semiconductor film, and a source / drain electrode on a substrate having a display portion,
The gate insulating film comprises a first gate insulating film formed on the side close to the substrate, and a second gate insulating film formed so as to cover the surface of the first gate insulating film,
A hydrogen concentration in the second gate insulating film is formed higher than a hydrogen concentration in the first gate insulating film;
The semiconductor film is made of silicon germanium, and a semiconductor crystal nucleus made of silicon germanium is formed on the interface side with the second gate insulating film ,
The germanium composition ratio of the semiconductor crystal nuclei is higher than that of the semiconductor film, and the semiconductor layer formed on the upper surface of the second gate insulating film is only silicon germanium between the semiconductor crystal nuclei and the semiconductor film. in is formed, characterized in Rukoto.

  The above-described configuration is merely an example, and the present invention can be modified as appropriate without departing from the technical idea. Further, examples of the configuration of the present invention other than the above-described configuration will be clarified from the entire description of the present specification or the drawings.

  According to the display device and the manufacturing method thereof configured as described above, a thin film transistor having a semiconductor film with excellent crystallinity can be provided by uniformizing crystal nuclei.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is sectional drawing which shows the structure of the thin-film transistor formed in the board | substrate 1 surface of the display apparatus of this invention. It is a figure which shows the manufacturing method of the structure shown in FIG. 1, and shows a series of processes with FIG. 3, FIG. 4, FIG. It is a figure which shows the manufacturing method of the structure shown in FIG. 1, and shows a series of processes with FIG. 2, FIG. 4, FIG. It is a figure which shows the manufacturing method of the structure shown in FIG. 1, and shows a series of processes with FIG. 2, FIG. 3, FIG. It is a figure which shows the manufacturing method of the structure shown in FIG. 1, and shows a series of processes with FIG. 2, FIG. 3, FIG. 2 is a graph showing a Ge composition ratio in a semiconductor film and showing a distribution along the line A-A ′ in FIG. 1. FIG. 2 is a graph showing a hydrogen concentration graph in a semiconductor film and an insulating film, showing a distribution along the line A-A ′ of FIG. 1. It is a figure which shows the cross section of a liquid crystal display device, and is a figure which showed the other board | substrate arrange | positioned facing the said board | substrate through a liquid crystal other than the board | substrate shown in FIG. It is sectional drawing which shows Example 2 of the display apparatus of this invention. It is explanatory drawing which shows Example 3 of the display apparatus of this invention, and is the graph which showed the hydrogen concentration profile in A-A 'of FIG. It is a graph which shows the result of having investigated the hydrogen concentration profile shown in FIG. 10 by SIMS. It is explanatory drawing which shows Example 4 of the display apparatus of this invention. It is sectional drawing which shows Example 5 of the display apparatus of this invention. It is the graph which showed the hydrogen concentration profile in the B-B 'line of FIG.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each example, the same or similar components are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a cross-sectional view showing a configuration of a thin film transistor TFT formed on a surface of a substrate 1 of a display device of the present invention, for example, a liquid crystal display device. The thin film transistor TFT is a so-called bottom gate type in which the gate electrode is formed as a layer disposed below the semiconductor layer. Further, in FIG. 1, a substrate 1 is one of a pair of substrates disposed with a liquid crystal interposed therebetween, and in this specification, the surface is a surface on the liquid crystal side.

  In FIG. 1, a gate electrode wiring 2 is formed on the surface of a substrate 1. This gate electrode wiring 2 functions as a gate electrode of the thin film transistor TFT in the formation region of the thin film transistor TFT.

  A gate insulating film 3 is formed on the surface of the substrate 1 so as to cover the gate electrode wiring 2. The gate insulating film 3 is made of, for example, a Si oxide film, and as shown in the enlarged view Q of the dotted line frame portion in FIG. Is contained.

  An island-shaped semiconductor film 4 is formed on the gate insulating film 3 in the formation region of the thin film transistor TFT. The semiconductor film 4 is formed so as to straddle the gate electrode wiring 2. The semiconductor film 4 is made of, for example, SiGe. As shown in the enlarged view Q, semiconductor crystal nuclei 4a are formed at the interface of the gate insulating film 3b, and the upper layer of the semiconductor crystal nuclei 4a is a polycrystalline film 4b. Yes. The semiconductor film 4 may be composed of at least one of silicon (Si) and germanium (Ge).

  On the surface of the semiconductor film 4, a source electrode wiring 6 a is formed on a portion of one side of the gate electrode wiring 2 with a portion overlapping with the gate electrode wiring 2 in a plan view. A drain electrode wiring 6b is formed on the other side. The source electrode wiring 6 a is formed so as to overlap the gate electrode wiring 2 at the end on the drain electrode wiring 6 b side and extend from the formation region of the semiconductor film 4 onto the gate insulating film 3. The drain electrode wiring 6 b overlaps with the gate electrode wiring 2 at the end on the source electrode wiring 6 a side, and is formed to extend from the formation region of the semiconductor film 4 onto the gate insulating film 3.

  Note that the names of the drain electrode wiring and the source electrode wiring in the thin film transistor TFT change depending on the bias application state. In this specification, for convenience of explanation, the left electrode wiring in the drawing is referred to as the source electrode wiring and the right electrode wiring in the drawing. Is referred to as a drain electrode wiring.

  Further, a contact layer 5a formed by doping the semiconductor film 4 with a high concentration impurity is formed at the interface between the source electrode wiring 6a and the semiconductor film 4, and at the interface between the drain electrode wiring 6b and the semiconductor film 4. A contact layer 5b formed by doping the semiconductor film 4 with a high-concentration impurity is formed. In the figure, a concave portion is formed on the surface of the semiconductor film 4 between the source electrode wiring 6a and the drain electrode wiring 6b. In the manufacture of the thin film transistor TFT, for example, the source electrode wiring 6a and the drain electrode wiring 6b are used as a mask to etch a high-concentration impurity layer between the source electrode wiring 6a and the drain electrode wiring 6b, thereby separating the contact layer. By going through the planning process.

  A protective film 7 and a protective film 8 are formed on the surface of the substrate 1 so as to cover the thin film transistor TFT configured as described above. The protective film 7 is made of an inorganic insulating film such as SiN, and the protective film 8 is made of an organic insulating film such as resin. The protective film 8 has an effect of flattening the surface.

  A pixel electrode 9 made of, for example, ITO (Indium Tin Oxide) is formed on the upper surface of the protective film 8. The pixel electrode 9 is connected to the protective film 8 and the drain electrode wiring of the thin film transistor TFT through the through hole TH formed in the protective film 7. 6b is electrically connected.

  An alignment film (not shown) is formed on the surface of the substrate 1 so as to cover the pixel electrode 9. This alignment film is a film in contact with the liquid crystal and regulates the initial alignment direction of the molecules of the liquid crystal.

  2 to 5 are process diagrams showing the manufacturing method having the above-described configuration. This process diagram draws up to the formation of the thin film transistor TFT, and omits the formation of the protective film 7, the protective film 8, and the pixel electrode 9. Hereinafter, it demonstrates in order of a process.

  First, as shown in FIG. 2, a substrate 1 made of, for example, glass is prepared, and a gate electrode wiring 2 is formed on the surface of the substrate 1. For example, a metal film made of Nb, Mo, W, Ta, Cr, Ti, Fe, Ni, Co, Al, Cu or the like is formed by a sputtering method, and the gate electrode wiring 2 is formed by selective etching by a photolithography technique. For example, a thickness of 100 nm is appropriate.

  Next, as shown in FIG. 3, a gate insulating film 3 is formed on the surface of the substrate 1 so as to cover the gate electrode wiring 2. The gate insulating film 3 is made of, for example, SiO, SiN, SiON or the like, and is formed by, for example, a plasma CVD method or a sputtering method. Moreover, plasma oxidation, photooxidation, etc. can also be used together. The film thickness is, for example, 50 to 300 nm, thereby reducing the level difference reflected by the gate electrode wiring 2 and ensuring the breakdown voltage as the insulating film.

Here, the gate insulating film 3 is composed of a sequentially laminated film of a gate insulating film 3a and a gate insulating film 3b, and the gate insulating film 3b is a layer containing high-concentration hydrogen. When the thickness of the gate insulating film 3b is dnm and the hydrogen concentration in the gate insulating film 3b is N _H cm ⁻³ , hydrogen is contained so that the relationship of the following formula (1) is satisfied.

d × N _H ≧ 1 × 10 ¹⁴ cm ⁻² (1)
The inclusion of hydrogen in the gate insulating film 3b can be performed, for example, by supplying hydrogen to the atmosphere during film formation when the film is formed by plasma CVD. As another method, hydrogen treatment can be performed after film formation to incorporate hydrogen into the gate insulating film 3b. Here, as a hydrogenation treatment, for example, there is a method of annealing (at a substrate temperature of 300 to 350 ° C. and a pressure of about 1 torr) in an atmosphere of atomic hydrogen or hydrogen plasma.

  Next, the semiconductor crystal nucleus 4 a is formed on the gate insulating film 3. For example, SiGe crystal nuclei are formed as the semiconductor crystal nuclei 4a. For this formation, a reactive thermal CVD method using a redox reaction between a semiconductor hydrogenation gas and a halogenated gas is used. Reactive thermal CVD is a method in which a semiconductor hydrogenation gas and a halogenated gas are chemically reacted on the substrate surface to produce a polycrystalline film directly on the substrate.

Here, Si _n H _{2n + 2} (n> 1) can be used as the semiconductor hydrogenation gas to be supplied. However, since it is necessary to suppress the gas phase reaction of the source gas in order to improve the crystallinity of the film formed by the reactive thermal CVD method, Si _n H _{2n + 2} (n> For example, it is desirable to use high-order Si ₂ H ₆ having high reactivity. For example, GeF ₄ may be used as the halogenated gas. In addition to this, a combination of gases can be used, for example, silanes, germane (GeH ₄ ) and F ₂ , and GeH ₄ and SiF ₄ . For example, when Si ₂ H ₆ and GeF ₄ are used, the gas flow rate ratio may be 0.002 to GeF _4, for example, while Si ₂ H ₆ is 1. The film forming pressure is set to about 10 Pa to 10000 Pa in order to generate crystal nuclei at a certain formation rate or higher. For this reason, a carrier gas such as He, Ar, or H ₂ is introduced during film formation. Of these, for example, if He is selected, the flow rate ratio between Si ₂ H ₆ and He is preferably set to, for example, 1:10 to 5000. The film formation temperature is preferably 300 ° C. or higher at which nucleation occurs, and 600 ° C. or lower in order to prevent deterioration of film crystallinity due to gas phase reaction. An example of film formation conditions is Si ₂ H ₆ flow rate: 0.5 sccm, GeF ₄ flow rate: 0.5 sccm, He flow rate: 1000 sccm, substrate temperature 500 ° C., and total pressure 1300 Pa. The size of the crystal nucleus 4a made of SiGe formed on the gate insulating film 3 by reactive thermal CVD has a lower limit of 10 nm in order to realize good crystallinity in the semiconductor film 4b to be formed next, On the other hand, the upper limit is preferably set to 200 nm or less in order to suppress an increase in surface irregularities. The Ge composition ratio of the SiGe crystal nuclei to be formed can be set to 0 to 100% because Si and Ge are completely dissolved.

  Subsequently, the semiconductor film 4b is formed. In this case, the semiconductor film 4b grows using the semiconductor crystal nucleus 4a as a seed. The semiconductor film 4b is made of Si or SiGe and is formed as a microcrystalline film or a polycrystalline film. Here, the microcrystalline film refers to a film composed of fine crystal grains having a grain size of 1 to 30 nm. A polycrystalline film is a film composed of crystal grains having a grain size of 30 nm or more.

The film formation conditions for the semiconductor film 4b may be the same as the film formation conditions for the semiconductor crystal nucleus 4a. However, for example, even if the flow rate of Si ₂ H ₆ is increased to 1.5 sccm, crystal growth is possible because the base is the semiconductor crystal nucleus 4a. The film thickness of the semiconductor film 4b is preferably adjusted to 100 to 300 nm by adding the film thickness of the semiconductor crystal nucleus 4a. This is because it is necessary to etch the semiconductor film 4 using the source electrode wiring and the drain electrode wiring as a mask in a subsequent process, thereby avoiding that the semiconductor film 4 becomes too thin to maintain the transistor characteristics. It is.

  Here, FIG. 6 shows a graph of the Ge composition ratio in the semiconductor film 4 and shows the distribution along the line A-A ′ of FIG. 1. The horizontal axis represents the depth (nm), and the vertical axis represents the Ge composition ratio (%). On the horizontal axis, the positions of the semiconductor film 4b, the semiconductor crystal nucleus 4a, the insulating film 3b, and the insulating film 3a are shown in association with each other.

The semiconductor crystal nuclei 4a are formed under the film formation conditions described above, and the formation conditions of the semiconductor film 4b are the same as the film formation conditions except that the Si ₂ H ₆ flow rate is 1.5 sccm. In FIG. 6, the semiconductor crystal nucleus 4a is a SiGe crystal nucleus having a Ge composition ratio of about 20%. Further, the semiconductor film 4b is a SiGe film having a Ge composition ratio of about 15%. In film formation by the reactive thermal CVD method, when the semiconductor crystal nucleus 4a and the semiconductor film 4b are compared, the semiconductor crystal nucleus 4a has a higher Ge composition ratio. The reason why the Ge composition ratio is high in the semiconductor crystal nucleus 4a is that GeF ₄ reacts more easily than Si ₂ H ₆ in the Si atom-H atom bond formed on the surface of the gate insulating film 3b which is the base layer. Because. Then, Ge generated by this reaction gathers to form semiconductor crystal nuclei 4a having a high Ge composition ratio. However, the Ge composition ratios in the semiconductor crystal nuclei 4a and the semiconductor film 4b are not limited to the above values, and various values can be obtained by adjusting the flow rate ratio of the source gas, for example, Si ₂ H ₆ and GeF ₄ and the film formation temperature. Will be controlled by the value of.

7 shows a graph of the hydrogen concentration in the semiconductor film 4 and the insulating film 3, and shows a distribution along the line AA ′ in FIG. The horizontal axis represents depth (nm) and the vertical axis represents hydrogen concentration. On the horizontal axis, the positions of the semiconductor film 4b, the semiconductor crystal nucleus 4a, the insulating film 3b, and the insulating film 2a are shown in association with each other. As is apparent from FIG. 7, the hydrogen concentration in the insulating film 3b is 10 × 10 ²⁰ cm ⁻³ , which is higher than the hydrogen concentration in the insulating film 3a.

Then, as shown in FIG. 4, a high concentration semiconductor layer 5 made of an n ⁺ Si film is formed on the semiconductor film 4 by using, for example, plasma CVD. For example, the high-concentration semiconductor layer 5 is formed by using a plasma frequency of 13.56 MHz, supplying hydrogen-diluted 10% monosilane (SiH ₄ ) at 100 sccm, setting the substrate temperature to 200 ° C., and the gas pressure to 133 Pa. Phosphine (PH ₃ ) or a hydrogen dilution gas (PH ₃ / H ₂ ) may be supplied as an n-type doping gas. The impurity doping concentration is about 1 × 10 ¹⁷ cm ⁻³ in order to form a low-resistance contact layer with an n ⁺ Si film thickness of about 20 nm, and the crystallinity deteriorates due to dopant atom clustering and segregation. In order to suppress the increase in resistance, it is desirable to set it to 1 × 10 ²² cm ⁻³ or less. Thereafter, the stacked film including the high-concentration semiconductor layer 5 and the semiconductor film 4 is processed into an island shape by performing selective etching using a photolithography technique.

  Further, as shown in FIG. 5, a metal film is formed on the surface of the substrate 1 by using, for example, a sputtering method. For example, Nb, Mo, W, Ta, Cr, Ti, Fe, Ni, Co, or the like is used as the material of the metal film. Moreover, an alloy of these metals and a laminated film of these metals can be used. Moreover, in order to lower the upper limit temperature of the process, a low resistance metal such as Al or Cu can be used. The metal film is formed with a thickness of about 500 nm to reduce wiring resistance. Then, the metal film is selectively etched by a photolithography technique to form a source electrode wiring 6a and a drain electrode wiring 6b. Further, using the source electrode wiring 6a and the drain electrode wiring 6b as a mask, all of the high-concentration semiconductor layer 5 exposed from the source electrode wiring 6a and the drain electrode wiring 6b and the semiconductor layer 4 below the high-concentration semiconductor layer 5 are used. A part of the surface side of the substrate is etched. Thus, the high-concentration semiconductor layer 5 is formed as a contact layer 5a interposed at the interface between the source electrode wiring 6a and the semiconductor layer 4, and the contact layer interposed at the interface between the drain electrode wiring 6b and the semiconductor layer 4 5b is formed. Thereby, a thin film transistor TFT is formed.

  Thereafter, as shown in FIG. 1, a protective film 7 made of, for example, a SiN film is formed on the surface of the substrate 1 by a plasma CVD method so as to cover the thin film transistor TFT. The film thickness is, for example, 500 nm. Next, a protective film 8 made of, for example, an organic resin is formed on the protective film 7. Thereafter, a contact hole TH is formed in the protective film 8 and the protective film 7 by selective etching using a photolithography technique, and a part of the drain electrode wiring 6b of the thin film transistor TFT is exposed. Then, for example, an ITO (Indium Tin Oxide) film is formed on the surface of the substrate 1 by a sputtering method, and the ITO film is selectively etched by a photolithography technique to form the pixel electrode 9. The film thickness of the pixel electrode 9 is preferably about 100 nm, for example.

  FIG. 8 is a diagram showing a cross section of the liquid crystal display device, and also shows a substrate 25 arranged opposite to the substrate 1 with a liquid crystal 27 in addition to the substrate 1 shown in FIG. An alignment film 20 is formed on the surface of the substrate 1 in contact with the liquid crystal 27 so as to cover the pixel electrode 9. The alignment film 20 is a film for regulating the initial alignment of the molecules of the liquid crystal 27. On the liquid crystal side surface of the substrate 25, a color filter layer 21, an overcoat layer 22, a counter electrode 23 made of an ITO film, and an alignment film 24 are sequentially formed. A spacer 26 is disposed between the substrate 1 and the substrate 25, and the gap between the substrate 1 and the substrate 25 is made uniform by the spacer 26, so that the layer thickness of the liquid crystal 27 is made uniform.

  FIG. 9 is a sectional view showing Example 2 of the display device of the present invention. The display device shown in FIG. 6 is an organic LE display device. Also in the organic EL display device, a thin film transistor TFT is formed on the substrate 1. The configuration of the thin film transistor TFT is the same as that of the thin film transistor TFT shown in FIG. 1, and the manufacturing method thereof is the same as that shown in FIGS. 2 to 5, for example. The thin film transistor TFT of the liquid crystal display device of FIG. 1 is shown as a switching element for pixel selection, but the thin film transistor TFT of the organic EL display device of FIG. 9 is shown as a current control element. The source electrode wiring 6a of the thin film transistor TFT in the figure is connected to a power supply line (not shown). Although the organic EL display device also includes a switching element for pixel selection, the switching element is not shown in FIG.

  In FIG. 9, a charge transport layer 10, a light emitting layer 11, a charge transport layer 12, and an upper electrode 13 are laminated on the upper surface of the pixel electrode 9 formed by being electrically connected to the drain electrode wiring 6 b of the thin film transistor TFT. Is formed. For example, when the light from the light emitting layer 11 is irradiated upward in the drawing, the pixel electrode 9 can be formed of a metal film, and the upper electrode 13 can be formed of ITO. Further, the surface of the substrate 1 thus formed is covered with a sealing layer 14 formed by, for example, vapor deposition or sputtering.

  FIG. 10 is an explanatory view showing Embodiment 3 of the display device of the present invention. FIG. 10 is a diagram drawn corresponding to FIG. 7 and shows a hydrogen concentration profile at A-A ′ of FIG. 1.

In FIG. 10, the configuration different from the case of FIG. 7 is that the hydrogen concentration in the semiconductor crystal nucleus 4a is one digit higher (1 × 10 ²⁰ cm ⁻³ ). In Example 3, the semiconductor crystal nucleus 4a is formed at 450 to 500 ° C., for example, by using, for example, Si ₂ H ₆ —GeF ₄ reactive thermal CVD. When the semiconductor crystal nucleus 4a is formed at this temperature, hydrogen contained in the underlying insulating film 3b is desorbed, and this hydrogen can be taken into the semiconductor crystal nucleus 4a. Here, the result of examining the hydrogen concentration profile shown in FIG. 10 by SIMS is shown in FIG. FIG. 11 also shows the Ge composition ratio. The hydrogen concentration in the Si oxide film (insulating film 3b) is approximately 1 × 10 ²¹ cm ⁻³ . Further, it can be seen that hydrogen of about 1 × 10 ²⁰ cm ⁻³ or more is also taken into the SiGe crystal nucleus (semiconductor crystal nucleus 4a). At this hydrogen concentration, the peak concentration of about 3 × 10 ²¹ cm ^{−3 at} the interface between the Si oxide film (insulating film 3b) and the SiGe crystal nucleus (semiconductor crystal nucleus 4a) is a value estimated to be higher by SIMS analysis. And may differ from the actual concentration. From this result, it is possible to incorporate hydrogen into the SiGe crystal nucleus (semiconductor crystal nucleus 4a) using hydrogen desorption during film formation by reactive thermal CVD by including hydrogen in the insulating film. I understand. From the Ge composition ratio profile, Ge is about 23% in the SiGe crystal nucleus (semiconductor crystal nucleus 4a) and about 17% in the microcrystalline SiGe film, and the Ge in the SiGe nucleus is actually higher. It can be seen that it has a composition ratio. In addition, in the hydrogenation treatment of the semiconductor crystal nucleus 4a, as a method other than the above-described method, for example, in the hydrogen molecule, atomic hydrogen, or hydrogen plasma atmosphere shown in Example 1 after the formation of the semiconductor crystal nucleus 4a. There are annealing in the.

The effects of the third embodiment are as follows. In the bottom gate type thin film transistor TFT, the interface of the semiconductor film 4 on the gate insulating film 3 side becomes a channel. For this reason, when the defect level density in this portion is large, carriers are trapped in the defect level, the mobility is lowered in the thin film transistor TFT, and the threshold voltage _Vth is likely to increase. On the other hand, in Example 3, the defect level existing on the surface or inside of the semiconductor crystal nucleus 4a is terminated with hydrogen. Therefore, the characteristics of the thin film transistor TFT can be improved.

  FIG. 12 is an explanatory view showing Embodiment 4 of the display device of the present invention. FIG. 12 is a diagram drawn corresponding to FIG. 10 and shows a hydrogen concentration profile at A-A ′ in FIG. 1.

In FIG. 12, the configuration different from the case of FIG. 10 is that the hydrogen concentration in the semiconductor film 4b is one digit higher (1 × 10 ²⁰ cm ⁻³ ). In Example 4, the semiconductor film 4b is formed at 450 to 500 ° C., for example, by using, for example, Si ₂ H ₆ —GeF ₄ reactive thermal CVD. When the semiconductor film 4b is formed at this temperature, hydrogen contained in the underlying insulating film 3b is desorbed, and the hydrogen concentration in the insulating film 3b is increased as compared with the case of Example 3, and further, reactive thermal CVD is performed. If the temperature is lowered, hydrogen can be easily taken into the semiconductor film 4b. Note that in the hydrogenation treatment of the semiconductor film 4b, as a method other than the above-described method, for example, in the hydrogen molecule, atomic hydrogen, or hydrogen plasma atmosphere described in the first embodiment after the formation of the semiconductor film 4b. There are annealing. When the hydrogenation treatment is performed after the formation of the semiconductor film 4b as described above, the hydrogenation of the semiconductor crystal nuclei 4a can be simultaneously performed by adjusting the annealing conditions, and after the formation of the semiconductor crystal nuclei 4a as shown in the third embodiment. It is not always necessary to perform the hydrotreatment once. For this reason, the number of process steps can be reduced as compared with the case of the third embodiment.

By doing this, not only the semiconductor crystal nuclei 4a but also the defect levels in the semiconductor film 4b are hydrogen-terminated, so that the mobility of the bottom gate type thin film transistor TFT is further improved than in the third embodiment. The threshold value _Vth can be reduced. In addition, by including a high concentration of hydrogen in the semiconductor film 4b, the defect level is terminated with hydrogen, so that the movement of carriers is suppressed and the off-state current of the thin film transistor TFT can be reduced.

  FIG. 13 is a diagram showing Example 5 of the display device of the present invention, and is a diagram drawn in correspondence with FIG.

  In FIG. 13, the semiconductor film 104, 105 has a different structure compared to the case of FIG. 1, and these semiconductor films 104, 105 are sequentially stacked to form a semiconductor layer of the thin film transistor TFT. Other configurations are the same as those in FIG. 1, and the same reference numerals as those in FIG.

  The lower semiconductor layer 104 is composed of the semiconductor crystal nuclei 104a and the semiconductor film 104b as in the case of FIG. 1, but the film thickness is thinner than that in FIG.

  The upper semiconductor film 105 is formed by, for example, a plasma CVD method, and is constituted by a hydrogenated amorphous Si film. Although the film formation temperature can be room temperature or higher, it is necessary to ensure a film formation rate above a certain level in order to improve the manufacturing throughput of the thin film transistor TFT, and it is desirable that the film formation temperature be 200 ° C. or higher. In order to suppress separation as much as possible, the temperature is preferably 500 ° C. or lower.

  The thickness of the upper semiconductor film 105 is preferably adjusted to 100 to 300 nm in combination with the thickness of the semiconductor film 104. This is because, after the formation of the semiconductor layer, etching is performed when forming the source electrode wiring 6a and the drain electrode wiring 6b of the thin film transistor TFT, so that the semiconductor film 104 becomes so thin that the characteristics of the thin film transistor TFT cannot be maintained. This is to avoid this.

In order to promote the hydrogen termination of the defect level formed in the lower semiconductor film 104, the upper semiconductor film 105 contains 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less of hydrogen. It is desirable that In order to form a hydrogenated amorphous Si film as the upper semiconductor film 105, for example, a plasma frequency of 13.56 MHz is used, hydrogen diluted 10% monosilane (SiH ₄ ) is supplied at 100 sccm, a substrate temperature of 200 ° C., gas The pressure may be set to 133 Pa.

Since the crystallized semiconductor film 104 is a lower layer, a microcrystalline Si film may be formed as the upper semiconductor film 105. Here, in order to form the microcrystalline Si film, for example, a plasma frequency of 13.56 MHz is used, and fluorinated silane (SiF ₄ ): H ₂ = 3: 1, a substrate temperature of 250 ° C., and a gas pressure of 40 Pa are used. That's fine.

FIG. 14 shows a hydrogen concentration profile along the line BB ′ in FIG. When comparing FIG. 14 with the case of FIG. 12 shown in Example 4, the hydrogen concentration is 1 × 10 ²⁰ cm ⁻³ in both the semiconductor film 104b and the semiconductor film 105 which are stacked bodies. Have a difference.

  According to the configuration shown in the fifth embodiment, for example, hydrogenated amorphous Si is formed as the upper semiconductor film 105, so that the lower semiconductor film 104 is hydrogenated during the formation of the semiconductor film 105. Become. Alternatively, hydrogen can be taken into the semiconductor film 104 by performing a hydrogen plasma treatment before the semiconductor film 105 is formed. For this reason, it is not always necessary to perform the hydrogenation treatment once after the formation of the semiconductor crystal nuclei 4a and the semiconductor film 4b as in the third and fourth embodiments. Therefore, the number of process steps can be reduced as compared with the case of the third and fourth embodiments.

  In addition, since the semiconductor film 105 containing high-concentration hydrogen is stacked, a defect level in the lower semiconductor film 104 is terminated with hydrogen, and movement of carriers is suppressed. The off-state current of the thin film transistor TFT can be reduced.

  The present invention has been described using the embodiments. However, the configurations described in the embodiments so far are only examples, and the present invention can be appropriately changed without departing from the technical idea. Further, the configurations described in the respective embodiments may be used in combination as long as they do not contradict each other.

DESCRIPTION OF SYMBOLS 1,25 ... Substrate, 2 ... Gate electrode wiring, 3, 3a, 3b ... Gate insulating film, 4, 4b ... Semiconductor film (polycrystalline film), 4a ... Semiconductor crystal nucleus, 5a, 5b ... Contact layer, 6a ... source electrode wiring, 6b ... drain electrode wiring, 7, 8 ... protective film, 9 ... pixel electrode, TH ... through hole, 20, 24 ... alignment film, 21 ... color filter Layer, 22 ... overcoat layer, 23 ... counter electrode, 26 ... spacer, 104, 105 ... semiconductor film.

Claims (11)

A manufacturing method of a display device including a thin film transistor in which a gate electrode, a gate insulating film, a semiconductor film, and a source / drain electrode are sequentially stacked on a substrate including a display unit,
The gate insulating film comprises a first gate insulating film formed on the side close to the substrate, and a second gate insulating film formed so as to cover the surface of the first gate insulating film,
Forming the first gate insulating film;
Forming the second gate insulating film having a hydrogen concentration higher than the hydrogen concentration of the first gate insulating film on the upper surface of the first gate insulating film;
A silicon germanium semiconductor crystal nucleus is directly formed on the upper surface of the second gate insulating film having a hydrogen concentration higher than that of the first gate insulating film by using a reactive thermal CVD method. A step of forming the semiconductor film of silicon germanium, using as a seed ,
The germanium composition ratio of the semiconductor crystal nuclei is higher than that of the semiconductor film, and the semiconductor layer formed on the upper surface of the second gate insulating film is only silicon germanium between the semiconductor crystal nuclei and the semiconductor film. method of manufacturing a display device according to in formed wherein Rukoto.   2. The method of manufacturing a display device according to claim 1, wherein the reactive thermal CVD is performed using silanes and germanium halide as a source gas. Hydrogen contained in the second gate insulating film includes d and _NH when the film thickness of the second gate insulating film is dcm and the hydrogen concentration of the second gate insulating film is N _H cm ^−3. 2. The method of manufacturing a display device according to claim 1, wherein the product of the display device is 1 × 10 ¹⁴ cm ⁻² or more. A display device comprising a thin film transistor configured by sequentially laminating a gate electrode, a gate insulating film, a semiconductor film, and a source / drain electrode on a substrate including a display unit,
The gate insulating film comprises a first gate insulating film formed on the side close to the substrate, and a second gate insulating film formed so as to cover the surface of the first gate insulating film,
A hydrogen concentration in the second gate insulating film is formed higher than a hydrogen concentration in the first gate insulating film;
The semiconductor film is made of silicon germanium, and a semiconductor crystal nucleus made of silicon germanium is formed on the interface side with the second gate insulating film ,
The germanium composition ratio of the semiconductor crystal nuclei is higher than that of the semiconductor film, and the semiconductor layer formed on the upper surface of the second gate insulating film is only silicon germanium between the semiconductor crystal nuclei and the semiconductor film. in the form display device characterized Rukoto. Hydrogen contained in the second gate insulating film includes d and _NH when the film thickness of the second gate insulating film is dcm and the hydrogen concentration of the second gate insulating film is N _H cm ^−3. 5. The display device according to claim 4, wherein the product is 1 × 10 ¹⁴ cm ⁻² or more. The semiconductor crystal nuclei A display device according to any one of claims 4, 5 whose size is characterized by a range near Rukoto of 200nm from 10 nm. The semiconductor film, a display device according to any one of claims 4, 5, 6, characterized that you have made a microcrystalline film or a polycrystalline film made of germanium on the semiconductor crystal on nuclei. Wherein the semiconductor-forming nucleating display device according to any one of claims 4, 5, 6, 7, characterized in that it contains a concentration 1 × ¹⁰ 19 ^{cm -3} or more hydrogen. The display according to claim 4, wherein the semiconductor film on the semiconductor crystal nucleus contains hydrogen having a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. apparatus. An amorphous film, a microcrystalline film, or a polycrystalline film made of silicon is laminated as the second semiconductor film on the semiconductor film. The display apparatus in any one of. Wherein the second semiconductor film, a display device according to claim 1 0, characterized in that it contains a concentration 1 × ¹⁰ 19 ^{cm -3} or more hydrogen.

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