JP5692998B2 - Power supply - Google Patents

Description

  The present invention relates to a synchronous rectification switching power supply device.

  In recent years, with the power saving of electronic device apparatuses, there has been a demand for efficient operation of power supply apparatuses. As an example of a power supply device that achieves efficient operation, a power supply device described in Patent Document 1 has been proposed. A configuration example of such a conventional power supply apparatus is shown in FIG. In FIG. 7, 1 is a DC power source, 2 is a control circuit for controlling a field effect transistor MOS-FET (hereinafter also referred to as FET) as a main switching element, 4 is an FET as a main switching element, and 5 is a transformer. 6 is a FET as a second switching element, 7 is a smoothing capacitor, 8 is a load to which a voltage is supplied, 9 is an output voltage detection circuit, 10 is a body diode parasitic to FET 6, 11 is a drive circuit for FET 6, and 12 is It is a current detection circuit of FET6.

  The input voltage from the DC power supply 1 is stored as excitation energy in the primary winding n1 of the transformer 5 by turning on (turning on) the FET 4 controlled by the control circuit 2 and the drive circuit 3. On the other hand, the energy excited in the primary winding n1 of the transformer 5 at the timing when the FET 4 is turned off (turned off) is converted into the secondary winding n2 and supplied to the load through the body diode 10 and the current detection circuit 12. . When the current detection circuit 12 detects that a current has flowed, it sends an on signal to the drive circuit 11 to turn on the FET 6. The current detection circuit 12 determines that the current has ended when the current flowing in the current detection circuit 12 becomes equal to or less than a predetermined value, and this time sends an off signal to the drive circuit 12 to turn off the FET 6. The loss due to the FET 6 is very low compared to the loss due to the forward voltage of the body diode 10. For this reason, the efficiency is improved by controlling the current flowing through the body diode 10 to be switched to the FET 6 side. Such a method is called a synchronous rectification method, and the FET 6 is also called a synchronous rectification FET.

Japanese Patent Laid-Open No. 7-115766

  However, the above conventional example has the following problems. In the case of the synchronous rectification method described above, a circuit for detecting on / off of the FET for synchronous rectification is provided in order to improve the operation efficiency, and this detection circuit becomes complicated. Therefore, the circuit scale is increased, resulting in an increase in cost. In addition, when the current flowing through the secondary winding is detected by a current transformer and the FET is turned on and off using the detected current, the amount of current flowing through the secondary winding is small at light loads and is output from the current transformer. The current that flows becomes very small, and the on / off state of the FET cannot be controlled correctly. If ON / OFF of the FET is not controlled (driven) correctly, efficiency may be reduced and power consumption may be increased. Such a light load (light load state) indicates a standby state waiting for operation or an energy saving mode for reducing power consumption (also referred to as a sleep mode), which is a so-called default state in an electronic device. This default state occupies a considerable amount of time during the day in the electronic device, and an increase or loss in power consumption due to the on / off operation of the FET greatly affects the total power consumption of the electronic device.

  Therefore, in view of the above points, the present invention reduces the circuit scale with a simple circuit configuration in a synchronous rectification type switching power supply, and correctly executes the synchronous rectification operation regardless of the load state, thereby reducing the power consumption. The purpose is to reduce.

In order to achieve the above object, a power supply device according to the present invention includes a transformer having an insulated primary side and a secondary side, first switching means for switching a DC voltage input to the primary side of the transformer, and the first Control means for controlling the drive operation of the first switching means so that the detected value is constant by detecting the current flowing through the switching means, a diode for rectifying the voltage generated on the secondary side of the transformer, Second switching means connected in parallel with the diode and driven in synchronism with the driving operation of the first switching means, and the control means is configured such that the power supply device operates with a heavy load. In the operating state, the second switching means is stopped and applied to the cathode terminal of the diode in the standby state in which the power supply device is operating at a light load. The driving falling said second switching means at a timing of a voltage begins to be followed, and controls so as to stop driving after a lapse of a predetermined a predetermined time.

  As described above, according to the present invention, in a synchronous rectification switching power supply, it is possible to correctly execute a synchronous rectification operation and reduce power consumption with a simple circuit configuration regardless of the state of a load.

Circuit diagram of power supply device of embodiment 1 Operational waveforms of the circuit of the first embodiment Operation waveform of the circuit of the second embodiment The flowchart which shows operation | movement of Example 2. Circuit diagram of power supply device according to embodiment 3 Operation waveform of circuit of embodiment 3 Conventional circuit diagram

  Next, specific configurations of the present invention for solving the above-described problems will be described based on examples. In addition, the Example shown below is an example, Comprising: It is not the meaning which limits the technical scope of this invention only to them.

  FIG. 1 is a circuit diagram of a power supply device according to Embodiment 1 of the present invention, and FIG. 2 is a diagram showing a part of its operation waveform. Hereinafter, the first embodiment will be described in detail with reference to FIGS. 1 and 2.

  Reference numeral 101 denotes a DC voltage power supply, and a DC voltage is obtained by smoothing an AC voltage supplied from an outlet (commercial power supply) and full-wave rectified by a diode bridge (not shown) with a capacitor (not shown). Reference numeral 102 denotes a control IC as a control unit, which controls the on / off operation of a MOS-FET 103 (hereinafter referred to as FET) as a first switching element. Reference numeral 104 denotes a transformer that converts primary side energy to the secondary side while taking insulation between the primary side and the secondary side. The inductance of the primary winding is Lp, and the inductance of the secondary winding is Ls. Reference numeral 105 denotes a current detection resistor for detecting the current of the FET 103, 120 denotes a secondary smoothing capacitor, 121 denotes a MOS-FET (hereinafter referred to as FET) as a second switching element, and the secondary side voltage is It is a FET for synchronous rectification that rectifies. Similarly, 122 is a diode (also referred to as a body diode) for rectifying the secondary side voltage, and 123 is a control IC (CPU) that controls the operation of the electronic device. Reference numeral 8 denotes a load that outputs a voltage.

When the power supply device is activated, the control IC 102 starts driving (turns on) the FET 103 by a not-illustrated activation circuit. When the FET 103 is turned on, current flows through the primary side of the transformer 104 and the current detection resistor 105, and when the peak current flowing through the primary winding of the transformer 104 is Ip, energy E1 expressed by the following equation 1 is Accumulated.
E1 = 1/2 Lp × Ip ² (Formula 1)
This peak current Ip is converted into a voltage by the current detection resistor, and is controlled to a constant value by the control IC 102. For this reason, even if the input voltage changes, the energy accumulated in the transformer 104 becomes substantially the same value. For example, when a 100-V system voltage is input, when the input voltage is AC 85 V, the slope of the peak current is steep (the amount of change per unit time is large), so that the driving time (also referred to as on-time) of the FET 103 is shortened. On the other hand, when the input voltage is AC 140 V, the current slope falls (the amount of change per unit time is small), so the on-time of the FET 103 becomes long. In this way, even if the input voltage is different, the peak current value is the same only in the current flowing time.

On the other hand, the energy E2 accumulated in the secondary winding is expressed by the following equation 2 where Is is the peak current generated in the secondary winding.
E2 = 1 / 2Ls × Is ² (Formula 2)
In the case of a flyback power supply, the energy generated on the primary side of the transformer is equal to the energy converted to the secondary side, so that the current flowing in the secondary winding of the transformer 104 flows for a certain time regardless of the input voltage. It will be. The first embodiment is based on the premise that the output is controlled based on the peak value of the current on the primary side of the transformer.

  When the input voltage is constant, the on time of the FET 103 is also constant, and the on time of the current on the secondary side of the transformer is also constant. And in order to cope with the difference in the state of the load 8 (the load is large / small), the frequency is varied by changing the off time. That is, even when the load state changes, the time during which current flows on the secondary side of the transformer is constant.

In FIG. 2, 201 is a current waveform flowing through the FET 103, 202 is a voltage waveform between the drain and source of the FET 103, 203 is a current waveform on the secondary side of the transformer, and 204 is a voltage waveform between the drain and source of the FET 121 for synchronous rectification. Is shown. As described above, the fall of the voltage between the drain and the source of the FET 121 and the start of the current flow on the secondary side of the transformer have the same timing. The falling timing is detected by the control IC 123, and the IC 123 drives the FET 121 by setting the FET 121 gate terminal to the high level.
Specifically, the voltage input to the cathode terminal of the diode 122 is detected by the IC 123, the falling timing of the voltage is detected, and the FET 121 is controlled to be driven at the detected timing.
As for the timing of turning off the FET 121, since the method of the first embodiment is based on the method of fixing the peak current, the off time is also fixed as described above, and this time is stored in the control IC 123 in advance. . After a certain time stored in advance in the IC 123 (after the off time), the gate terminal of the FET 121 is set to a low level to turn off the FET 121. This off time is a predetermined time set in advance, and is 4 μs in this embodiment. Note that the off-time may be set as appropriate according to the characteristics of the circuit and elements used.

  As described above, in the method of fixing the peak current on the primary side of the transformer with the power supply of the synchronous rectification method, the falling of the output voltage of the secondary winding of the transformer is detected, and the synchronous rectification on the secondary side The driving of the FET is started, and the driving of the FET for synchronous rectification is controlled to stop after the prestored time has elapsed. As a result, the synchronous rectification FET on the secondary side can be operated correctly regardless of the state (size) of the load.

  In the first embodiment, the secondary-side rectifying diode 122 is provided separately from the FET 121, but a body diode provided in the synchronous rectifying FET can also be used.

  In Example 1, the falling of the output of the secondary winding of the transformer was detected by a method of fixing the peak current on the primary side of the transformer, and the driving of the secondary side synchronous rectification FET was controlled. The second embodiment proposes a method for reducing the decrease in efficiency due to variations in transformer inductance in the configuration of the first embodiment.

  In the configuration described in the first embodiment, for example, the time stored in the control IC and the actual secondary side due to variations in the primary and secondary inductances of the transformer, variations in resistance that is the primary-side current detection circuit, and the like There is a possibility that a difference occurs in the time during which current flows in the FET 121. In particular, when the load is large (also referred to as a heavy load), there is a possibility that the FET 121 on the secondary side of the transformer may continue to be driven even if current starts to flow on the primary side of the transformer. In such a case, when the primary side FET 6 is turned on again, that is, when a voltage is generated on the winding start side of the secondary side winding, the secondary side FET 121 continues to be driven. In this state, the negative side of the secondary electrolytic capacitor 120 may be reverse-biased, and the secondary electrolytic capacitor 120 may be deteriorated. Furthermore, the efficiency of the power supply may be reduced.

  FIG. 3 shows the relationship between the primary side current and the secondary side current when there is a difference between the stored time and the actual time. Reference numeral 301a denotes a current on the primary side of the transformer at a light load, 302b denotes a current on the secondary side of the transformer, and a section indicated by a broken line is an off time. On the other hand, 302a indicates the current on the primary side of the transformer at the time of heavy load, 302b indicates the current on the secondary side, and the period during which the current on the secondary side flows on the negative side (solid triangular area) is the primary side of the transformer. This is the overlap period of the drive timing of the FET of the second side and the FET of the secondary side. When this overlap period occurs, efficiency decreases. If the diode rectification method is used instead of the synchronous rectification method, it is automatically turned off when the rectification operation is completed, so such an overlapping period does not substantially exist (except for the reverse recovery time of the diode).

  In the second embodiment, as described above, in order to prevent the drive timings of the primary FET and secondary FET of the transformer from overlapping, the diode rectification is performed without performing the synchronous rectification operation in a heavy load state where the load is large. Then, control is performed so that the synchronous rectification operation is performed in a light load state in which a sufficient off time can be secured. Thereby, the remarkable efficiency fall at the time of heavy load can be avoided. In the case of a light load in which the off-time is sufficiently secured, even if there is a slight difference between the time stored in the control IC and the time actually driving the FET on the secondary side of the transformer, There is room in the time until the FET is turned on again, and the efficiency is not reduced as described above.

  Note that the light load state in which the off-time can be secured is a standby state (for example, a standby state or a sleep state (power saving state)) in which an electronic device is waiting for an operation. On the other hand, if the electronic device is in an operating state, it becomes a heavy load state in which the load is larger than in the light load state. In electronic devices, the standby time is longer than the operating state (operating state), so reducing the power consumption in this standby state is important to reduce the total power consumption of the electronic device. It is.

  Hereinafter, the operation of the second embodiment will be described. Since the circuit configuration is the same as that of the first embodiment (FIG. 1), description of the configuration is omitted. The difference from the first embodiment is the driving operation of the FET 121 on the secondary side of the transformer. As a matter of course, the electronic device is in a heavy load state when in an operating state, and is in a light load state in a standby state in which the device is stopped or a sleep state in which the power consumption of the device is reduced. The second embodiment is characterized in that the operation of the FET on the secondary side of the transformer is controlled in accordance with the state (mode) of the electronic device.

  A specific operation will be described based on the flowchart of FIG. First, in step 401, it is detected whether or not the electronic device is in an operating state. For example, in the case of a printer such as an image forming apparatus as an example of an electronic device, it is possible to define an operation state when the apparatus enters an image forming operation and a non-operation state when it is not. For example, it may be determined that the apparatus has entered the operating state at the timing when the image forming operation is started. When the electronic device is in an operating state (when S401 is Yes), it is determined that the electronic device is in a heavy load state, and the control IC 123 does not operate (control) the FET 121 for synchronous rectification, and the rectification operation is performed by the diode 122. To do. That is, the control IC 123 does not drive the FET 121. When the drive control of the FET 121 is not performed, the voltage on the secondary side of the transformer is automatically rectified by the diode 122. In this case, during the period when the current is flowing to the primary side of the transformer, a voltage is generated with the secondary winding starting from the winding start side being positive. However, since the diode 122 blocks the current, no current flows to the load 8 side. . Then, when the current on the primary side has finished flowing, a voltage having a positive polarity on the winding end side of the secondary winding is generated, and the secondary winding of the diode 122 → the transformer 104 is generated from the load 8 (and the electrolytic capacitor 120). Current flows through the route. At this time, since the forward direction of the diode 122 and the direction of the current are the same, the current is not blocked by the diode 122. On the other hand, if step 401 is No, that is, if the electronic device transitions to a standby state or a sleep state, the process waits until a falling edge of the output of the secondary winding comes in step 402. When the falling edge is detected (when S402 is Yes), in step 403, the gate terminal of the FET 121 is set to the high level, and the FET 121 is turned on. Next, in step 404, a timer is set. The timer value set at this time is the same as or slightly smaller than the time during which current is flowing through the transformer described in the first embodiment. The reason for setting a slightly smaller value is that the current may flow backward from the smoothing capacitor 120 on the secondary side if the actual flow time becomes larger than the time that the current flows on the secondary side due to variations or the like. This is because energy may be wasted. In step 405, the process waits until the timer reaches zero. When the timer reaches zero, in step 406, the gate terminal of the FET 121 is set to a low level, and the FET 121 is turned off.

  As explained above, the diode rectification method is used instead of the synchronous rectification method when the electronic device is operating, and the output voltage of the secondary winding falls when the electronic device is in the standby state or sleep state. Is detected to control the driving of the synchronous rectification FET. As a result, the drive control of the primary-side FET and the secondary-side FET can be controlled without overlapping, and a synchronous rectification operation with reduced power consumption becomes possible.

  When applied to a power supply device that lowers the output voltage in the sleep state in order to further reduce power consumption in the sleep state. Switching between diode rectification and synchronous rectification can be performed based on a power supply switching signal.

  In the first and second embodiments, the driving of the secondary side FET of the transformer is controlled by the control unit (CPU) of the electronic device. The third embodiment is characterized in that the driving of the secondary-side FET is controlled using a driving circuit instead of the control unit.

  The configuration of the third embodiment will be described below based on the circuit diagram of FIG. 5 and the operation waveforms of FIG. In FIG. 5, the same components as those in the first embodiment (FIG. 1) are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 5, reference numeral 130 denotes an auxiliary winding for supplying a voltage to the gate terminal of the FET 121 on the secondary side of the transformer. C131 is a capacitor having one end connected to the winding end side of the auxiliary winding 130 and the other end connected to the gate terminal of the FET 121 on the secondary side. Reference numeral 132 denotes a resistor having one end connected to the gate terminal of the secondary FET 121 and the other end connected to the winding start side of the auxiliary winding 130 and the ground side of the secondary output. In addition, a diode 133 is connected in parallel with the resistor 132 and the cathode side thereof is connected to the gate terminal of the FET 121 on the secondary side. In such a circuit configuration, when the primary side FET 103 is turned off, a voltage having a positive polarity at the winding end side of the auxiliary winding 130 is generated for a certain period, and the voltage is supplied to the gate terminal of the secondary side FET 121 through the capacitor 131. start. The capacitor 131 and the resistor 132 form a differentiation circuit, and the voltage supplied to the secondary-side FET 121 is gradually attenuated. The diode 133 is connected so that the voltage between the gate and the source of the secondary FET 121 does not exceed the withstand voltage.

  FIG. 6 shows a voltage waveform applied to the gate terminal of the FET 121. The vertical axis represents voltage value (V), and the horizontal axis represents time (t). The timing at which the voltage decay curve falls below Vth, which is the ON voltage of the secondary-side FET 121, is the ON period of the secondary-side FET 121. The values of the capacitor 131 and the resistor 132 are adjusted so that the ON period becomes a predetermined value. Thus, the synchronous rectification operation can be performed by setting the ON period to a predetermined value.

  As described above, the auxiliary winding is added to the transformer, and the output of the auxiliary winding is supplied to the gate terminal of the secondary-side FET through the differentiation circuit using the capacitor and the resistor. As a result, the secondary FET can be turned on for a certain period of time, and a stable and accurate synchronous rectification operation can be realized as in the first embodiment.

  Even when the hardware circuit is configured and the synchronous rectification FET is driven and controlled as in the third embodiment, the same operation as in the first and second embodiments can be realized. For example, if the timing at which the secondary side FET is turned off is set before (shorter) than the timing at which the secondary side current becomes zero, and control is performed to switch to diode rectification immediately before the secondary side FET is turned off, Even if each element varies, the drive timing of the primary side FET and the secondary side FET can be controlled so as not to overlap.

101 DC power supply 102 Control IC
103 Field Effect Transistor 104 Transformer 120 Smoothing Capacitor 121 Synchronous Rectification FET
122 diode

Claims (4)

A transformer in which the primary side and the secondary side are insulated;
First switching means for switching a DC voltage input to the primary side of the transformer;
Control means for controlling the driving operation of the first switching means so that the value detected by detecting the current flowing through the first switching means becomes constant;
A diode for rectifying the voltage generated on the secondary side of the transformer;
A second switching means connected in parallel with the diode and driven in synchronism with the driving operation of the first switching means;
The control means stops the second switching means in an operating state in which the power supply device is operating at a heavy load, and in a standby state in which the power supply device is operating at a light load, the cathode terminal of the diode The power supply device is controlled to start driving the second switching means at the fall timing of the voltage applied to the first and then stop driving after a predetermined time has elapsed . The power supply apparatus according to claim 1 , wherein the control unit stores a value of the predetermined time. 3. The power supply device according to claim 1, wherein the second switching means is a MOS-FET. 4. The power supply device according to claim 3, wherein the diode is a body diode of the MOS-FET.

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