JP5692705B2 - Comparator circuit - Google Patents

Description

  The present invention relates to a comparator circuit that can operate at a higher speed and with lower power consumption than the prior art.

  In recent research, in order to realize ultra-low power consumption of LSI (Large Scaled Integrated circuit), sub-threshold LSI using sub-threshold region operation of MOS field-effect transistor (hereinafter referred to as MOS transistor) has been attracting attention. Yes. However, since these design methodologies are in the early stages of development, there is a strong demand for design techniques for ultra-low power consumption circuits. In order to realize such an LSI, various studies have been performed (for example, see Non-Patent Documents 1 to 4). In this specification, a MOS transistor used as a switch element is referred to as a switch transistor.

JP 2002-311063 A US Pat. No. 6,922,319

Anantha P. Chandrakasan et al., "Next generation micro-power systems", Symposium VLSI Circuits Digest, pp. 2-5, June 2008. Ken Ueno et al., “A 300-nW, 15-ppm / ℃, 20-ppm / V CMOS voltage reference circuit consisting of subthreshold MOSFETs”, IEEE Journal of Solid-State Circuits, vol. 44, no.7, pp 2047-2054, 2009. Tetsuya Hirose et al., "A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities", Proceedings of the 36th European Solid-state Circuits Conference, pp. 114-117, September 2010. Tetsuya Hirose et al., "A CMOS Bandgap and Sub-Bandgap Voltage Reference Circuits for Nanowatt Power LSIs", IEEE Asian Solid-state Circuits Conference, pp. 77-80, November 2010. Marc Degrauwe et al., "Adaptive biasing CMOS amplifiers", IEEE Journal of Solid-state Circuits, vol. 17, pp. 522-528, June, 1982. R. Jacob Baker et al., "CMOS Circuit Design, Layout, and Simulation", Second Edition, IEEE Press, 2004. Hui Shao et al., "Low Energy Level Converter Design for Sub-VTH Logics", ASP-DAC 2009, pp. 107-108, 19-22, January 2009.

  The comparator circuit is an important element circuit for processing various analog / digital signals in the LSI. One effective method for reducing the power of the comparator is to reduce the bias current to below microamperes. However, when the bias current is set to the nanoampere order in the stage type comparator according to the prior art, it takes a long time to compare the input voltages and output a digital signal as a comparison result. Therefore, in practice, a comparator cannot be used with a bias current in the order of nanoamperes.

  Non-patent document 5 introduces an adaptive bias technique for a CMOS amplifier. This technique is useful in OTA (Operational Transconductance Amplifier) design, but it cannot be said that it is practical because it increases power consumption when applied to comparator design (see, for example, Non-Patent Document 6).

  In recent research, a comparator circuit using an adaptive bias current generation circuit for improving the low-speed operation of the low power consumption comparator has been proposed (see, for example, Patent Documents 1 and 2). However, even this circuit is insufficient to satisfy the requirements of high speed and low power consumption. This is because the adaptive bias technique can increase the operation speed of the comparator, but generates more current than necessary, resulting in an increase in power consumption. In addition, the need for a plurality of differential pairs increases the circuit scale.

  An object of the present invention is to solve the above problems and to provide a comparator circuit that can operate at a subthreshold region operation and can reduce power consumption at a higher speed than in the prior art.

The comparator circuit (1) according to the present invention includes:
Depending on two input voltages (V _INP , V _INM ) input, in any one MOS transistor of the input differential pair composed of the first and second MOS transistors (M _P1 , M _P2 ), the 1 An input differential pair and an adaptive bias current generation circuit (12) for generating an adaptive bias current (I _ADP ) by a loop (L1, or L2) including two MOS transistors and a switch transistor ( _MSW1 or _MSW2 );
The latch transistors of the two output voltages (V _P , V _M ) are determined according to the initial state and the two input voltages (V _INP , V _INM ) to control the switch transistor (M _SW1 or M _SW2 ). A latch circuit for controlling the input differential pair and the adaptive bias current generating circuit (12).
The latch circuit (13) _{generates the} adaptive bias current (I _ADP ) when the latch logic of the two output voltages (V _P , V _M ) and the two input voltages (V _INP , V _INM ) do not match each other. ) To control the input differential pair and the adaptive bias current generation circuit (12),
The latch circuit (13) detects the current corresponding to the adaptive bias current (I _ADP ) and changes the latch logic, and then switches the switch transistor (M _SW1 or M _SW2 ) from on to off. To control the input differential pair and the adaptive bias current generation circuit (12) so as to cut off the adaptive bias current (I _ADP ) .

In the comparator circuit (1), the input differential pair and the adaptive bias current generation circuit (12) include first and second loops (L1, L2),
The first loop (L1) includes the first MOS transistor (M _P1 ), the first switch transistor (M _SW1 ), and the third and fourth MOS transistors (M _N3 , M _N4 ). A first current mirror circuit (M _N3 , M _N4 ) configured such that an aspect ratio of the fourth MOS transistor (M _N4 ) is larger than an aspect ratio of the third MOS transistor (M _N3 ); Are connected in series,
The second loop (L2) includes the second MOS transistor (M _P2 ), the second switch transistor (M _SW2 ), and the fifth and sixth MOS transistors (M _N5 , M _N6 ). A second current mirror circuit (M _N5 , M _N6 ) configured such that the aspect ratio of the sixth MOS transistor (M _N6 ) is larger than the aspect ratio of the fifth MOS transistor (M _N5 ); Are connected in series,
The adaptive bias current (I _ADP ) is generated by the first or second current mirror circuit (M _N3 , M _N4 ; M _N5 , M _N6 ).

In the comparator circuit (1),
The third MOS transistor (M _N3 ) is connected in series to the first MOS transistor (M _P1 ),
The fifth MOS transistor (M _N5 ) is connected in series to the second MOS transistor (M _P2 ),
The input differential pair and the adaptive bias current generation circuit (12)
By detecting the current flowing through the third MOS transistor _{(M N3),} current to the first and second transistors _{(M P1,} M _P2) and an input differential pair _(connecting point _{M P1,} M _P2) A seventh MOS transistor (M _P4 ) that outputs
By detecting the current flowing through the fifth MOS transistor _{(M N5),} current to the first and second transistors _{(M P1,} M _P2) and an input differential pair _(connecting point _{M P1,} M _P2) An eighth MOS transistor (M _P6 ) for outputting
A ninth MOS transistor (M _N1 ) connected in parallel with the third MOS transistor (M _N3 );
A tenth MOS transistor (M _N2 ) connected in parallel with the fifth MOS transistor (M _N5 );
The ninth MOS transistor (M _N1 ) and the tenth MOS transistor (M _N2 ) are cross-gate connected so that one of the two input voltages (V _INP , V _INM ) has an input voltage. On the other hand, the first detection voltage or the second detection voltage includes a positive feedback hysteresis circuit having hysteresis characteristics.

Further, in the comparator circuit (1), the input differential pair and the adaptive bias current generation circuit (12) are configured so that the two input voltages (V _INP and V _INM ) substantially coincide with each other, or Circuits (M _P9 , M _P10 ) for reducing the current flowing in the first and second loops (L1, L2) when both the first and second switch transistors (M _SW1 , M _SW2 ) are turned on. ) Is further provided.

  Still further, the comparator circuit (1) is composed of only a CMOS circuit.

  The comparator circuit (1) further includes a buffer circuit (2) connected to the subsequent stage of the latch circuit (13) and buffering and amplifying the output voltage of the latch circuit. .

  Therefore, according to the comparator circuit of the present invention, it is possible to provide a comparator circuit that can operate at a higher speed and reduce power consumption in a comparator circuit that operates in a subthreshold region operation.

1 is a circuit diagram showing a configuration of a circuit including a comparator circuit 1 and a buffer circuit 2 according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an operation example 1 of the comparator circuit 1 in FIG. 1. FIG. 6 is a circuit diagram showing an operation example 2 of the comparator circuit 1 in FIG. 1. 1 is an experimental result of the comparator circuit 1 according to the embodiment (prototype example) of FIG. 1 and the comparator circuit according to the conventional example of FIG. 8, where (a) shows the input reference voltage VIN + when the input frequency is 10 kHz, It is a measurement waveform diagram showing the output voltage and the output voltage of the conventional example, (b) is a measurement waveform diagram showing the input reference voltage VIN + when the input frequency is 20 kHz, the output voltage of the embodiment and the output voltage of the conventional example. is there. It is an experimental result of the comparator circuit which concerns on an Example and a prior art example, _{Comprising: It} is a graph which shows the operation | movement maximum frequency _{fmax with} respect to bias current _IREF . It is an experimental result of the comparator circuit which concerns on an Example and a prior art example, Comprising: It is a graph which shows the consumption current with respect to input frequency. It is an experimental result of the comparator circuit which concerns on an Example and a prior art example, Comprising: It is a graph which shows the duty ratio of the output pulse with respect to input frequency. It is a circuit diagram which shows the structure of the comparator circuit which concerns on a prior art example. It is a table | surface which shows the operation state of the comparator circuit 1 which concerns on an Example. It is a table | surface which shows the performance specification of the comparator circuit which concerns on an Example and a prior art example.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a circuit diagram showing a configuration of a circuit including a comparator circuit 1 and a buffer circuit 2 according to an embodiment of the present invention. In the present embodiment, in order to solve the above-mentioned problems of the prior art, a high speed and low power consumption using the input differential pair and the adaptive bias current generation circuit 12 is realized in the comparator circuit operating in the subthreshold region operation. Propose a comparator to do. The proposed comparator circuit 1 uses two positive feedback loops L1 and L2 for current generation, uses the latch circuit 13 to determine the logic of the output voltage, and the input differential pair and the adaptive bias current generation circuit 12. It is characterized by performing current control.

In FIG. 1, the comparator circuit 1 according to the present embodiment is
(A) the reference bias current is a minute current of nano-amperes _{(hereinafter.} Referred bias _current) and a current source 20 for generating _{I REF,} the bias current generator that includes a MOS transistor _{M PB1} monitoring the bias current _{I REF} A circuit 11 (see, for example, Non-Patent Document 3);
(B) A circuit 12 that operates based on a current generated by a current generation circuit 14 using a current mirror from a bias current I _REF , and includes an input differential pair circuit (MOS transistors M _PB2 , M _P1 , M _P2 , M _N3 , M _N5 ) and an adaptive bias current generating circuit having hysteresis control (MOS transistors M _P3 , M _P4 , M _P9 , _{MSW 1} , M _N1 , M _N4 ; MOS transistors M _P5 , M N _P6 , _MP10 , _MSW2 , _MN2 , _MN6 ) and an input differential pair and adaptive bias current generating circuit 12, and (c) current supply MOS transistors _MP7 , _MP8 are cross-coupled. and four MOS transistors and a _M N7 _{~M N10,} input differential pair, and the adaptive bias current generating circuit Based on the adaptive bias current _{I ADP} flowing to 2, as described in detail later, together with changing the cross-couple connected four MOS transistors _{M N9, M N7, M N10} , internal logic latch consisting of _{M N8} And a latch circuit 13 for controlling the adaptive bias current I _ADP by controlling on / off of the switch transistors _MSW1 and _MSW2 .

  In the subsequent stage of the comparator circuit 1, in order to increase the output current capacity, cross-gate connected MOS transistors Q1 to Q4, common source amplification MOS transistors Q5 and Q6, and output terminals 23 and 24 are provided. A buffer circuit 2 is provided. Further, the comparator circuit 1 and the buffer circuit 2 are all constituted by CMOS circuits composed of pMOS transistors and nMOS transistors. Note that the comparator circuit 1 operates in the sub-threshold region during standby, and when the adaptive bias current is generated, a large current operation is performed, so that the sub-threshold operation is changed to a strong inversion region operation. As will be described later, after the adaptive bias current is generated and the logic inversion is completed, the operation is performed again in the subthreshold region.

In this embodiment, a bias current generating circuit (see, for example, Non-Patent Document 3) that generates a minute current of nanoampere current is used in order to realize ultra-low power consumption. The latch circuit 13 determines the logic of the output voltages V _P and V _M according to the initial state and the relationship between the input voltages V _INP and V _INM input to the input terminals 21 and 22, and the switch transistor switches M _SW1 and M _{SW The} input differential pair and the adaptive bias current generation circuit 12 are controlled by ON / OFF control of _SW2 .

The input differential pair and adaptive bias current generation circuit 12 includes two positive feedback loops L1 and L2. The path of the loop L1 is a MOS transistor _MP1 - _MN3 - _MN4 - _MSW1 - _MP3 - _MP4 , and the path of the loop L2 is a MOS transistor _MP2 - _MN5 - _MN6 - _SW2 - _MP5- M. _P6 . In the loop L1, L2 of the two, the aspect ratio K (> 1) is doubled about W / L for the MOS transistors _{M N3} of the MOS transistor _{M N4,} the aspect ratio for W / L for the MOS transistors _{M N5} of the MOS transistor _{M N6} K (> 1) times. Here, W is the gate width of the MOS transistor, L is the gate length of the MOS transistor, and K is a current gain factor determined by the aspect ratio of the two MOS transistors constituting the current mirror circuit. By making the current gain factor K greater than 1, the positive feedback loop generates an adaptive bias current I _ADP . The input differential pair and adaptive bias current generation circuit 12 has an adaptive bias current I _ADP applied to either the loop L1 or the loop L2 according to the input voltage _VINP to the input terminal 21 and the input voltage _VINM to the input terminal 22. Is generated.

The latch circuit 13 detects the adaptive bias current I _ADP by receiving the current through the MOS transistors M _P7 and M _P8 and changes the internal logic. After the logic has determined, since the adaptive bias current _{I ADP} unnecessary to cut off the adaptive bias current _{I ADP} according to the logic and switching transistor _{M SW1, M SW2} latch circuit 13.

  Next, the operation principle of the comparator circuit 1 will be described in detail below with reference to FIG. 1, FIG. 2, FIG. 3, and FIG. 2 is a circuit diagram showing an operation example 1 (states 1 and 2 in FIG. 9) of the comparator circuit 1 in FIG. 1, and FIG. 3 is an operation example 2 in the comparator circuit 1 in FIG. 1 (states 3 and 4 in FIG. 9). FIG. FIG. 9 is a table showing the operating state of the comparator circuit 1 according to the embodiment. Since the logic of the latch circuit 13 plays an important role in the operation of the comparator circuit according to this embodiment in the comparator circuit 1, the circuit operation based on the logic of the latch circuit 13 will be described below.

(1) State 1 (FIG. 2): The circuit operation when the latch logic is the output voltage V _P = L level and the output voltage V _M = H level is as follows.
When the input voltage V _INP is higher than the input voltage V _INM (V _INP > V _INM ), most of the bias current I _REF flows through the MOS transistor MP ₁ . Thereby, the adaptive bias current I _ADP is generated in the positive feedback loop L1, and is amplified by the current mirror circuit (MOS transistors M _N3 and M _N4 ) having the current gain factor K. That is, the current flowing through the MOS transistor _{M N4} becomes K times the current flowing through the MOS transistor _{M N3.} The adaptive bias current I _ADP generated here is copied by the current mirror circuit (MOS transistors M _P3 , M _P7 ), that is, the adaptive bias current I _ADP is detected by the MOS transistor MP ₃ and the current corresponding thereto is the MOS transistor. by flowing through the M _P7, to vary the output voltage _{V P} from L level to H level. As a result, the internal logic of the latch circuit 13 is inverted. If the logic of the output voltage _{V M} is inverted from H level to L level, the switch transistor _{M SW1} is turned off by the output voltage _{V M,} the adaptive bias current _{I ADP} is interrupted, the process proceeds to state 3.

(2) State 2 (FIG. 2): The circuit operation when the latch logic (V _P = L level, V _M = H level) is as follows.
When the input voltage V _INP is lower than the input voltage V _INM (V _INP <V _INM ), most of the bias current I _REF flows through the MOS transistor _MP2 . However, the output voltage _{V P} because it has to turn off the switch transistor _{M SW2,} loop L2 is not functional, the adaptive bias current _{I ADP} is not generated. In this case, the latch circuit 13 holds the internal logic.

(3) The circuit operation in the state 3 (FIG. 3) latch logic: V _P = H level, V _M = L level is as follows.
When the input voltage V _INP is higher than the input voltage V _INM (V _INP > V _INM ), most of the bias current I _REF flows through the MOS transistor MP ₁ . However, the output voltage _{V M} is because it turns off the switch transistors _{M SW1,} loop L1 does not function, the adaptive bias current _{I ADP} is not generated. In this case, the latch circuit 13 holds the internal logic.

(4) The circuit operation in the state 4 (FIG. 3) latch logic: V _P = H level, V _M = L level is as follows.
When the input voltage V _INP is lower than the input voltage V _INM (V _INP <V _INM ), most of the bias current I _REF flows through the MOS transistor _MP2 . Thereby, the adaptive bias current I _ADP is generated in the positive feedback loop L2, and is amplified by the current mirror circuit (MOS transistors M _P5 and M _P6 ) having the current gain factor K. That is, the current flowing through the MOS transistor _{M N6} becomes K times the current flowing in the MOS transistors _{M N5.} The adaptive bias current I _ADP generated here is copied by the current mirror circuit (MOS transistors M _P5 , M _P8 ), that is, the adaptive bias current I _ADP is detected by the MOS transistor M _P5 and the corresponding current is detected by the MOS transistor. by flowing through the M _P8, to vary the output voltage _{V M} from L level to H level. As a result, the internal logic of the latch circuit 13 is inverted. If the logic of the output voltage _{V P} is inverted from H level to L level, the switching transistor _{M SW2} is turned off by the output voltage _{V P,} the adaptive bias current _{I ADP} is interrupted, the process proceeds to state 2.

As is apparent from FIG. 9, the adaptive bias current I _ADP is generated only when the logic of the latch circuit 13 and the input voltage level do not match each other (states 1 and 4). Then, state 1 shifts to state 3 and becomes a steady state, while state 4 shifts to state 2 and becomes a steady state.

The generated adaptive bias current I _ADP is expressed as follows: First, let αI _REF be the current flowing through the MOS transistor with the lower gate potential. Here, α (0.5 <α <1) is a ratio depending on the input voltages V _INP and V _INM . Thus, the adaptive bias current I _ADP is expressed by the following equation.

Here, when K is set to a value larger than 1, the adaptive bias current I _ADP can be obtained. The generated adaptive bias current I _ADP changes the internal logic of the latch circuit 13 to cut off the adaptive bias current. By this method, high speed and low power consumption operation of the comparator can be realized.

  Next, the hysteresis characteristics of the input differential pair and the adaptive bias current generation circuit 12 will be described below.

A hysteresis circuit used for suppressing the influence of noise superimposed on the input signal and identifying the signal level in the mV order will be described. This hysteresis circuit is realized by using positive feedback of MOS transistors M _N1 and M _N2 by cross-gate connection. Currents I _P1 and I _P2 flowing through the input differential pair circuit can be expressed by the following equations. Here, the current I _P1 is a current that flows into the MOS transistor _MN1 , and I _P2 is a current that flows into the MOS transistor _MN2 .

Here, g _m the transconductance of the input differential pair circuit, the I _SS is the source current of the input differential pair circuit. Also, β ₃ = β ₅ = β _A and β ₁ = β ₂ = β _B. β _i = W / L (i = 1, 2, 3, 5), where W is the gate width of the MOS transistor and L is the gate length of the MOS transistor. Β ₁ is the aspect ratio of the MOS transistor M _N1 , β ₂ is the aspect ratio of the MOS transistor M _N2 , β ₃ is the aspect ratio of the MOS transistor M _N3 , and β ₅ is the aspect ratio of the MOS transistor M _N5 . Is the ratio.

Here, consider a case where the input voltage V _INM rises from a voltage sufficiently lower than the input voltage V _{INP and} the gate-source voltage V _gs (M _N3 ) of the MOS transistor M _N3 is inverted to zero. In the initial state, MOS transistor _M gate-source voltage _V gs _{(M N3)} of _N3 is the threshold voltage _{V TH} voltage in the vicinity of the MOS transistor, the other of the gate-source voltage _{V gs} of the MOS transistor MN5 (M _N5 ) is 0V. Here, the condition MOS transistor gate-source voltage _V gs of _{M N3 to (M N3)} is inverted to zero, the current of the MOS transistor _{M N1} induced by (i) current _{I P1,} (ii) current I The current of the MOS transistor _MN1 induced by _P2 becomes equal. That is, it is expressed by the following formula.

On the other hand, consider a case where the input voltage V _INM drops from a voltage sufficiently higher than the input voltage V _{INP and} the gate-source voltage V _gs (M _N5 ) of the MOS transistor M _N5 is inverted to zero. In the initial state, MOS transistor gate-source voltage _V gs of _{M N5 (M N5)} is the threshold voltage _{V TH} voltage in the vicinity of the MOS transistor, the MOS transistor gate-source voltage _{V gs} of _{M N5} ( M _N5 ) is 0V. As with the above, the conditions MOS transistor gate-source voltage _V gs of _{M N5 (M N5)} is reversed, and the current of the MOS transistor _{M N2} induced by (i) current _{I P2,} (ii) it is that in which the current of the MOS transistor _{M N2} induced by the current _{I P1} equal. That is, it is expressed by the following formula.

Therefore, from the expressions (2) to (4), the voltages V _SPH and V _{SPL at the} switching point are expressed by the following expressions.

As is clear from the above equation (5), no hysteresis characteristic appears when β _A = β _B. On the other hand, when β _B > β _A , a hysteresis characteristic appears in the input differential pair of the comparator circuit 1 and the adaptive bias current generation circuit 12. The hysteresis can be controlled by adjusting the transistor sizes of the MOS transistors M _N1 , M _N2 , M _N3 , and M _N5 .

  Next, suppression of current consumption will be described below.

As described above, the comparator circuit 1 according to the present embodiment realizes a high speed and low power consumption operation by using the adaptive bias current generation technique and the latch circuit 13. The adaptive bias current I _ADP is generated only when the logic level of the latch circuit 13 and the input voltage level do not substantially match each other. Thereby, current consumption can be minimized.

However, when both input voltages are equal (V _INP = V _INM ) or when the switch transistors M _SW1 and M _SW2 are turned on / off in a special state (for example, the switch transistors M _SW1 and M _SW2 are In a state in which both are turned on, the current consumption increases in both positive feedback loops L1 and L2. In this state, half of the bias current I _REF flows to the input MOS transistors M _P1 and M _P2 , and both the positive feedback loops L 1 and L 2 become active, so that the adaptive bias current I _ADP becomes both the positive feedback loops L 1 and L 2. Generated at L2. When such a phenomenon occurs, there is a problem that current consumption of the circuit increases.

In order to solve this problem, MOS transistors M _P9 and M _P10 shown in FIG. 1 are added. The aspect ratio of the MOS transistor _{M P9} is 'set to be doubled, the aspect ratio of the MOS transistor _{M P10} is K aspect ratio of the MOS transistor _{M P3'} K aspect ratio of the MOS transistor _{M P5} set to be doubled To do. Here, MOS transistors _{M P9, M P10} monitors the current flowing through the MOS transistor _{M P5, M P3} respectively. By using two current mirror circuits composed of these transistors, the current flowing through the transistors M _P3 and M _P5 is reduced and reduced when the adaptive bias currents of both positive feedback loops L1 and L2 are generated simultaneously. Can do. This will be described below.

First, currents flowing through the input transistors M _P1 and M _P2 and the MOS transistors M _P3 and M _P5 are I _REF / 2 and I ₁ , respectively. As a result, the following equation can be derived from Kirchhoff's law.

From the equation (7), the current I ₁ is expressed by the following equation.

From here, the adaptive bias current I _ADP is expressed by the following equation.

  At this time, if K / (1 + K ′) is designed to be 1 or less, Expression (4) can be simplified as the following expression.

From the equation (10), there is a difference in timing when the same input voltages M _P1 and M _P2 are applied to the input differential pair (MOS transistors M _P1 and M _P2 ) and the switch transistors M _SW1 and M _SW2 are turned on / off. Even when it occurs, the adaptive bias current I _ADP can be suppressed.

The comparator circuit (1) configured as described above is characterized by having the following configuration. In other words, the comparator circuit (1) has either one of the input differential pairs composed of the first and second MOS transistors (M _P1 , M _P2 ) according to the two input voltages (V _INP , V _INM ) inputted. In one MOS transistor, an input differential pair that generates an adaptive bias current (I _ADP ) by a loop (L1, or L2) including the one MOS transistor and a switch transistor (M _SW1 or M _SW2 ) and adaptive After detecting a current corresponding to the bias current generation circuit (12) and the adaptive bias current (I _ADP ) and changing the latch logic, the switch transistor (M _SW1 or M _SW2 ) is switched from on to off. And a latch circuit (13) for cutting off the adaptive bias current.

In the comparator circuit (1), the input differential pair and the adaptive bias current generation circuit (12) include first and second loops (L1, L2),
The first loop (L1) includes the first MOS transistor (M _P1 ), the first switch transistor (M _SW1 ), and the third and fourth MOS transistors (M _N3 , M _N4 ). A first current mirror circuit (M _N3 , M _N4 ) configured such that an aspect ratio of the fourth MOS transistor (M _N4 ) is larger than an aspect ratio of the third MOS transistor (M _N3 ); Are connected in series,
The second loop (L2) includes the second MOS transistor (M _P2 ), the second switch transistor (M _SW2 ), and the fifth and sixth MOS transistors (M _N5 , M _N6 ). A second current mirror circuit (M _N5 , M _N6 ) configured such that the aspect ratio of the sixth MOS transistor (M _N6 ) is larger than the aspect ratio of the fifth MOS transistor (M _N5 ); Are connected in series,
The adaptive bias current (I _ADP ) is generated by the first or second current mirror circuit (M _N3 , M _N4 ; M _N5 , M _N6 ).

In the comparator circuit (1), the third MOS transistor (M _N3 ) is connected in series to the first MOS transistor (M _P1 ), and the fifth MOS transistor (M _N5 ) is connected to the first MOS transistor (M _N5 ). Connected in series to two MOS transistors (M _P2 ),
The input differential pair and the adaptive bias current generation circuit (12)
By detecting the current flowing through the third MOS transistor _{(M N3),} current to the first and second transistors _{(M P1,} M _P2) and an input differential pair _(connecting point _{M P1,} M _P2) A seventh MOS transistor (M _P4 ) that outputs
By detecting the current flowing through the fifth MOS transistor _{(M N5),} current to the first and second transistors _{(M P1,} M _P2) and an input differential pair _(connecting point _{M P1,} M _P2) An eighth MOS transistor (M _P6 ) for outputting
A ninth MOS transistor (M _N1 ) connected in parallel with the third MOS transistor (M _N3 );
A tenth MOS transistor (M _N2 ) connected in parallel with the fifth MOS transistor (M _N5 );
The ninth MOS transistor (M _N1 ) and the tenth MOS transistor (M _N2 ) are cross-gate connected so that one of the two input voltages (V _INP , V _INM ) has an input voltage. On the other hand, the first detection voltage or the second detection voltage includes a positive feedback hysteresis circuit having hysteresis characteristics.

Further, in the comparator circuit (1), the input differential pair and the adaptive bias current generation circuit (12) are configured so that the two input voltages (V _INP and V _INM ) substantially coincide with each other, or Circuits (M _P9 , M _P10 ) for reducing the current flowing in the first and second loops (L1, L2) when both the first and second switch transistors (M _SW1 , M _SW2 ) are turned on. ).

  FIG. 4 is an experimental result of the comparator circuit 1 according to the embodiment (prototype example) of FIG. 1 and the conventional comparator circuit of FIG. 8, and FIG. 4 (a) is an input reference voltage when the input frequency is 10 kHz. FIG. 4B is a measurement waveform diagram showing VIN +, the output voltage of the embodiment, and the output voltage of the conventional example. FIG. 4B is an input reference voltage VIN + when the input frequency is 20 kHz, the output voltage of the embodiment, and the output of the conventional example. It is a measurement waveform diagram which shows a voltage. FIG. 8 is a circuit diagram showing a configuration of a comparator circuit according to a conventional example.

The inventors made a prototype of the comparator circuit 1 of FIG. 1 according to the embodiment of the present invention as an example (prototype example) by a 0.35 μm, 2-poly, 4-metal, standard CMOS process. For comparison, a two-stage comparator circuit according to a conventional example was also designed and manufactured as a prototype. A comparator circuit 1 according to the embodiment, the area of the two-stage type comparator according to the conventional example becomes 3600Myuemu ² and 2700Myuemu ^2, respectively. The ratio of 1: K: K ′ was designed to be 1: 2: 3. As measurement conditions, the power supply voltage Vdd, the input reference voltage, and the input sine wave signal were 3.0 V, 1.5 V, and 1.5 + 0.05 × sin 2πf _IN t, respectively.

FIG. 4 is an experimental result of the comparator circuit 1 according to the embodiment (prototype example) of FIG. 1 and the conventional comparator circuit of FIG. 8, and FIG. 4 (a) is an input reference voltage when the input frequency is 10 kHz. _{(V iN} +), the output voltage of the example (prop.) and a measured waveform diagram showing an output voltage (conv. (2stage)) of the conventional example, FIG. 4 (b) input when the input frequency is 20kHz It is a measured waveform diagram which shows a reference voltage (V _{IN +} ), an output voltage (prop.) Of an example, and an output voltage (conv. (2 stage)) of a conventional example. Here, the bias current I _REF was set to 30 nA. As is clear from FIG. 4A, it was confirmed that both comparator circuits can accurately generate output pulses under the condition of an input frequency of 10 kHz. The rise of the output voltage of the conventional two-stage comparator circuit is significantly delayed. This is because the bias current is as small as 30 nA, so that the bias current cannot charge the output voltage in the conventional two-stage comparator. On the other hand, the comparator circuit 1 according to the embodiment operates without causing a delay. As is clear from FIG. 4B, the two-stage comparator circuit according to the conventional example does not operate correctly under the condition where the input frequency is 20 kHz. This is because the delay of the comparator circuit exceeds the period of the input sine wave. However, it was confirmed that the comparator circuit 1 according to the example can operate correctly even under this condition.

FIG. 5 is a graph showing experimental results of the comparator circuit according to the example and the conventional example, and showing the maximum operating frequency f _max with respect to the bias current I _REF . Here, f _max is the maximum frequency at which the comparator can generate an output pulse. As is apparent from FIG. 5, as the bias current I _REF increases, the maximum frequency _fmax of each comparator circuit also increases. The maximum operating frequency f _max of the comparator circuit according to the example and the conventional example at the bias current I _REF = 10 nA is 40 kHz and 5 kHz, respectively. The comparator circuit 1 according to the embodiment can operate 8 times faster than the two-stage comparator circuit according to the conventional example. Further, the standby current of the comparator circuit 1 according to the example at the bias current I _REF = 10 nA was 18.9 nA. Further, FIG. 5 shows that the proposed comparator can operate with a lower bias current I _REF when the input frequency is fixed.

FIG. 6 is a graph showing experimental results of the comparator circuit according to the example and the conventional example, and showing the current consumption with respect to the input frequency. Here, the bias currents I _REF of the comparator circuit 1 according to the example and the comparator circuit according to the conventional example are set to 33 nA and 50 nA, respectively. The bias current I _REF was set so that the consumption current of each comparator circuit was the same at an input frequency of 10 kHz. In this state, the current consumption of both comparator circuits was 151 nA. When the input frequency is lowered, the current consumption of the comparator circuit according to the embodiment is lower than the current consumption of the two-stage comparator circuit according to the conventional example.

  FIG. 7 is a graph showing experimental results of the comparator circuit according to the example and the conventional example, and showing the duty ratio of the output pulse with respect to the input frequency. FIG. 7 shows the duty ratio of the output pulse of the comparator circuit in the same input frequency region as FIG. As is apparent from FIG. 7, the duty ratio of the comparator circuit 1 according to the example is almost 50%. However, the duty ratio of the two-stage comparator according to the conventional example decreases as the input frequency increases. Since the bias current cannot charge the output, the rise of the output is delayed as the input frequency increases. This result is consistent with the result of FIG.

  FIG. 10 is a table showing performance specifications of the comparator circuit according to the example and the conventional example. From this, it was confirmed that the comparator circuit 1 according to the example can realize the operation with high speed and low power consumption. This comparator circuit 1 is very useful for low power consumption LSI applications.

  As described above, in the embodiment of the present invention, the ultra-low power consumption comparator circuit 1 using the input differential pair and the adaptive bias current generation circuit 12 has been proposed. The input differential pair and the adaptive bias current generation circuit 12 generate an operating current, and the latch circuit 13 controls the operations of the input differential pair and the adaptive bias current generation circuit 12 so that power consumption can be suppressed. Only when the input signal level and the logic of the latch circuit 13 do not match each other, the input differential pair and the adaptive bias current generation circuit 12 and the latch circuit 13 operate. Therefore, the comparator circuit according to the embodiment realizes high speed and low power consumption. can do. From the measurement results, it was confirmed that the comparator circuit 1 operates at high speed and low power consumption. The standby current was 18.9 nA when the bias current was 10 nA, and the power consumption was 88.5 nW at an input frequency of 1 kHz and a power supply voltage of 3 V.

  As described above in detail, it is possible to provide a comparator circuit capable of reducing power consumption at a higher speed than in the prior art.

1 ... Control circuit,
2 ... Buffer circuit,
11: Bias current generation circuit,
12: Input differential pair and adaptive bias current generation circuit,
13 ... Latch circuit,
14 ... Current generation circuit using current mirror,
20: Reference current source,
21, 22 ... input terminals,
23, 24 ... output terminals,
M _{P1 to} M _P10 , M _PB1 , M _PB2 , Q1 to Q4... P channel MOS transistor,
M _{N1 to} M _N10 , M _SW1 , M _SW2 , Q5, Q6... N channel MOS transistor.

Claims (6)

In accordance with the two input voltages input, in any one MOS transistor of the input differential pair composed of the first and second MOS transistors, an adaptive bias current is generated by a loop including the one MOS transistor and the switch transistor. An input differential pair and an adaptive bias current generation circuit for generating
A latch circuit for controlling the input differential pair and the adaptive bias current generation circuit by determining latch logic of two output voltages according to an initial state and the two input voltages and controlling the switch transistor;
The latch circuit controls the input differential pair and the adaptive bias current generation circuit to generate the adaptive bias current when the latch logic of the two output voltages and the two input voltages do not match each other,
The latch circuit detects a current corresponding to the adaptive bias current, changes a latch logic, and then switches the switch transistor from on to off so as to cut off the adaptive bias current . And a comparator circuit for controlling an adaptive bias current generating circuit. The input differential pair and the adaptive bias current generation circuit include first and second loops,
The first loop includes the first MOS transistor, the first switch transistor, and third and fourth MOS transistors, and the aspect ratio of the fourth MOS transistor is the aspect ratio of the third MOS transistor. A first current mirror circuit configured to be larger than the ratio is connected in series;
The second loop includes the second MOS transistor, the second switch transistor, and the fifth and sixth MOS transistors, and the aspect ratio of the sixth MOS transistor is the aspect ratio of the fifth MOS transistor. A second current mirror circuit configured to be greater than the ratio is connected in series,
2. The comparator circuit according to claim 1, wherein the adaptive bias current is generated by the first or second current mirror circuit. The third MOS transistor is connected in series to the first MOS transistor,
The fifth MOS transistor is connected in series to the second MOS transistor,
The input differential pair and the adaptive bias current generation circuit are:
A seventh MOS transistor that detects a current flowing through the third MOS transistor and outputs a current to an input differential pair including the first and second transistors;
An eighth MOS transistor that detects a current flowing through the fifth MOS transistor and outputs a current to an input differential pair including the first and second transistors;
A ninth MOS transistor connected in parallel with the third MOS transistor;
A tenth MOS transistor connected in parallel with the fifth MOS transistor;
The ninth MOS transistor and the tenth MOS transistor are cross-gate connected, and the first detection voltage or the second detection voltage is detected with respect to one of the two input voltages. 3. The comparator circuit according to claim 2, wherein the voltage includes a positive feedback hysteresis circuit having a hysteresis characteristic.   The input differential pair and the adaptive bias current generation circuit are configured such that when the two input voltages substantially coincide with each other, or when both the first and second switch transistors are turned on, 4. The comparator circuit according to claim 2, further comprising a circuit for reducing a current flowing through the second loop.   5. The comparator circuit according to claim 1, wherein the comparator circuit includes only a CMOS circuit. 6.   6. The comparator circuit according to claim 1, further comprising a buffer circuit connected to a subsequent stage of the latch circuit and buffering and amplifying the output voltage of the latch circuit. .

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